[PATCH] zd1211rw: Consistency for address space constants
The zd1211rw address space has confused me once too many times. This patch introduces the following naming notation: Memory space is split into segments (cr, fw, eeprom) and segments may contain components (e.g. boot code inside eeprom). These names are arbitrary and only for the description below: x_START: Absolute address of segment start (previously these were named such as CR_BASE_OFFSET, but they weren't really offsets unless you were considering them as an offset to 0) x_LEN: Segment length x_y_LEN: Length of component y of segment x x_y_OFFSET: Relative address of component y into segment x. The absolute address for this component is (x_START + x_y_OFFSET) I also renamed EEPROM registers to EEPROM data. These 'registers' can't be written to using standard I/O and really represent predefined data from the vendor. Signed-off-by: Daniel Drake <dsd@gentoo.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Daniel Drake
Jeff Garzik
parent
a2bdcc6792
commit
ee30276774
3 changed files with 74 additions and 63 deletions
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@ -594,49 +594,49 @@
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/*
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* Upper 16 bit contains the regulatory domain.
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*/
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#define E2P_SUBID E2P_REG(0x00)
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#define E2P_POD E2P_REG(0x02)
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#define E2P_MAC_ADDR_P1 E2P_REG(0x04)
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#define E2P_MAC_ADDR_P2 E2P_REG(0x06)
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#define E2P_PWR_CAL_VALUE1 E2P_REG(0x08)
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#define E2P_PWR_CAL_VALUE2 E2P_REG(0x0a)
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#define E2P_PWR_CAL_VALUE3 E2P_REG(0x0c)
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#define E2P_PWR_CAL_VALUE4 E2P_REG(0x0e)
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#define E2P_PWR_INT_VALUE1 E2P_REG(0x10)
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#define E2P_PWR_INT_VALUE2 E2P_REG(0x12)
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#define E2P_PWR_INT_VALUE3 E2P_REG(0x14)
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#define E2P_PWR_INT_VALUE4 E2P_REG(0x16)
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#define E2P_SUBID E2P_DATA(0x00)
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#define E2P_POD E2P_DATA(0x02)
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#define E2P_MAC_ADDR_P1 E2P_DATA(0x04)
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#define E2P_MAC_ADDR_P2 E2P_DATA(0x06)
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#define E2P_PWR_CAL_VALUE1 E2P_DATA(0x08)
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#define E2P_PWR_CAL_VALUE2 E2P_DATA(0x0a)
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#define E2P_PWR_CAL_VALUE3 E2P_DATA(0x0c)
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#define E2P_PWR_CAL_VALUE4 E2P_DATA(0x0e)
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#define E2P_PWR_INT_VALUE1 E2P_DATA(0x10)
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#define E2P_PWR_INT_VALUE2 E2P_DATA(0x12)
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#define E2P_PWR_INT_VALUE3 E2P_DATA(0x14)
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#define E2P_PWR_INT_VALUE4 E2P_DATA(0x16)
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/* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30)
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* also only 11 channels. */
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#define E2P_ALLOWED_CHANNEL E2P_REG(0x18)
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#define E2P_ALLOWED_CHANNEL E2P_DATA(0x18)
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#define E2P_PHY_REG E2P_REG(0x1a)
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#define E2P_DEVICE_VER E2P_REG(0x20)
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#define E2P_36M_CAL_VALUE1 E2P_REG(0x28)
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#define E2P_36M_CAL_VALUE2 E2P_REG(0x2a)
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#define E2P_36M_CAL_VALUE3 E2P_REG(0x2c)
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#define E2P_36M_CAL_VALUE4 E2P_REG(0x2e)
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#define E2P_11A_INT_VALUE1 E2P_REG(0x30)
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#define E2P_11A_INT_VALUE2 E2P_REG(0x32)
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#define E2P_11A_INT_VALUE3 E2P_REG(0x34)
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#define E2P_11A_INT_VALUE4 E2P_REG(0x36)
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#define E2P_48M_CAL_VALUE1 E2P_REG(0x38)
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#define E2P_48M_CAL_VALUE2 E2P_REG(0x3a)
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#define E2P_48M_CAL_VALUE3 E2P_REG(0x3c)
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#define E2P_48M_CAL_VALUE4 E2P_REG(0x3e)
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#define E2P_48M_INT_VALUE1 E2P_REG(0x40)
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#define E2P_48M_INT_VALUE2 E2P_REG(0x42)
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#define E2P_48M_INT_VALUE3 E2P_REG(0x44)
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#define E2P_48M_INT_VALUE4 E2P_REG(0x46)
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#define E2P_54M_CAL_VALUE1 E2P_REG(0x48) /* ??? */
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#define E2P_54M_CAL_VALUE2 E2P_REG(0x4a)
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#define E2P_54M_CAL_VALUE3 E2P_REG(0x4c)
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#define E2P_54M_CAL_VALUE4 E2P_REG(0x4e)
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#define E2P_54M_INT_VALUE1 E2P_REG(0x50)
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#define E2P_54M_INT_VALUE2 E2P_REG(0x52)
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#define E2P_54M_INT_VALUE3 E2P_REG(0x54)
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#define E2P_54M_INT_VALUE4 E2P_REG(0x56)
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#define E2P_PHY_REG E2P_DATA(0x1a)
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#define E2P_DEVICE_VER E2P_DATA(0x20)
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#define E2P_36M_CAL_VALUE1 E2P_DATA(0x28)
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#define E2P_36M_CAL_VALUE2 E2P_DATA(0x2a)
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#define E2P_36M_CAL_VALUE3 E2P_DATA(0x2c)
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#define E2P_36M_CAL_VALUE4 E2P_DATA(0x2e)
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#define E2P_11A_INT_VALUE1 E2P_DATA(0x30)
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#define E2P_11A_INT_VALUE2 E2P_DATA(0x32)
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#define E2P_11A_INT_VALUE3 E2P_DATA(0x34)
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#define E2P_11A_INT_VALUE4 E2P_DATA(0x36)
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#define E2P_48M_CAL_VALUE1 E2P_DATA(0x38)
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#define E2P_48M_CAL_VALUE2 E2P_DATA(0x3a)
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#define E2P_48M_CAL_VALUE3 E2P_DATA(0x3c)
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#define E2P_48M_CAL_VALUE4 E2P_DATA(0x3e)
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#define E2P_48M_INT_VALUE1 E2P_DATA(0x40)
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#define E2P_48M_INT_VALUE2 E2P_DATA(0x42)
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#define E2P_48M_INT_VALUE3 E2P_DATA(0x44)
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#define E2P_48M_INT_VALUE4 E2P_DATA(0x46)
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#define E2P_54M_CAL_VALUE1 E2P_DATA(0x48) /* ??? */
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#define E2P_54M_CAL_VALUE2 E2P_DATA(0x4a)
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#define E2P_54M_CAL_VALUE3 E2P_DATA(0x4c)
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#define E2P_54M_CAL_VALUE4 E2P_DATA(0x4e)
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#define E2P_54M_INT_VALUE1 E2P_DATA(0x50)
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#define E2P_54M_INT_VALUE2 E2P_DATA(0x52)
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#define E2P_54M_INT_VALUE3 E2P_DATA(0x54)
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#define E2P_54M_INT_VALUE4 E2P_DATA(0x56)
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/* All 16 bit values */
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#define FW_FIRMWARE_VER FW_REG(0)
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@ -653,20 +653,33 @@
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/* 0x2 - link led on? */
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enum {
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CR_BASE_OFFSET = 0x9000,
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FW_START_OFFSET = 0xee00,
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FW_BASE_ADDR_OFFSET = FW_START_OFFSET + 0x1d,
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EEPROM_START_OFFSET = 0xf800,
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EEPROM_SIZE = 0x800, /* words */
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LOAD_CODE_SIZE = 0xe, /* words */
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LOAD_VECT_SIZE = 0x10000 - 0xfff7, /* words */
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EEPROM_REGS_OFFSET = LOAD_CODE_SIZE + LOAD_VECT_SIZE,
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EEPROM_REGS_SIZE = 0x7e, /* words */
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E2P_BASE_OFFSET = EEPROM_START_OFFSET +
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EEPROM_REGS_OFFSET,
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};
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/* CONTROL REGISTERS */
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CR_START = 0x9000,
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#define FW_REG_TABLE_ADDR USB_ADDR(FW_START_OFFSET + 0x1d)
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/* FIRMWARE */
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FW_START = 0xee00,
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/* The word at this offset contains the base address of the FW_REG
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* registers */
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FW_REGS_ADDR_OFFSET = 0x1d,
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/* EEPROM */
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E2P_START = 0xf800,
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E2P_LEN = 0x800,
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/* EEPROM layout */
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E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */
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E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */
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/* E2P_DATA indexes into this */
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E2P_DATA_LEN = 0x7e, /* base 0xf817 */
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E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */
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E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */
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/* Some precomputed offsets into the EEPROM */
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E2P_DATA_OFFSET = E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN,
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E2P_BOOT_CODE_OFFSET = E2P_DATA_OFFSET + E2P_DATA_LEN,
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};
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enum {
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/* indices for ofdm_cal_values */
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@ -55,7 +55,7 @@ enum {
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#define ZD_NULL_ADDR ((zd_addr_t)0)
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#define USB_REG(offset) ZD_ADDR(USB_BASE, offset) /* word addressing */
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#define CTL_REG(offset) ZD_ADDR(CR_BASE, offset) /* byte addressing */
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#define E2P_REG(offset) ZD_ADDR(E2P_BASE, offset) /* word addressing */
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#define E2P_DATA(offset) ZD_ADDR(E2P_BASE, offset) /* word addressing */
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#define FW_REG(offset) ZD_ADDR(FW_BASE, offset) /* word addressing */
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static inline zd_addr_t zd_inc_word(zd_addr_t addr)
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@ -152,10 +152,10 @@ static u16 usb_addr(struct zd_usb *usb, zd_addr_t addr)
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switch (base) {
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case CR_BASE:
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offset += CR_BASE_OFFSET;
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offset += CR_START;
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break;
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case E2P_BASE:
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offset += E2P_BASE_OFFSET;
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offset += E2P_START + E2P_DATA_OFFSET;
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break;
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case FW_BASE:
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offset += usb->fw_base_offset;
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@ -297,14 +297,13 @@ static int handle_version_mismatch(struct usb_device *udev, u8 device_type,
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if (r)
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goto error;
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r = upload_code(udev, ur_fw->data, ur_fw->size, FW_START_OFFSET,
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REBOOT);
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r = upload_code(udev, ur_fw->data, ur_fw->size, FW_START, REBOOT);
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if (r)
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goto error;
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offset = ((EEPROM_REGS_OFFSET + EEPROM_REGS_SIZE) * sizeof(u16));
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offset = (E2P_BOOT_CODE_OFFSET * sizeof(u16));
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r = upload_code(udev, ub_fw->data + offset, ub_fw->size - offset,
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E2P_BASE_OFFSET + EEPROM_REGS_SIZE, REBOOT);
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E2P_START + E2P_BOOT_CODE_OFFSET, REBOOT);
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/* At this point, the vendor driver downloads the whole firmware
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* image, hacks around with version IDs, and uploads it again,
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@ -333,7 +332,7 @@ static int upload_firmware(struct usb_device *udev, u8 device_type)
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if (r)
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goto error;
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fw_bcdDevice = get_word(ub_fw->data, EEPROM_REGS_OFFSET);
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fw_bcdDevice = get_word(ub_fw->data, E2P_DATA_OFFSET);
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if (fw_bcdDevice != bcdDevice) {
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dev_info(&udev->dev,
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@ -359,8 +358,7 @@ static int upload_firmware(struct usb_device *udev, u8 device_type)
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if (r)
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goto error;
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r = upload_code(udev, uph_fw->data, uph_fw->size, FW_START_OFFSET,
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REBOOT);
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r = upload_code(udev, uph_fw->data, uph_fw->size, FW_START, REBOOT);
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if (r) {
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dev_err(&udev->dev,
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"Could not upload firmware code uph. Error number %d\n",
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@ -899,7 +897,7 @@ int zd_usb_init_hw(struct zd_usb *usb)
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ZD_ASSERT(mutex_is_locked(&chip->mutex));
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r = zd_ioread16_locked(chip, &usb->fw_base_offset,
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USB_REG((u16)FW_BASE_ADDR_OFFSET));
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USB_REG(FW_START + FW_REGS_ADDR_OFFSET));
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if (r)
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return r;
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dev_dbg_f(zd_usb_dev(usb), "fw_base_offset: %#06hx\n",
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