firewire: Add phy register defines.
Signed-off-by: Marc Butler <marc@adaptivecode.com> Signed-off-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> (added whitespace)
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2 changed files with 16 additions and 4 deletions
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@ -395,9 +395,9 @@ fw_card_add(struct fw_card *card,
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card->link_speed = link_speed;
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card->link_speed = link_speed;
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card->guid = guid;
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card->guid = guid;
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/* FIXME: add #define's for phy registers. */
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/* Activate link_on bit and contender bit in our self ID packets.*/
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/* Activate link_on bit and contender bit in our self ID packets.*/
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if (card->driver->update_phy_reg(card, 4, 0, 0x80 | 0x40) < 0)
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if (card->driver->update_phy_reg(card, 4, 0,
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PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
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return -EIO;
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return -EIO;
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/* The subsystem grabs a reference when the card is added and
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/* The subsystem grabs a reference when the card is added and
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@ -483,7 +483,8 @@ static struct fw_card_driver dummy_driver = {
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void
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void
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fw_core_remove_card(struct fw_card *card)
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fw_core_remove_card(struct fw_card *card)
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{
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{
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card->driver->update_phy_reg(card, 4, 0x80 | 0x40, 0);
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card->driver->update_phy_reg(card, 4,
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PHY_LINK_ACTIVE | PHY_CONTENDER, 0);
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fw_core_initiate_bus_reset(card, 1);
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fw_core_initiate_bus_reset(card, 1);
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down_write(&fw_bus_type.subsys.rwsem);
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down_write(&fw_bus_type.subsys.rwsem);
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@ -531,6 +532,11 @@ EXPORT_SYMBOL(fw_card_put);
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int
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int
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fw_core_initiate_bus_reset(struct fw_card *card, int short_reset)
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fw_core_initiate_bus_reset(struct fw_card *card, int short_reset)
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{
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{
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return card->driver->update_phy_reg(card, short_reset ? 5 : 1, 0, 0x40);
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int reg = short_reset ? 5 : 1;
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/* The following values happen to be the same bit. However be
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* explicit for clarity. */
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int bit = short_reset ? PHY_BUS_SHORT_RESET : PHY_BUS_RESET;
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return card->driver->update_phy_reg(card, reg, 0, bit);
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}
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}
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EXPORT_SYMBOL(fw_core_initiate_bus_reset);
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EXPORT_SYMBOL(fw_core_initiate_bus_reset);
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@ -107,6 +107,12 @@
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#define PHY_PACKET_LINK_ON 0x1
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#define PHY_PACKET_LINK_ON 0x1
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#define PHY_PACKET_SELF_ID 0x2
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#define PHY_PACKET_SELF_ID 0x2
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/* Bit fields _within_ the PHY registers. */
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#define PHY_LINK_ACTIVE 0x80
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#define PHY_CONTENDER 0x40
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#define PHY_BUS_RESET 0x40
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#define PHY_BUS_SHORT_RESET 0x40
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#define CSR_REGISTER_BASE 0xfffff0000000ULL
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#define CSR_REGISTER_BASE 0xfffff0000000ULL
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/* register offsets relative to CSR_REGISTER_BASE */
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/* register offsets relative to CSR_REGISTER_BASE */
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