ARM: at91: make rtt register base soc independant
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
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9627b200ed
commit
eab5fd67d6
12 changed files with 21 additions and 21 deletions
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@ -670,8 +670,8 @@ static void __init at91_add_device_tc(void) { }
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static struct resource rtt_resources[] = {
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{
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.start = AT91_BASE_SYS + AT91_RTT,
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.end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
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.start = AT91CAP9_BASE_RTT,
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.end = AT91CAP9_BASE_RTT + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@ -714,8 +714,8 @@ static void __init at91_add_device_tc(void) { }
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static struct resource rtt_resources[] = {
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{
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.start = AT91_BASE_SYS + AT91_RTT,
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.end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
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.start = AT91SAM9260_BASE_RTT,
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.end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@ -600,8 +600,8 @@ static void __init at91_add_device_tc(void) { }
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static struct resource rtt_resources[] = {
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{
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.start = AT91_BASE_SYS + AT91_RTT,
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.end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
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.start = AT91SAM9261_BASE_RTT,
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.end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@ -956,8 +956,8 @@ static void __init at91_add_device_tc(void) { }
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static struct resource rtt0_resources[] = {
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{
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.start = AT91_BASE_SYS + AT91_RTT0,
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.end = AT91_BASE_SYS + AT91_RTT0 + SZ_16 - 1,
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.start = AT91SAM9263_BASE_RTT0,
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.end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@ -971,8 +971,8 @@ static struct platform_device at91sam9263_rtt0_device = {
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static struct resource rtt1_resources[] = {
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{
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.start = AT91_BASE_SYS + AT91_RTT1,
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.end = AT91_BASE_SYS + AT91_RTT1 + SZ_16 - 1,
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.start = AT91SAM9263_BASE_RTT1,
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.end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@ -1081,8 +1081,8 @@ void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
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static struct resource rtt_resources[] = {
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{
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.start = AT91_BASE_SYS + AT91_RTT,
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.end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
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.start = AT91SAM9G45_BASE_RTT,
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.end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@ -685,8 +685,8 @@ static void __init at91_add_device_rtc(void) {}
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static struct resource rtt_resources[] = {
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{
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.start = AT91_BASE_SYS + AT91_RTT,
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.end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
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.start = AT91SAM9RL_BASE_RTT,
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.end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@ -89,7 +89,6 @@
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
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@ -102,6 +101,7 @@
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#define AT91CAP9_BASE_PIOB 0xfffff400
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#define AT91CAP9_BASE_PIOC 0xfffff600
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#define AT91CAP9_BASE_PIOD 0xfffff800
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#define AT91CAP9_BASE_RTT 0xfffffd20
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#define AT91_USART0 AT91CAP9_BASE_US0
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#define AT91_USART1 AT91CAP9_BASE_US1
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@ -89,7 +89,6 @@
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
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@ -98,6 +97,7 @@
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#define AT91SAM9260_BASE_PIOA 0xfffff400
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#define AT91SAM9260_BASE_PIOB 0xfffff600
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#define AT91SAM9260_BASE_PIOC 0xfffff800
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#define AT91SAM9260_BASE_RTT 0xfffffd20
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#define AT91_USART0 AT91SAM9260_BASE_US0
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#define AT91_USART1 AT91SAM9260_BASE_US1
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@ -73,7 +73,6 @@
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
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@ -81,6 +80,7 @@
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#define AT91SAM9261_BASE_PIOA 0xfffff400
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#define AT91SAM9261_BASE_PIOB 0xfffff600
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#define AT91SAM9261_BASE_PIOC 0xfffff800
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#define AT91SAM9261_BASE_RTT 0xfffffd20
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#define AT91_USART0 AT91SAM9261_BASE_US0
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#define AT91_USART1 AT91SAM9261_BASE_US1
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@ -85,10 +85,8 @@
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
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#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
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#define AT91SAM9263_BASE_ECC0 0xffffe000
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@ -98,6 +96,8 @@
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#define AT91SAM9263_BASE_PIOC 0xfffff600
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#define AT91SAM9263_BASE_PIOD 0xfffff800
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#define AT91SAM9263_BASE_PIOE 0xfffffa00
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#define AT91SAM9263_BASE_RTT0 0xfffffd20
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#define AT91SAM9263_BASE_RTT1 0xfffffd50
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#define AT91_USART0 AT91SAM9263_BASE_US0
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#define AT91_USART1 AT91SAM9263_BASE_US1
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@ -95,7 +95,6 @@
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
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@ -108,6 +107,7 @@
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#define AT91SAM9G45_BASE_PIOC 0xfffff600
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#define AT91SAM9G45_BASE_PIOD 0xfffff800
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#define AT91SAM9G45_BASE_PIOE 0xfffffa00
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#define AT91SAM9G45_BASE_RTT 0xfffffd20
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#define AT91_USART0 AT91SAM9G45_BASE_US0
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#define AT91_USART1 AT91SAM9G45_BASE_US1
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@ -78,7 +78,6 @@
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
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@ -91,6 +90,7 @@
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#define AT91SAM9RL_BASE_PIOB 0xfffff600
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#define AT91SAM9RL_BASE_PIOC 0xfffff800
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#define AT91SAM9RL_BASE_PIOD 0xfffffa00
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#define AT91SAM9RL_BASE_RTT 0xfffffd20
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#define AT91_USART0 AT91SAM9RL_BASE_US0
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#define AT91_USART1 AT91SAM9RL_BASE_US1
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