netxen: improve pci memory access
o Access on card memory through memory controller (agent) rather than moving small pci window around. Clean up the code for moving windows around. o Restrict memory accesss to 64 bit, currently only firmware download uses this. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
f78c0850d2
commit
ea6828b8aa
3 changed files with 93 additions and 266 deletions
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@ -552,8 +552,8 @@ struct netxen_hardware_context {
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int qdr_sn_window;
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int qdr_sn_window;
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int ddr_mn_window;
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int ddr_mn_window;
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unsigned long mn_win_crb;
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u32 mn_win_crb;
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unsigned long ms_win_crb;
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u32 ms_win_crb;
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u8 cut_through;
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u8 cut_through;
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u8 revision_id;
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u8 revision_id;
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@ -1279,25 +1279,6 @@ netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
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return data;
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return data;
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}
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}
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/*
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* check memory access boundary.
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* used by test agent. support ddr access only for now
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*/
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static unsigned long
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netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
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unsigned long long addr, int size)
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{
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if (!ADDR_IN_RANGE(addr,
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NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
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!ADDR_IN_RANGE(addr+size-1,
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NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
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((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
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return 0;
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}
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return 1;
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}
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static int netxen_pci_set_window_warning_count;
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static int netxen_pci_set_window_warning_count;
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static unsigned long
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static unsigned long
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@ -1424,10 +1405,8 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
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/* DDR network side */
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/* DDR network side */
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window = MN_WIN(addr);
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window = MN_WIN(addr);
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adapter->ahw.ddr_mn_window = window;
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adapter->ahw.ddr_mn_window = window;
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NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
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NXWR32(adapter, adapter->ahw.mn_win_crb, window);
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window);
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win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
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win_read = NXRD32(adapter,
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adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
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if ((win_read << 17) != window) {
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if ((win_read << 17) != window) {
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printk(KERN_INFO "Written MNwin (0x%x) != "
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printk(KERN_INFO "Written MNwin (0x%x) != "
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"Read MNwin (0x%x)\n", window, win_read);
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"Read MNwin (0x%x)\n", window, win_read);
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@ -1442,10 +1421,8 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
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window = OCM_WIN(addr);
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window = OCM_WIN(addr);
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adapter->ahw.ddr_mn_window = window;
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adapter->ahw.ddr_mn_window = window;
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NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
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NXWR32(adapter, adapter->ahw.mn_win_crb, window);
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window);
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win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
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win_read = NXRD32(adapter,
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adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
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if ((win_read >> 7) != window) {
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if ((win_read >> 7) != window) {
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printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
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printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
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"Read OCMwin (0x%x)\n",
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"Read OCMwin (0x%x)\n",
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@ -1458,10 +1435,8 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
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/* QDR network side */
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/* QDR network side */
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window = MS_WIN(addr);
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window = MS_WIN(addr);
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adapter->ahw.qdr_sn_window = window;
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adapter->ahw.qdr_sn_window = window;
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NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
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NXWR32(adapter, adapter->ahw.ms_win_crb, window);
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window);
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win_read = NXRD32(adapter, adapter->ahw.ms_win_crb);
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win_read = NXRD32(adapter,
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adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
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if (win_read != window) {
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if (win_read != window) {
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printk(KERN_INFO "%s: Written MSwin (0x%x) != "
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printk(KERN_INFO "%s: Written MSwin (0x%x) != "
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"Read MSwin (0x%x)\n",
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"Read MSwin (0x%x)\n",
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@ -1484,177 +1459,6 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
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return addr;
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return addr;
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}
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}
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static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
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unsigned long long addr)
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{
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int window;
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unsigned long long qdr_max;
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if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
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qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
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else
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qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
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if (ADDR_IN_RANGE(addr,
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NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
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/* DDR network side */
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BUG(); /* MN access can not come here */
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} else if (ADDR_IN_RANGE(addr,
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NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
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return 1;
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} else if (ADDR_IN_RANGE(addr,
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NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
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return 1;
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} else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
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/* QDR network side */
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window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
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if (adapter->ahw.qdr_sn_window == window)
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return 1;
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}
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return 0;
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}
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static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
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u64 off, void *data, int size)
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{
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unsigned long flags;
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void __iomem *addr, *mem_ptr = NULL;
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int ret = 0;
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u64 start;
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unsigned long mem_base;
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unsigned long mem_page;
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write_lock_irqsave(&adapter->adapter_lock, flags);
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/*
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* If attempting to access unknown address or straddle hw windows,
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* do not access.
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*/
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start = adapter->pci_set_window(adapter, off);
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if ((start == -1UL) ||
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(netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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printk(KERN_ERR "%s out of bound pci memory access. "
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"offset is 0x%llx\n", netxen_nic_driver_name,
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(unsigned long long)off);
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return -1;
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}
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addr = pci_base_offset(adapter, start);
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if (!addr) {
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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mem_base = pci_resource_start(adapter->pdev, 0);
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mem_page = start & PAGE_MASK;
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/* Map two pages whenever user tries to access addresses in two
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consecutive pages.
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*/
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if (mem_page != ((start + size - 1) & PAGE_MASK))
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mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
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else
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mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
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if (mem_ptr == NULL) {
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*(uint8_t *)data = 0;
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return -1;
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}
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addr = mem_ptr;
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addr += start & (PAGE_SIZE - 1);
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write_lock_irqsave(&adapter->adapter_lock, flags);
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}
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switch (size) {
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case 1:
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*(uint8_t *)data = readb(addr);
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break;
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case 2:
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*(uint16_t *)data = readw(addr);
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break;
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case 4:
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*(uint32_t *)data = readl(addr);
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break;
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case 8:
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*(uint64_t *)data = readq(addr);
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break;
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default:
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ret = -1;
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break;
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}
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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if (mem_ptr)
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iounmap(mem_ptr);
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return ret;
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}
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static int
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netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
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void *data, int size)
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{
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unsigned long flags;
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void __iomem *addr, *mem_ptr = NULL;
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int ret = 0;
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u64 start;
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unsigned long mem_base;
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unsigned long mem_page;
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write_lock_irqsave(&adapter->adapter_lock, flags);
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/*
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* If attempting to access unknown address or straddle hw windows,
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* do not access.
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*/
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start = adapter->pci_set_window(adapter, off);
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if ((start == -1UL) ||
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(netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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printk(KERN_ERR "%s out of bound pci memory access. "
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"offset is 0x%llx\n", netxen_nic_driver_name,
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(unsigned long long)off);
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return -1;
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}
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addr = pci_base_offset(adapter, start);
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if (!addr) {
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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mem_base = pci_resource_start(adapter->pdev, 0);
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mem_page = start & PAGE_MASK;
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/* Map two pages whenever user tries to access addresses in two
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* consecutive pages.
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*/
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if (mem_page != ((start + size - 1) & PAGE_MASK))
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mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
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else
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mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
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if (mem_ptr == NULL)
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return -1;
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addr = mem_ptr;
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addr += start & (PAGE_SIZE - 1);
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write_lock_irqsave(&adapter->adapter_lock, flags);
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}
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switch (size) {
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case 1:
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writeb(*(uint8_t *)data, addr);
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break;
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case 2:
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writew(*(uint16_t *)data, addr);
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break;
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case 4:
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writel(*(uint32_t *)data, addr);
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break;
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case 8:
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writeq(*(uint64_t *)data, addr);
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break;
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default:
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ret = -1;
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break;
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}
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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if (mem_ptr)
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iounmap(mem_ptr);
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return ret;
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}
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#define MAX_CTL_CHECK 1000
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#define MAX_CTL_CHECK 1000
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static int
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static int
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@ -1667,19 +1471,28 @@ netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
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uint64_t off8, tmpw, word[2] = {0, 0};
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uint64_t off8, tmpw, word[2] = {0, 0};
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void __iomem *mem_crb;
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void __iomem *mem_crb;
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/*
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if (size != 8)
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* If not MN, go check for MS or invalid.
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return -EIO;
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*/
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if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
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return netxen_nic_pci_mem_write_direct(adapter,
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off, data, size);
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
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NETXEN_ADDR_QDR_NET_MAX_P2)) {
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
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goto correct;
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}
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
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goto correct;
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}
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return -EIO;
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correct:
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off8 = off & 0xfffffff8;
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off8 = off & 0xfffffff8;
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off0 = off & 0x7;
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off0 = off & 0x7;
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sz[0] = (size < (8 - off0)) ? size : (8 - off0);
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sz[0] = (size < (8 - off0)) ? size : (8 - off0);
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sz[1] = size - sz[0];
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sz[1] = size - sz[0];
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loop = ((off0 + size - 1) >> 3) + 1;
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loop = ((off0 + size - 1) >> 3) + 1;
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
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if ((size != 8) || (off0 != 0)) {
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if ((size != 8) || (off0 != 0)) {
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for (i = 0; i < loop; i++) {
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for (i = 0; i < loop; i++) {
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@ -1760,20 +1573,29 @@ netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
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uint64_t off8, val, word[2] = {0, 0};
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uint64_t off8, val, word[2] = {0, 0};
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void __iomem *mem_crb;
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void __iomem *mem_crb;
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if (size != 8)
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return -EIO;
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/*
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
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* If not MN, go check for MS or invalid.
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NETXEN_ADDR_QDR_NET_MAX_P2)) {
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*/
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
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if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
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goto correct;
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return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
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}
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
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goto correct;
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}
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return -EIO;
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correct:
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off8 = off & 0xfffffff8;
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off8 = off & 0xfffffff8;
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off0[0] = off & 0x7;
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off0[0] = off & 0x7;
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off0[1] = 0;
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off0[1] = 0;
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sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
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sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
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sz[1] = size - sz[0];
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sz[1] = size - sz[0];
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loop = ((off0[0] + size - 1) >> 3) + 1;
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loop = ((off0[0] + size - 1) >> 3) + 1;
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
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write_lock_irqsave(&adapter->adapter_lock, flags);
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write_lock_irqsave(&adapter->adapter_lock, flags);
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netxen_nic_pci_change_crbwindow_128M(adapter, 0);
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netxen_nic_pci_change_crbwindow_128M(adapter, 0);
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@ -1847,20 +1669,26 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
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{
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{
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int i, j, ret = 0, loop, sz[2], off0;
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int i, j, ret = 0, loop, sz[2], off0;
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uint32_t temp;
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uint32_t temp;
|
||||||
uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
|
uint64_t off8, tmpw, word[2] = {0, 0};
|
||||||
|
void __iomem *mem_crb;
|
||||||
|
|
||||||
/*
|
if (size != 8)
|
||||||
* If not MN, go check for MS or invalid.
|
return -EIO;
|
||||||
*/
|
|
||||||
if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
|
if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
|
||||||
mem_crb = NETXEN_CRB_QDR_NET;
|
NETXEN_ADDR_QDR_NET_MAX_P3)) {
|
||||||
else {
|
mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
|
||||||
mem_crb = NETXEN_CRB_DDR_NET;
|
goto correct;
|
||||||
if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
|
|
||||||
return netxen_nic_pci_mem_write_direct(adapter,
|
|
||||||
off, data, size);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
|
||||||
|
mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
|
||||||
|
goto correct;
|
||||||
|
}
|
||||||
|
|
||||||
|
return -EIO;
|
||||||
|
|
||||||
|
correct:
|
||||||
off8 = off & 0xfffffff8;
|
off8 = off & 0xfffffff8;
|
||||||
off0 = off & 0x7;
|
off0 = off & 0x7;
|
||||||
sz[0] = (size < (8 - off0)) ? size : (8 - off0);
|
sz[0] = (size < (8 - off0)) ? size : (8 - off0);
|
||||||
|
@ -1906,21 +1734,18 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
|
||||||
*/
|
*/
|
||||||
|
|
||||||
for (i = 0; i < loop; i++) {
|
for (i = 0; i < loop; i++) {
|
||||||
temp = off8 + (i << 3);
|
writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO);
|
||||||
NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
|
writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI);
|
||||||
temp = 0;
|
writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO);
|
||||||
NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
|
writel((word[i] >> 32) & 0xffffffff,
|
||||||
temp = word[i] & 0xffffffff;
|
mem_crb+MIU_TEST_AGT_WRDATA_HI);
|
||||||
NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
|
writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE),
|
||||||
temp = (word[i] >> 32) & 0xffffffff;
|
mem_crb+MIU_TEST_AGT_CTRL);
|
||||||
NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
|
writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE,
|
||||||
temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
|
mem_crb+MIU_TEST_AGT_CTRL);
|
||||||
NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
|
|
||||||
temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
|
|
||||||
NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
|
|
||||||
|
|
||||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||||
temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
|
temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
|
||||||
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -1947,21 +1772,26 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
|
||||||
{
|
{
|
||||||
int i, j = 0, k, start, end, loop, sz[2], off0[2];
|
int i, j = 0, k, start, end, loop, sz[2], off0[2];
|
||||||
uint32_t temp;
|
uint32_t temp;
|
||||||
uint64_t off8, val, mem_crb, word[2] = {0, 0};
|
uint64_t off8, val, word[2] = {0, 0};
|
||||||
|
void __iomem *mem_crb;
|
||||||
|
|
||||||
/*
|
if (size != 8)
|
||||||
* If not MN, go check for MS or invalid.
|
return -EIO;
|
||||||
*/
|
|
||||||
|
|
||||||
if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
|
if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
|
||||||
mem_crb = NETXEN_CRB_QDR_NET;
|
NETXEN_ADDR_QDR_NET_MAX_P3)) {
|
||||||
else {
|
mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
|
||||||
mem_crb = NETXEN_CRB_DDR_NET;
|
goto correct;
|
||||||
if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
|
|
||||||
return netxen_nic_pci_mem_read_direct(adapter,
|
|
||||||
off, data, size);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
|
||||||
|
mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
|
||||||
|
goto correct;
|
||||||
|
}
|
||||||
|
|
||||||
|
return -EIO;
|
||||||
|
|
||||||
|
correct:
|
||||||
off8 = off & 0xfffffff8;
|
off8 = off & 0xfffffff8;
|
||||||
off0[0] = off & 0x7;
|
off0[0] = off & 0x7;
|
||||||
off0[1] = 0;
|
off0[1] = 0;
|
||||||
|
@ -1976,17 +1806,14 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
|
||||||
*/
|
*/
|
||||||
|
|
||||||
for (i = 0; i < loop; i++) {
|
for (i = 0; i < loop; i++) {
|
||||||
temp = off8 + (i << 3);
|
writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO);
|
||||||
NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
|
writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI);
|
||||||
temp = 0;
|
writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL);
|
||||||
NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
|
writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE,
|
||||||
temp = MIU_TA_CTL_ENABLE;
|
mem_crb + MIU_TEST_AGT_CTRL);
|
||||||
NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
|
|
||||||
temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
|
|
||||||
NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
|
|
||||||
|
|
||||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||||
temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
|
temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
|
||||||
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -2001,8 +1828,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
|
||||||
start = off0[i] >> 2;
|
start = off0[i] >> 2;
|
||||||
end = (off0[i] + sz[i] - 1) >> 2;
|
end = (off0[i] + sz[i] - 1) >> 2;
|
||||||
for (k = start; k <= end; k++) {
|
for (k = start; k <= end; k++) {
|
||||||
temp = NXRD32(adapter,
|
temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k));
|
||||||
mem_crb + MIU_TEST_AGT_RDDATA(k));
|
|
||||||
word[i] |= ((uint64_t)temp << (32 * k));
|
word[i] |= ((uint64_t)temp << (32 * k));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -643,9 +643,10 @@ netxen_setup_pci_map(struct netxen_adapter *adapter)
|
||||||
adapter->ahw.ddr_mn_window = 0;
|
adapter->ahw.ddr_mn_window = 0;
|
||||||
adapter->ahw.qdr_sn_window = 0;
|
adapter->ahw.qdr_sn_window = 0;
|
||||||
|
|
||||||
adapter->ahw.mn_win_crb = 0x100000 + PCIX_MN_WINDOW +
|
adapter->ahw.mn_win_crb = NETXEN_PCI_CRBSPACE +
|
||||||
(pci_func * 0x20);
|
0x100000 + PCIX_MN_WINDOW + (pci_func * 0x20);
|
||||||
adapter->ahw.ms_win_crb = 0x100000 + PCIX_SN_WINDOW;
|
adapter->ahw.ms_win_crb = NETXEN_PCI_CRBSPACE +
|
||||||
|
0x100000 + PCIX_SN_WINDOW;
|
||||||
if (pci_func < 4)
|
if (pci_func < 4)
|
||||||
adapter->ahw.ms_win_crb += (pci_func * 0x20);
|
adapter->ahw.ms_win_crb += (pci_func * 0x20);
|
||||||
else
|
else
|
||||||
|
|
Loading…
Reference in a new issue