rtlwifi: Modify wifi.h for rtl8192cu
Further merge of parameters needed for rtl8192cu. In addition, some changes needed for rtl8192se and rtl8192de are included and additional Hungarian notation is removed. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Larry Finger
John W. Linville
parent
18d30067d3
commit
e97b775d9b
2 changed files with 238 additions and 49 deletions
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@ -57,8 +57,6 @@
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#define IQK_MAC_REG_NUM 4
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#define RF90_PATH_MAX 2
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#define CHANNEL_MAX_NUMBER 14
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#define CHANNEL_GROUP_MAX 3
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#define CT_OFFSET_MAC_ADDR 0X16
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@ -78,8 +76,6 @@
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#define CT_OFFSET_CUSTOMER_ID 0x7F
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#define RTL92C_MAX_PATH_NUM 2
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#define CHANNEL_MAX_NUMBER 14
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#define CHANNEL_GROUP_MAX 3
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#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
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enum swchnlcmd_id {
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CMDID_END,
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@ -83,6 +83,19 @@
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#define MAC80211_3ADDR_LEN 24
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#define MAC80211_4ADDR_LEN 30
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#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
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#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
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#define MAX_PG_GROUP 13
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#define CHANNEL_GROUP_MAX_2G 3
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#define CHANNEL_GROUP_IDX_5GL 3
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#define CHANNEL_GROUP_IDX_5GM 6
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#define CHANNEL_GROUP_IDX_5GH 9
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#define CHANNEL_GROUP_MAX_5G 9
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#define CHANNEL_MAX_NUMBER_2G 14
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#define AVG_THERMAL_NUM 8
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/* for early mode */
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#define EM_HDR_LEN 8
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enum intf_type {
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INTF_PCI = 0,
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INTF_USB = 1,
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@ -114,18 +127,37 @@ enum hardware_type {
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HARDWARE_TYPE_RTL8192CU,
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HARDWARE_TYPE_RTL8192DE,
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HARDWARE_TYPE_RTL8192DU,
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HARDWARE_TYPE_RTL8723E,
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HARDWARE_TYPE_RTL8723U,
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/*keep it last*/
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/* keep it last */
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HARDWARE_TYPE_NUM
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};
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#define IS_HARDWARE_TYPE_8192SU(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
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#define IS_HARDWARE_TYPE_8192SE(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
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#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
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#define IS_HARDWARE_TYPE_8192CU(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
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#define IS_HARDWARE_TYPE_8192DE(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
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#define IS_HARDWARE_TYPE_8192DU(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
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#define IS_HARDWARE_TYPE_8723E(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
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#define IS_HARDWARE_TYPE_8723U(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
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#define IS_HARDWARE_TYPE_8192S(rtlhal) \
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(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
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#define IS_HARDWARE_TYPE_8192C(rtlhal) \
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(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
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#define IS_HARDWARE_TYPE_8192D(rtlhal) \
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(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
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#define IS_HARDWARE_TYPE_8723(rtlhal) \
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(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
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enum scan_operation_backup_opt {
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SCAN_OPT_BACKUP = 0,
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@ -324,6 +356,7 @@ enum rf_type {
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RF_1T1R = 0,
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RF_1T2R = 1,
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RF_2T2R = 2,
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RF_2T2R_GREEN = 3,
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};
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enum ht_channel_width {
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@ -408,6 +441,7 @@ enum rtl_var_map {
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RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
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RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
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RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
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RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
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RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
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RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
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RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
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@ -416,7 +450,8 @@ enum rtl_var_map {
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RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
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RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
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RTL_IMR_ROK, /*Receive DMA OK Interrupt */
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RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt|RTL_IMR_TBDOK|RTL_IMR_TBDER)*/
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RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
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* RTL_IMR_TBDER) */
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/*CCK Rates, TxHT = 0 */
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RTL_RC_CCK_RATE1M,
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@ -492,6 +527,19 @@ enum acm_method {
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eAcmWay2_SW = 2,
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};
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enum macphy_mode {
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SINGLEMAC_SINGLEPHY = 0,
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DUALMAC_DUALPHY,
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DUALMAC_SINGLEPHY,
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};
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enum band_type {
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BAND_ON_2_4G = 0,
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BAND_ON_5G,
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BAND_ON_BOTH,
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BANDMAX
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};
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/*aci/aifsn Field.
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Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
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union aci_aifsn {
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@ -625,6 +673,8 @@ struct false_alarm_statistics {
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u32 cnt_rate_illegal;
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u32 cnt_crc8_fail;
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u32 cnt_mcs_fail;
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u32 cnt_fast_fsync_fail;
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u32 cnt_sb_search_fail;
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u32 cnt_ofdm_fail;
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u32 cnt_cck_fail;
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u32 cnt_all;
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@ -712,6 +762,13 @@ struct rtl_rfkill {
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bool rfkill_state; /*0 is off, 1 is on */
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};
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#define IQK_MATRIX_REG_NUM 8
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#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
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struct iqk_matrix_regs {
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bool b_iqk_done;
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long value[1][IQK_MATRIX_REG_NUM];
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};
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struct phy_parameters {
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u16 length;
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u32 *pdata;
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@ -746,8 +803,9 @@ struct rtl_phy {
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u8 current_channel;
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u8 h2c_box_num;
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u8 set_io_inprogress;
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u8 lck_inprogress;
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/*record for power tracking*/
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/* record for power tracking */
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s32 reg_e94;
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s32 reg_e9c;
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s32 reg_ea4;
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@ -764,27 +822,32 @@ struct rtl_phy {
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u32 iqk_mac_backup[IQK_MAC_REG_NUM];
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u32 iqk_bb_backup[10];
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/* Dual mac */
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bool need_iqk;
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struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
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bool rfpi_enable;
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u8 pwrgroup_cnt;
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u8 cck_high_power;
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/* 3 groups of pwr diff by rates*/
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u32 mcs_txpwrlevel_origoffset[4][16];
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/* MAX_PG_GROUP groups of pwr diff by rates */
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u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
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u8 default_initialgain[4];
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/*the current Tx power level*/
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/* the current Tx power level */
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u8 cur_cck_txpwridx;
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u8 cur_ofdm24g_txpwridx;
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u32 rfreg_chnlval[2];
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bool apk_done;
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u32 reg_rf3c[2]; /* pathA / pathB */
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/*fsync*/
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u8 framesync;
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u32 framesync_c34;
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u8 num_total_rfpath;
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struct phy_parameters hwparam_tables[MAX_TAB];
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u16 rf_pathmap;
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};
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#define MAX_TID_COUNT 9
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@ -825,12 +888,11 @@ struct rtl_io {
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int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
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u8 *pdata);
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u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
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u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
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u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
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u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
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u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
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u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
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int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
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u8 *pdata);
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};
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struct rtl_mac {
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@ -862,16 +924,24 @@ struct rtl_mac {
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bool act_scanning;
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u8 cnt_after_linked;
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/*RDG*/ bool rdg_en;
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/* early mode */
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/* skb wait queue */
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struct sk_buff_head skb_waitq[MAX_TID_COUNT];
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u8 earlymode_threshold;
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/*AP*/ u8 bssid[6];
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u8 mcs[16]; /*16 bytes mcs for HT rates.*/
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u32 basic_rates; /*b/g rates*/
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/*RDG*/
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bool rdg_en;
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/*AP*/
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u8 bssid[6];
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u32 vendor;
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u8 mcs[16]; /* 16 bytes mcs for HT rates. */
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u32 basic_rates; /* b/g rates */
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u8 ht_enable;
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u8 sgi_40;
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u8 sgi_20;
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u8 bw_40;
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u8 mode; /*wireless mode*/
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u8 mode; /* wireless mode */
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u8 slot_time;
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u8 short_preamble;
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u8 use_cts_protect;
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@ -882,9 +952,11 @@ struct rtl_mac {
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u8 retry_long;
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u16 assoc_id;
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/*IBSS*/ int beacon_interval;
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/*IBSS*/
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int beacon_interval;
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/*AMPDU*/ u8 min_space_cfg; /*For Min spacing configurations */
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/*AMPDU*/
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u8 min_space_cfg; /*For Min spacing configurations */
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u8 max_mss_density;
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u8 current_ampdu_factor;
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u8 current_ampdu_density;
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@ -899,11 +971,13 @@ struct rtl_hal {
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enum intf_type interface;
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u16 hw_type; /*92c or 92d or 92s and so on */
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u8 ic_class;
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u8 oem_id;
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u32 version; /*version of chip */
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u8 state; /*stop 0, start 1 */
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/*firmware */
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u32 fwsize;
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u8 *pfirmware;
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u16 fw_version;
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u16 fw_subversion;
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@ -912,6 +986,39 @@ struct rtl_hal {
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bool fw_ready;
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/*Reserve page start offset except beacon in TxQ. */
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u8 fw_rsvdpage_startoffset;
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u8 h2c_txcmd_seq;
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/* FW Cmd IO related */
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u16 fwcmd_iomap;
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u32 fwcmd_ioparam;
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bool set_fwcmd_inprogress;
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u8 current_fwcmd_io;
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/**/
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bool driver_going2unload;
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/*AMPDU init min space*/
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u8 minspace_cfg; /*For Min spacing configurations */
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/* Dual mac */
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enum macphy_mode macphymode;
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enum band_type current_bandtype; /* 0:2.4G, 1:5G */
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enum band_type current_bandtypebackup;
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enum band_type bandset;
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/* dual MAC 0--Mac0 1--Mac1 */
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u32 interfaceindex;
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/* just for DualMac S3S4 */
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u8 macphyctl_reg;
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bool earlymode_enable;
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/* Dual mac*/
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bool during_mac0init_radiob;
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bool during_mac1init_radioa;
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bool reloadtxpowerindex;
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/* True if IMR or IQK have done
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for 2.4G in scan progress */
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bool load_imrandiqk_setting_for2g;
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bool disable_amsdu_8k;
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};
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struct rtl_security {
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@ -936,7 +1043,7 @@ struct rtl_security {
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};
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struct rtl_dm {
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/*PHY status for DM (dynamic management) */
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/*PHY status for Dynamic Management */
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long entry_min_undecoratedsmoothed_pwdb;
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long undecorated_smoothed_pwdb; /*out dm */
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long entry_max_undecoratedsmoothed_pwdb;
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@ -951,33 +1058,46 @@ struct rtl_dm {
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bool txpower_tracking;
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bool useramask;
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bool rfpath_rxenable[4];
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bool inform_fw_driverctrldm;
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bool current_mrc_switch;
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u8 txpowercount;
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u8 thermalvalue_rxgain;
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u8 thermalvalue_iqk;
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u8 thermalvalue_lck;
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u8 thermalvalue;
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u8 last_dtp_lvl;
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u8 thermalvalue_avg[AVG_THERMAL_NUM];
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u8 thermalvalue_avg_index;
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bool done_txpower;
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u8 dynamic_txhighpower_lvl; /*Tx high power level */
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u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
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u8 dm_flag; /*Indicate each dynamic mechanism's status. */
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u8 dm_type;
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u8 txpower_track_control;
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bool interrupt_migration;
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bool disable_tx_int;
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char ofdm_index[2];
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char cck_index;
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u8 power_index_backup[6];
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};
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#define EFUSE_MAX_LOGICAL_SIZE 256
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#define EFUSE_MAX_LOGICAL_SIZE 256
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struct rtl_efuse {
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bool autoload_ok;
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bool autoLoad_ok;
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bool bootfromefuse;
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u16 max_physical_size;
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u8 contents[EFUSE_MAX_LOGICAL_SIZE];
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u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
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u16 efuse_usedbytes;
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u8 efuse_usedpercentage;
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#ifdef EFUSE_REPG_WORKAROUND
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bool efuse_re_pg_sec1flag;
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u8 efuse_re_pg_data[8];
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#endif
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u8 autoload_failflag;
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u8 autoload_status;
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short epromtype;
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u16 eeprom_vid;
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@ -993,43 +1113,61 @@ struct rtl_efuse {
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u8 dev_addr[6];
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bool txpwr_fromeprom;
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u8 eeprom_crystalcap;
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u8 eeprom_tssi[2];
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u8 eeprom_pwrlimit_ht20[3];
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u8 eeprom_pwrlimit_ht40[3];
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u8 eeprom_chnlarea_txpwr_cck[2][3];
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u8 eeprom_chnlarea_txpwr_ht40_1s[2][3];
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u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3];
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u8 txpwrlevel_cck[2][14];
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u8 txpwrlevel_ht40_1s[2][14]; /*For HT 40MHZ pwr */
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u8 txpwrlevel_ht40_2s[2][14]; /*For HT 40MHZ pwr */
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u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
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u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
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u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
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u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
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u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
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u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
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u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
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u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
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u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
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u8 internal_pa_5g[2]; /* pathA / pathB */
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u8 eeprom_c9;
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u8 eeprom_cc;
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/*For power group */
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u8 pwrgroup_ht20[2][14];
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u8 pwrgroup_ht40[2][14];
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u8 eeprom_pwrgroup[2][3];
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u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
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u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
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char txpwr_ht20diff[2][14]; /*HT 20<->40 Pwr diff */
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u8 txpwr_legacyhtdiff[2][14]; /*For HT<->legacy pwr diff */
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char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
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/*For HT<->legacy pwr diff*/
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u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
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u8 txpwr_safetyflag; /* Band edge enable flag */
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u16 eeprom_txpowerdiff;
|
||||
u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
|
||||
u8 antenna_txpwdiff[3];
|
||||
|
||||
u8 eeprom_regulatory;
|
||||
u8 eeprom_thermalmeter;
|
||||
/*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
|
||||
u8 thermalmeter[2];
|
||||
u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
|
||||
u16 tssi_13dbm;
|
||||
u8 crystalcap; /* CrystalCap. */
|
||||
u8 delta_iqk;
|
||||
u8 delta_lck;
|
||||
|
||||
u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
|
||||
bool apk_thermalmeterignore;
|
||||
|
||||
bool b1x1_recvcombine;
|
||||
bool b1ss_support;
|
||||
|
||||
/*channel plan */
|
||||
u8 channel_plan;
|
||||
};
|
||||
|
||||
struct rtl_ps_ctl {
|
||||
bool pwrdomain_protect;
|
||||
bool set_rfpowerstate_inprogress;
|
||||
bool in_powersavemode;
|
||||
bool rfchange_inprogress;
|
||||
bool swrf_processing;
|
||||
bool hwradiooff;
|
||||
|
||||
u32 last_sleep_jiffies;
|
||||
u32 last_awake_jiffies;
|
||||
u32 last_delaylps_stamp_jiffies;
|
||||
|
||||
/*
|
||||
* just for PCIE ASPM
|
||||
* If it supports ASPM, Offset[560h] = 0x40,
|
||||
|
|
@ -1040,6 +1178,7 @@ struct rtl_ps_ctl {
|
|||
|
||||
/*for LPS */
|
||||
enum rt_psmode dot11_psmode; /*Power save mode configured. */
|
||||
bool swctrl_lps;
|
||||
bool leisure_ps;
|
||||
bool fwctrl_lps;
|
||||
u8 fwctrl_psmode;
|
||||
|
|
@ -1063,8 +1202,25 @@ struct rtl_ps_ctl {
|
|||
u8 const_amdpci_aspm;
|
||||
|
||||
bool pwrdown_mode;
|
||||
|
||||
enum rf_pwrstate inactive_pwrstate;
|
||||
enum rf_pwrstate rfpwr_state; /*cur power state */
|
||||
|
||||
/* for SW LPS*/
|
||||
bool sw_ps_enabled;
|
||||
bool state;
|
||||
bool state_inap;
|
||||
bool multi_buffered;
|
||||
u16 nullfunc_seq;
|
||||
unsigned int dtim_counter;
|
||||
unsigned int sleep_ms;
|
||||
unsigned long last_sleep_jiffies;
|
||||
unsigned long last_awake_jiffies;
|
||||
unsigned long last_delaylps_stamp_jiffies;
|
||||
unsigned long last_dtim;
|
||||
unsigned long last_beacon;
|
||||
unsigned long last_action;
|
||||
unsigned long last_slept;
|
||||
};
|
||||
|
||||
struct rtl_stats {
|
||||
|
|
@ -1103,6 +1259,7 @@ struct rtl_stats {
|
|||
u8 rx_drvinfo_size;
|
||||
u8 rx_bufshift;
|
||||
bool isampdu;
|
||||
bool isfirst_ampdu;
|
||||
bool rx_is40Mhzpacket;
|
||||
u32 rx_pwdb_all;
|
||||
u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
|
||||
|
|
@ -1148,6 +1305,15 @@ struct rtl_tcb_desc {
|
|||
u8 ratr_index;
|
||||
u8 mac_id;
|
||||
u8 hw_rate;
|
||||
|
||||
u8 last_inipkt:1;
|
||||
u8 cmd_or_init:1;
|
||||
u8 queue_index;
|
||||
|
||||
/* early mode */
|
||||
u8 empkt_num;
|
||||
/* The max value by HW */
|
||||
u32 empkt_len[5];
|
||||
};
|
||||
|
||||
struct rtl_hal_ops {
|
||||
|
|
@ -1159,6 +1325,8 @@ struct rtl_hal_ops {
|
|||
u32 *p_inta, u32 *p_intb);
|
||||
int (*hw_init) (struct ieee80211_hw *hw);
|
||||
void (*hw_disable) (struct ieee80211_hw *hw);
|
||||
void (*hw_suspend) (struct ieee80211_hw *hw);
|
||||
void (*hw_resume) (struct ieee80211_hw *hw);
|
||||
void (*enable_interrupt) (struct ieee80211_hw *hw);
|
||||
void (*disable_interrupt) (struct ieee80211_hw *hw);
|
||||
int (*set_network_type) (struct ieee80211_hw *hw,
|
||||
|
|
@ -1167,7 +1335,7 @@ struct rtl_hal_ops {
|
|||
bool check_bssid);
|
||||
void (*set_bw_mode) (struct ieee80211_hw *hw,
|
||||
enum nl80211_channel_type ch_type);
|
||||
u8 (*switch_channel) (struct ieee80211_hw *hw);
|
||||
u8(*switch_channel) (struct ieee80211_hw *hw);
|
||||
void (*set_qos) (struct ieee80211_hw *hw, int aci);
|
||||
void (*set_bcn_reg) (struct ieee80211_hw *hw);
|
||||
void (*set_bcn_intv) (struct ieee80211_hw *hw);
|
||||
|
|
@ -1219,6 +1387,7 @@ struct rtl_hal_ops {
|
|||
|
||||
struct rtl_intf_ops {
|
||||
/*com */
|
||||
void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
|
||||
int (*adapter_start) (struct ieee80211_hw *hw);
|
||||
void (*adapter_stop) (struct ieee80211_hw *hw);
|
||||
|
||||
|
|
@ -1262,6 +1431,7 @@ struct rtl_hal_usbint_cfg {
|
|||
};
|
||||
|
||||
struct rtl_hal_cfg {
|
||||
u8 bar_id;
|
||||
char *name;
|
||||
char *fw_name;
|
||||
struct rtl_hal_ops *ops;
|
||||
|
|
@ -1285,7 +1455,11 @@ struct rtl_locks {
|
|||
spinlock_t rf_ps_lock;
|
||||
spinlock_t rf_lock;
|
||||
spinlock_t lps_lock;
|
||||
spinlock_t waitq_lock;
|
||||
spinlock_t tx_urb_lock;
|
||||
|
||||
/*Dual mac*/
|
||||
spinlock_t cck_and_rw_pagea_lock;
|
||||
};
|
||||
|
||||
struct rtl_works {
|
||||
|
|
@ -1302,12 +1476,20 @@ struct rtl_works {
|
|||
struct workqueue_struct *rtl_wq;
|
||||
struct delayed_work watchdog_wq;
|
||||
struct delayed_work ips_nic_off_wq;
|
||||
|
||||
/* For SW LPS */
|
||||
struct delayed_work ps_work;
|
||||
struct delayed_work ps_rfon_wq;
|
||||
};
|
||||
|
||||
struct rtl_debug {
|
||||
u32 dbgp_type[DBGP_TYPE_MAX];
|
||||
u32 global_debuglevel;
|
||||
u64 global_debugcomponents;
|
||||
|
||||
/* add for proc debug */
|
||||
struct proc_dir_entry *proc_dir;
|
||||
char proc_name[20];
|
||||
};
|
||||
|
||||
struct rtl_priv {
|
||||
|
|
@ -1358,6 +1540,7 @@ struct rtl_priv {
|
|||
#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
|
||||
#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
|
||||
|
||||
|
||||
/***************************************
|
||||
Bluetooth Co-existance Related
|
||||
****************************************/
|
||||
|
|
@ -1441,6 +1624,7 @@ struct bt_coexist_info {
|
|||
|
||||
};
|
||||
|
||||
|
||||
/****************************************
|
||||
mem access macro define start
|
||||
Call endian free function when
|
||||
|
|
@ -1563,10 +1747,15 @@ Set subfield of little-endian 4-byte value to specified value. */
|
|||
((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
|
||||
);
|
||||
|
||||
#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
|
||||
(__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
|
||||
|
||||
/****************************************
|
||||
mem access macro define end
|
||||
****************************************/
|
||||
|
||||
#define byte(x, n) ((x >> (8 * n)) & 0xff)
|
||||
|
||||
#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
|
||||
#define RTL_WATCH_DOG_TIME 2000
|
||||
#define MSECS(t) msecs_to_jiffies(t)
|
||||
|
|
@ -1587,6 +1776,8 @@ Set subfield of little-endian 4-byte value to specified value. */
|
|||
#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
|
||||
/*Always enable ASPM and Clock Req in initialization.*/
|
||||
#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
|
||||
/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
|
||||
#define RT_PS_LEVEL_ASPM BIT(7)
|
||||
/*When LPS is on, disable 2R if no packet is received or transmittd.*/
|
||||
#define RT_RF_LPS_DISALBE_2R BIT(30)
|
||||
#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
|
||||
|
|
@ -1601,8 +1792,10 @@ Set subfield of little-endian 4-byte value to specified value. */
|
|||
container_of(container_of(x, struct delayed_work, work), y, z)
|
||||
|
||||
#define FILL_OCTET_STRING(_os, _octet, _len) \
|
||||
(_os).octet = (u8 *)(_octet); \
|
||||
(_os).length = (_len);
|
||||
do { \
|
||||
(_os). octet = (u8 *)(_octet); \
|
||||
(_os). length = (_len); \
|
||||
} while (0);
|
||||
|
||||
#define CP_MACADDR(des, src) \
|
||||
memcpy((des), (src), ETH_ALEN)
|
||||
|
|
|
|||
Loading…
Reference in a new issue