sky2: add register definitions for new chips
This adds infrastructure for the newer chip versions and workarounds. Extracted from the vendor (GPL) driver. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Stephen Hemminger
David S. Miller
parent
e30a4ac243
commit
e91cd2e65f
1 changed files with 177 additions and 1 deletions
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@ -16,6 +16,13 @@ enum {
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PCI_DEV_REG5 = 0x88,
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PCI_CFG_REG_0 = 0x90,
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PCI_CFG_REG_1 = 0x94,
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PSM_CONFIG_REG0 = 0x98,
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PSM_CONFIG_REG1 = 0x9C,
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PSM_CONFIG_REG2 = 0x160,
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PSM_CONFIG_REG3 = 0x164,
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PSM_CONFIG_REG4 = 0x168,
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};
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/* Yukon-2 */
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@ -48,6 +55,37 @@ enum pci_dev_reg_2 {
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PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
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};
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/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
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enum pci_dev_reg_3 {
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P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
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P_CLK_COR_REGS_D0_DIS = 1<<17,/* Disable Clock Core Regs D0 */
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P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
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P_CLK_PCI_REGS_D0_DIS = 1<<16,/* Disable Clock PCI Regs D0 */
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P_CLK_COR_YTB_ARB_DIS = 1<<15,/* Disable Clock YTB Arbiter */
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P_CLK_MAC_LNK1_D3_DIS = 1<<14,/* Disable Clock MAC Link1 D3 */
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P_CLK_COR_LNK1_D0_DIS = 1<<13,/* Disable Clock Core Link1 D0 */
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P_CLK_MAC_LNK1_D0_DIS = 1<<12,/* Disable Clock MAC Link1 D0 */
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P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */
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P_CLK_PCI_MST_ARB_DIS = 1<<10,/* Disable Clock PCI Master Arb. */
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P_CLK_COR_REGS_D3_DIS = 1<<9, /* Disable Clock Core Regs D3 */
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P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */
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P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
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P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
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P_CLK_PCI_COMMON_DIS = 1<<5, /* Disable Clock PCI Common */
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P_CLK_COR_COMMON_DIS = 1<<4, /* Disable Clock Core Common */
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P_CLK_PCI_LNK1_BMU_DIS = 1<<3, /* Disable Clock PCI Link1 BMU */
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P_CLK_COR_LNK1_BMU_DIS = 1<<2, /* Disable Clock Core Link1 BMU */
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P_CLK_PCI_LNK1_BIU_DIS = 1<<1, /* Disable Clock PCI Link1 BIU */
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P_CLK_COR_LNK1_BIU_DIS = 1<<0, /* Disable Clock Core Link1 BIU */
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PCIE_OUR3_WOL_D3_COLD_SET = P_CLK_ASF_REGS_DIS |
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P_CLK_COR_REGS_D0_DIS |
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P_CLK_COR_LNK1_D0_DIS |
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P_CLK_MAC_LNK1_D0_DIS |
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P_CLK_PCI_MST_ARB_DIS |
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P_CLK_COR_COMMON_DIS |
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P_CLK_COR_LNK1_BMU_DIS,
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};
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/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
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enum pci_dev_reg_4 {
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/* (Link Training & Status State Machine) */
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@ -114,7 +152,7 @@ enum pci_dev_reg_5 {
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P_GAT_PCIE_RX_EL_IDLE,
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};
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#/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
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/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
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enum pci_cfg_reg1 {
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P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
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/* Bit 23..21: Release Clock on Event */
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@ -145,6 +183,72 @@ enum pci_cfg_reg1 {
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P_CF1_ENA_TXBMU_WR_IDLE,
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};
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/* Yukon-Optima */
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enum {
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PSM_CONFIG_REG1_AC_PRESENT_STATUS = 1<<31, /* AC Present Status */
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PSM_CONFIG_REG1_PTP_CLK_SEL = 1<<29, /* PTP Clock Select */
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PSM_CONFIG_REG1_PTP_MODE = 1<<28, /* PTP Mode */
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PSM_CONFIG_REG1_MUX_PHY_LINK = 1<<27, /* PHY Energy Detect Event */
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PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT = 1<<26, /* Enable LED_DUPLEX for ac_present */
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PSM_CONFIG_REG1_EN_PCIE_TIMER = 1<<25, /* Enable PCIe Timer */
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PSM_CONFIG_REG1_EN_SPU_TIMER = 1<<24, /* Enable SPU Timer */
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PSM_CONFIG_REG1_POLARITY_AC_PRESENT = 1<<23, /* AC Present Polarity */
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PSM_CONFIG_REG1_EN_AC_PRESENT = 1<<21, /* Enable AC Present */
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PSM_CONFIG_REG1_EN_GPHY_INT_PSM = 1<<20, /* Enable GPHY INT for PSM */
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PSM_CONFIG_REG1_DIS_PSM_TIMER = 1<<19, /* Disable PSM Timer */
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};
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/* Yukon-Supreme */
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enum {
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PSM_CONFIG_REG1_GPHY_ENERGY_STS = 1<<31, /* GPHY Energy Detect Status */
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PSM_CONFIG_REG1_UART_MODE_MSK = 3<<29, /* UART_Mode */
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PSM_CONFIG_REG1_CLK_RUN_ASF = 1<<28, /* Enable Clock Free Running for ASF Subsystem */
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PSM_CONFIG_REG1_UART_CLK_DISABLE= 1<<27, /* Disable UART clock */
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PSM_CONFIG_REG1_VAUX_ONE = 1<<26, /* Tie internal Vaux to 1'b1 */
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PSM_CONFIG_REG1_UART_FC_RI_VAL = 1<<25, /* Default value for UART_RI_n */
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PSM_CONFIG_REG1_UART_FC_DCD_VAL = 1<<24, /* Default value for UART_DCD_n */
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PSM_CONFIG_REG1_UART_FC_DSR_VAL = 1<<23, /* Default value for UART_DSR_n */
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PSM_CONFIG_REG1_UART_FC_CTS_VAL = 1<<22, /* Default value for UART_CTS_n */
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PSM_CONFIG_REG1_LATCH_VAUX = 1<<21, /* Enable Latch current Vaux_avlbl */
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PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT= 1<<20, /* Force Testmode pin as input PAD */
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PSM_CONFIG_REG1_UART_RST = 1<<19, /* UART_RST */
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PSM_CONFIG_REG1_PSM_PCIE_L1_POL = 1<<18, /* PCIE L1 Event Polarity for PSM */
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PSM_CONFIG_REG1_TIMER_STAT = 1<<17, /* PSM Timer Status */
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PSM_CONFIG_REG1_GPHY_INT = 1<<16, /* GPHY INT Status */
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PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO= 1<<15, /* Force internal Testmode as 1'b0 */
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PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ = 1<<14, /* ENABLE INT for CLKRUN on ASPM and CLKREQ */
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PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ = 1<<13, /* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */
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PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK = 1<<12, /* Disable CLK_GATE control snd_task */
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PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
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PSM_CONFIG_REG1_DIS_LOADER = 1<<9, /* Disable Loader SM after PSM Goes back to IDLE */
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PSM_CONFIG_REG1_DO_PWDN = 1<<8, /* Do Power Down, Start PSM Scheme */
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PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
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PSM_CONFIG_REG1_DIS_PERST = 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */
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PSM_CONFIG_REG1_EN_REG18_PD = 1<<5, /* Enable REG18 Power Down for PSM */
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PSM_CONFIG_REG1_EN_PSM_LOAD = 1<<4, /* Disable EEPROM Loader after PSM Goes back to IDLE */
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PSM_CONFIG_REG1_EN_PSM_HOT_RST = 1<<3, /* Enable PCIe Hot Reset for PSM */
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PSM_CONFIG_REG1_EN_PSM_PERST = 1<<2, /* Enable PCIe Reset Event for PSM */
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PSM_CONFIG_REG1_EN_PSM_PCIE_L1 = 1<<1, /* Enable PCIe L1 Event for PSM */
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PSM_CONFIG_REG1_EN_PSM = 1<<0, /* Enable PSM Scheme */
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};
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/* PSM_CONFIG_REG4 0x0168 PSM Config Register 4 */
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enum {
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/* PHY Link Detect Timer */
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PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 0xf<<4,
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PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4,
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PSM_CONFIG_REG4_DEBUG_TIMER = 1<<1, /* Debug Timer */
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PSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1<<0, /* Reset GPHY Link Detect */
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};
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#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
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PCI_STATUS_SIG_SYSTEM_ERROR | \
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@ -197,6 +301,9 @@ enum csr_regs {
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B2_I2C_IRQ = 0x0168,
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B2_I2C_SW = 0x016c,
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Y2_PEX_PHY_DATA = 0x0170,
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Y2_PEX_PHY_ADDR = 0x0172,
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B3_RAM_ADDR = 0x0180,
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B3_RAM_DATA_LO = 0x0184,
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B3_RAM_DATA_HI = 0x0188,
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@ -317,6 +424,10 @@ enum {
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Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
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Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
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Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */
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Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */
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Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */
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Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
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Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
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Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
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@ -435,6 +546,7 @@ enum {
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CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
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CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
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CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
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CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */
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};
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enum yukon_ec_rev {
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CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
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@ -459,6 +571,8 @@ enum yukon_ex_rev {
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};
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enum yukon_supr_rev {
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CHIP_REV_YU_SU_A0 = 0,
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CHIP_REV_YU_SU_B0 = 1,
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CHIP_REV_YU_SU_B1 = 3,
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};
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@ -513,6 +627,12 @@ enum {
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TIM_T_STEP = 1<<0, /* Test step */
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};
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/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
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enum {
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PEX_RD_ACCESS = 1<<31, /* Access Mode Read = 1, Write = 0 */
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PEX_DB_ACCESS = 1<<30, /* Access to debug register */
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};
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/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
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/* Bit 31..19: reserved */
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#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
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@ -754,6 +874,42 @@ enum {
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BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
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};
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/* TBMU_TEST 0x06B8 Transmit BMU Test Register */
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enum {
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TBMU_TEST_BMU_TX_CHK_AUTO_OFF = 1<<31, /* BMU Tx Checksum Auto Calculation Disable */
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TBMU_TEST_BMU_TX_CHK_AUTO_ON = 1<<30, /* BMU Tx Checksum Auto Calculation Enable */
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TBMU_TEST_HOME_ADD_PAD_FIX1_EN = 1<<29, /* Home Address Paddiing FIX1 Enable */
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TBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 1<<28, /* Home Address Paddiing FIX1 Disable */
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TBMU_TEST_ROUTING_ADD_FIX_EN = 1<<27, /* Routing Address Fix Enable */
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TBMU_TEST_ROUTING_ADD_FIX_DIS = 1<<26, /* Routing Address Fix Disable */
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TBMU_TEST_HOME_ADD_FIX_EN = 1<<25, /* Home address checksum fix enable */
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TBMU_TEST_HOME_ADD_FIX_DIS = 1<<24, /* Home address checksum fix disable */
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TBMU_TEST_TEST_RSPTR_ON = 1<<22, /* Testmode Shadow Read Ptr On */
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TBMU_TEST_TEST_RSPTR_OFF = 1<<21, /* Testmode Shadow Read Ptr Off */
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TBMU_TEST_TESTSTEP_RSPTR = 1<<20, /* Teststep Shadow Read Ptr */
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TBMU_TEST_TEST_RPTR_ON = 1<<18, /* Testmode Read Ptr On */
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TBMU_TEST_TEST_RPTR_OFF = 1<<17, /* Testmode Read Ptr Off */
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TBMU_TEST_TESTSTEP_RPTR = 1<<16, /* Teststep Read Ptr */
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TBMU_TEST_TEST_WSPTR_ON = 1<<14, /* Testmode Shadow Write Ptr On */
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TBMU_TEST_TEST_WSPTR_OFF = 1<<13, /* Testmode Shadow Write Ptr Off */
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TBMU_TEST_TESTSTEP_WSPTR = 1<<12, /* Teststep Shadow Write Ptr */
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TBMU_TEST_TEST_WPTR_ON = 1<<10, /* Testmode Write Ptr On */
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TBMU_TEST_TEST_WPTR_OFF = 1<<9, /* Testmode Write Ptr Off */
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TBMU_TEST_TESTSTEP_WPTR = 1<<8, /* Teststep Write Ptr */
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TBMU_TEST_TEST_REQ_NB_ON = 1<<6, /* Testmode Req Nbytes/Addr On */
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TBMU_TEST_TEST_REQ_NB_OFF = 1<<5, /* Testmode Req Nbytes/Addr Off */
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TBMU_TEST_TESTSTEP_REQ_NB = 1<<4, /* Teststep Req Nbytes/Addr */
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TBMU_TEST_TEST_DONE_IDX_ON = 1<<2, /* Testmode Done Index On */
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TBMU_TEST_TEST_DONE_IDX_OFF = 1<<1, /* Testmode Done Index Off */
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TBMU_TEST_TESTSTEP_DONE_IDX = 1<<0, /* Teststep Done Index */
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};
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/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
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/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
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enum {
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@ -1674,6 +1830,12 @@ enum {
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/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
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enum {
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RX_GCLKMAC_ENA = 1<<31, /* RX MAC Clock Gating Enable */
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RX_GCLKMAC_OFF = 1<<30,
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RX_STFW_DIS = 1<<29, /* RX Store and Forward Enable */
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RX_STFW_ENA = 1<<28,
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RX_TRUNC_ON = 1<<27, /* enable packet truncation */
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RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
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RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
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@ -1711,6 +1873,20 @@ enum {
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GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
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};
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/* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
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enum {
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RX_IPV6_SA_MOB_ENA = 1<<9, /* IPv6 SA Mobility Support Enable */
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RX_IPV6_SA_MOB_DIS = 1<<8, /* IPv6 SA Mobility Support Disable */
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RX_IPV6_DA_MOB_ENA = 1<<7, /* IPv6 DA Mobility Support Enable */
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RX_IPV6_DA_MOB_DIS = 1<<6, /* IPv6 DA Mobility Support Disable */
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RX_PTR_SYNCDLY_ENA = 1<<5, /* Pointers Delay Synch Enable */
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RX_PTR_SYNCDLY_DIS = 1<<4, /* Pointers Delay Synch Disable */
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RX_ASF_NEWFLAG_ENA = 1<<3, /* RX ASF Flag New Logic Enable */
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RX_ASF_NEWFLAG_DIS = 1<<2, /* RX ASF Flag New Logic Disable */
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RX_FLSH_MISSPKT_ENA = 1<<1, /* RX Flush Miss-Packet Enable */
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RX_FLSH_MISSPKT_DIS = 1<<0, /* RX Flush Miss-Packet Disable */
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};
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/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
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enum {
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TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
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