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regulator: replace ADTV1 register by ADTV2 in da903x

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In PXA3xx SoC family, V_CORE power doamin is supplied by BUCK1 that is
controller by ADTV1 or ADTV2 register.

By default, v1 and v2 has the same copy. If v1 or v2 is updated, the last
value that is written to either register takes effect. It means that v1
and v2 has different copy. And the actual voltage output is determinated
by last update on either register.

DA9034/35 is binded with PXA3xx SoC family. While SoC is scaling OP or
entering/exiting lower power mode, SoC needs to change voltage of V_CORE
power doamin. In order to be efficient, POWER I2C (hardcode) mode could
be enabled in SoC. In this mode, SoC will control v2 register directly.

In original DA903x driver, software will only read regulator data from v1
register. But SoC controls v2 register directly. It results that v1 and v2
isn't synchronized. Wrong data will be read from v1 register. So access v2
register in da903x driver instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Haojian Zhuang 2009-07-09 17:52:30 +08:00 committed by Liam Girdwood
parent fc4f42e7fb
commit e88267e164
1 changed files with 3 additions and 3 deletions
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6
drivers/regulator/da903x.c
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@ -469,9 +469,9 @@ static struct da903x_regulator_info da903x_regulator_info[] = {
DA9030_LDO(13, 2100, 2100, 0, INVAL, 0, 0, RCTL11, 3), /* fixed @2.1V */
/* DA9034 */
DA9034_DVC(BUCK1, 725, 1500, 25, ADTV1, 5, VCC1, 0, OVER1, 0),
DA9034_DVC(BUCK2, 725, 1500, 25, CDTV1, 5, VCC1, 2, OVER1, 1),
DA9034_DVC(LDO2, 725, 1500, 25, SDTV1, 5, VCC1, 4, OVER1, 2),
DA9034_DVC(BUCK1, 725, 1500, 25, ADTV2, 5, VCC1, 0, OVER1, 0),
DA9034_DVC(BUCK2, 725, 1500, 25, CDTV2, 5, VCC1, 2, OVER1, 1),
DA9034_DVC(LDO2, 725, 1500, 25, SDTV2, 5, VCC1, 4, OVER1, 2),
DA9034_DVC(LDO1, 1700, 2075, 25, MDTV1, 4, VCC1, 6, OVER3, 4),
DA9034_LDO( 3, 1800, 3300, 100, LDO643, 0, 4, OVER3, 5),