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msm: vidc: Add snapshot of MSM video driver

Browse source 
This is a snapshot from branch msm-4.14
'commit 195f5d0cdc2c ("cnss2: Do not handle MHI device
error during driver unloading")'.

CRs-Fixed: 2344373
Change-Id: Ifd98751c64924852de74a56f4827b0ec7b9eb291
Signed-off-by: Tapas Kumar Kundu <tkundu@codeaurora.org>
Signed-off-by: Vaibhav Deshu Venkatesh <vdeshuve@codeaurora.org>
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>
This commit is contained in:
Chinmay Sawarkar 2018-09-24 17:57:11 -07:00 • committed by Vaibhav Deshu Venkatesh
parent 9e86e31f47
commit e8507af28b
50 changed files with 37446 additions and 6 deletions

1
drivers/media/platform/msm/Kconfig
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@ -10,3 +10,4 @@ menuconfig SPECTRA_CAMERA
IFE and postprocessing drivers.
source "drivers/media/platform/msm/sde/Kconfig"
source "drivers/media/platform/msm/vidc/Kconfig"

7
drivers/media/platform/msm/Makefile
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@ -1,4 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += sde/
obj-$(CONFIG_SPECTRA_CAMERA) += camera/
obj-$(CONFIG_SPECTRA_CAMERA) += camera/
#
# Makefile for the qti specific video device drivers
# based on V4L2.
#
obj-$(CONFIG_MSM_VIDC_V4L2) += vidc/

12
drivers/media/platform/msm/vidc/Kconfig Normal file
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@ -0,0 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
#
# VIDEO CORE
#
menuconfig MSM_VIDC_V4L2
tristate "Qualcomm Technologies, Inc. MSM V4L2 based video driver"
depends on ARCH_QCOM && VIDEO_V4L2
select VIDEOBUF2_CORE
help
Enable support of MSM V4L2 video driver for
Qualcomm Technologies, Inc.

26
drivers/media/platform/msm/vidc/Makefile Normal file
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@ -0,0 +1,26 @@
# SPDX-License-Identifier: GPL-2.0
ccflags-y += -I$(srctree)/drivers/media/platform/msm/vidc/ \
-I$(srctree)/drivers/devfreq/
msm-vidc-objs := msm_v4l2_vidc.o \
msm_v4l2_private.o \
msm_vidc_platform.o \
msm_vidc_common.o \
msm_vidc.o \
msm_vdec.o \
msm_venc.o \
msm_cvp.o \
msm_smem.o \
msm_vidc_debug.o \
msm_vidc_res_parse.o \
venus_hfi.o \
hfi_response_handler.o \
hfi_packetization.o \
vidc_hfi.o \
venus_boot.o \
msm_vidc_clocks.o \
msm_vidc_ar50_dyn_gov.o \
msm_vidc_dyn_gov.o
obj-$(CONFIG_MSM_VIDC_V4L2) := msm-vidc.o

65
drivers/media/platform/msm/vidc/fixedpoint.h Normal file
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@ -0,0 +1,65 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifdef _FIXP_ARITH_H
#error "This implementation is meant to override fixp-arith.h, don't use both"
#endif
#ifndef _FIXEDPOINT_H_
#define _FIXEDPOINT_H_
/*
* Normally would typedef'ed, but checkpatch doesn't like typedef.
* Also should be normally typedef'ed to intmax_t but that doesn't seem to be
* available in the kernel
*/
#define fp_t size_t
/* (Arbitrarily) make the first 25% of the bits to be the fractional bits */
#define FP_FRACTIONAL_BITS ((sizeof(fp_t) * 8) / 4)
#define FP(__i, __f_n, __f_d) \
((((fp_t)(__i)) << FP_FRACTIONAL_BITS) + \
(((__f_n) << FP_FRACTIONAL_BITS) / (__f_d)))
#define FP_INT(__i) FP(__i, 0, 1)
#define FP_ONE FP_INT(1)
#define FP_ZERO FP_INT(0)
static inline size_t fp_frac_base(void)
{
return GENMASK(FP_FRACTIONAL_BITS - 1, 0);
}
static inline size_t fp_frac(fp_t a)
{
return a & GENMASK(FP_FRACTIONAL_BITS - 1, 0);
}
static inline size_t fp_int(fp_t a)
{
return a >> FP_FRACTIONAL_BITS;
}
static inline size_t fp_round(fp_t a)
{
/* is the fractional part >= frac_max / 2? */
bool round_up = fp_frac(a) >= fp_frac_base() / 2;
return fp_int(a) + round_up;
}
static inline fp_t fp_mult(fp_t a, fp_t b)
{
return (a * b) >> FP_FRACTIONAL_BITS;
}
static inline fp_t fp_div(fp_t a, fp_t b)
{
return (a << FP_FRACTIONAL_BITS) / b;
}
#endif

2121
drivers/media/platform/msm/vidc/hfi_packetization.c Normal file
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File diff suppressed because it is too large Load diff

93
drivers/media/platform/msm/vidc/hfi_packetization.h Normal file
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@ -0,0 +1,93 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __HFI_PACKETIZATION_H__
#define __HFI_PACKETIZATION_H__
#include <linux/types.h>
#include "vidc_hfi_helper.h"
#include "vidc_hfi.h"
#include "vidc_hfi_api.h"
#define call_hfi_pkt_op(q, op, ...) \
(((q) && (q)->pkt_ops && (q)->pkt_ops->op) ? \
((q)->pkt_ops->op(__VA_ARGS__)) : 0)
enum hfi_packetization_type {
HFI_PACKETIZATION_4XX,
};
struct hfi_packetization_ops {
int (*sys_init)(struct hfi_cmd_sys_init_packet *pkt, u32 arch_type);
int (*sys_pc_prep)(struct hfi_cmd_sys_pc_prep_packet *pkt);
int (*sys_power_control)(struct hfi_cmd_sys_set_property_packet *pkt,
u32 enable);
int (*sys_set_resource)(
struct hfi_cmd_sys_set_resource_packet *pkt,
struct vidc_resource_hdr *resource_hdr,
void *resource_value);
int (*sys_debug_config)(struct hfi_cmd_sys_set_property_packet *pkt,
u32 mode);
int (*sys_coverage_config)(struct hfi_cmd_sys_set_property_packet *pkt,
u32 mode);
int (*sys_release_resource)(
struct hfi_cmd_sys_release_resource_packet *pkt,
struct vidc_resource_hdr *resource_hdr);
int (*sys_ping)(struct hfi_cmd_sys_ping_packet *pkt);
int (*sys_image_version)(struct hfi_cmd_sys_get_property_packet *pkt);
int (*ssr_cmd)(enum hal_ssr_trigger_type type,
struct hfi_cmd_sys_test_ssr_packet *pkt);
int (*session_init)(
struct hfi_cmd_sys_session_init_packet *pkt,
struct hal_session *session,
u32 session_domain, u32 session_codec);
int (*session_cmd)(struct vidc_hal_session_cmd_pkt *pkt,
int pkt_type, struct hal_session *session);
int (*session_set_buffers)(
struct hfi_cmd_session_set_buffers_packet *pkt,
struct hal_session *session,
struct vidc_buffer_addr_info *buffer_info);
int (*session_release_buffers)(
struct hfi_cmd_session_release_buffer_packet *pkt,
struct hal_session *session,
struct vidc_buffer_addr_info *buffer_info);
int (*session_register_buffer)(
struct hfi_cmd_session_register_buffers_packet *pkt,
struct hal_session *session,
struct vidc_register_buffer *buffer);
int (*session_unregister_buffer)(
struct hfi_cmd_session_unregister_buffers_packet *pkt,
struct hal_session *session,
struct vidc_unregister_buffer *buffer);
int (*session_etb_decoder)(
struct hfi_cmd_session_empty_buffer_compressed_packet *pkt,
struct hal_session *session,
struct vidc_frame_data *input_frame);
int (*session_etb_encoder)(
struct hfi_cmd_session_empty_buffer_uncompressed_plane0_packet
*pkt, struct hal_session *session,
struct vidc_frame_data *input_frame);
int (*session_ftb)(struct hfi_cmd_session_fill_buffer_packet *pkt,
struct hal_session *session,
struct vidc_frame_data *output_frame);
int (*session_get_buf_req)(
struct hfi_cmd_session_get_property_packet *pkt,
struct hal_session *session);
int (*session_flush)(struct hfi_cmd_session_flush_packet *pkt,
struct hal_session *session, enum hal_flush flush_mode);
int (*session_get_property)(
struct hfi_cmd_session_get_property_packet *pkt,
struct hal_session *session, enum hal_property ptype);
int (*session_set_property)(
struct hfi_cmd_session_set_property_packet *pkt,
struct hal_session *session,
enum hal_property ptype, void *pdata);
int (*session_sync_process)(
struct hfi_cmd_session_sync_process_packet *pkt,
struct hal_session *session);
};
struct hfi_packetization_ops *hfi_get_pkt_ops_handle(
enum hfi_packetization_type);
#endif

1925
drivers/media/platform/msm/vidc/hfi_response_handler.c Normal file
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File diff suppressed because it is too large Load diff

627
drivers/media/platform/msm/vidc/msm_cvp.c Normal file
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@ -0,0 +1,627 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include "msm_cvp.h"
#define MSM_VIDC_NOMINAL_CYCLES (444 * 1000 * 1000)
#define MSM_VIDC_UHD60E_VPSS_CYCLES (111 * 1000 * 1000)
#define MSM_VIDC_UHD60E_ISE_CYCLES (175 * 1000 * 1000)
#define MAX_CVP_VPSS_CYCLES (MSM_VIDC_NOMINAL_CYCLES - \
MSM_VIDC_UHD60E_VPSS_CYCLES)
#define MAX_CVP_ISE_CYCLES (MSM_VIDC_NOMINAL_CYCLES - \
MSM_VIDC_UHD60E_ISE_CYCLES)
static void print_client_buffer(u32 tag, const char *str,
struct msm_vidc_inst *inst, struct msm_cvp_buffer *cbuf)
{
if (!(tag & msm_vidc_debug) || !inst || !cbuf)
return;
dprintk(tag,
"%s: %x : idx %2d fd %d off %d size %d type %d flags 0x%x\n",
str, hash32_ptr(inst->session), cbuf->index, cbuf->fd,
cbuf->offset, cbuf->size, cbuf->type, cbuf->flags);
}
static void print_cvp_buffer(u32 tag, const char *str,
struct msm_vidc_inst *inst, struct msm_vidc_cvp_buffer *cbuf)
{
if (!(tag & msm_vidc_debug) || !inst || !cbuf)
return;
dprintk(tag,
"%s: %x : idx %2d fd %d off %d daddr %x size %d type %d flags 0x%x\n",
str, hash32_ptr(inst->session), cbuf->buf.index, cbuf->buf.fd,
cbuf->buf.offset, cbuf->smem.device_addr, cbuf->buf.size,
cbuf->buf.type, cbuf->buf.flags);
}
static enum hal_buffer get_hal_buftype(const char *str, unsigned int type)
{
enum hal_buffer buftype = HAL_BUFFER_NONE;
if (type == MSM_CVP_BUFTYPE_INPUT)
buftype = HAL_BUFFER_INPUT;
else if (type == MSM_CVP_BUFTYPE_OUTPUT)
buftype = HAL_BUFFER_OUTPUT;
else if (type == MSM_CVP_BUFTYPE_INTERNAL_1)
buftype = HAL_BUFFER_INTERNAL_SCRATCH_1;
else if (type == MSM_CVP_BUFTYPE_INTERNAL_2)
buftype = HAL_BUFFER_INTERNAL_SCRATCH_1;
else
dprintk(VIDC_ERR, "%s: unknown buffer type %#x\n",
str, type);
return buftype;
}
void handle_session_register_buffer_done(enum hal_command_response cmd,
void *resp)
{
struct msm_vidc_cb_cmd_done *response = resp;
struct msm_vidc_inst *inst;
struct msm_vidc_cvp_buffer *cbuf;
struct v4l2_event event = {0};
u32 *data;
bool found;
if (!response) {
dprintk(VIDC_ERR, "%s: invalid response\n", __func__);
return;
}
inst = get_inst(get_vidc_core(response->device_id),
response->session_id);
if (!inst) {
dprintk(VIDC_ERR, "%s: invalid session %pK\n", __func__,
response->session_id);
return;
}
mutex_lock(&inst->cvpbufs.lock);
found = false;
list_for_each_entry(cbuf, &inst->cvpbufs.list, list) {
if (response->data.regbuf.client_data ==
cbuf->smem.device_addr) {
found = true;
break;
}
}
mutex_unlock(&inst->cvpbufs.lock);
if (!found) {
dprintk(VIDC_ERR, "%s: client_data %x not found\n",
__func__, response->data.regbuf.client_data);
goto exit;
}
print_cvp_buffer(VIDC_DBG, "register_done", inst, cbuf);
event.type = V4L2_EVENT_MSM_VIDC_REGISTER_BUFFER_DONE;
data = (u32 *)event.u.data;
data[0] = cbuf->buf.index;
data[1] = cbuf->buf.type;
data[2] = cbuf->buf.fd;
data[3] = cbuf->buf.offset;
v4l2_event_queue_fh(&inst->event_handler, &event);
exit:
put_inst(inst);
}
void handle_session_unregister_buffer_done(enum hal_command_response cmd,
void *resp)
{
int rc;
struct msm_vidc_cb_cmd_done *response = resp;
struct msm_vidc_inst *inst;
struct msm_vidc_cvp_buffer *cbuf, *dummy;
struct v4l2_event event = {0};
u32 *data;
bool found;
if (!response) {
dprintk(VIDC_ERR, "%s: invalid response\n", __func__);
return;
}
inst = get_inst(get_vidc_core(response->device_id),
response->session_id);
if (!inst) {
dprintk(VIDC_ERR, "%s: invalid session %pK\n", __func__,
response->session_id);
return;
}
mutex_lock(&inst->cvpbufs.lock);
found = false;
list_for_each_entry_safe(cbuf, dummy, &inst->cvpbufs.list, list) {
if (response->data.unregbuf.client_data ==
cbuf->smem.device_addr) {
found = true;
break;
}
}
mutex_unlock(&inst->cvpbufs.lock);
if (!found) {
dprintk(VIDC_ERR, "%s: client_data %x not found\n",
__func__, response->data.unregbuf.client_data);
goto exit;
}
print_cvp_buffer(VIDC_DBG, "unregister_done", inst, cbuf);
rc = inst->smem_ops->smem_unmap_dma_buf(inst, &cbuf->smem);
if (rc) {
print_cvp_buffer(VIDC_ERR, "unmap fail", inst, cbuf);
goto exit;
}
event.type = V4L2_EVENT_MSM_VIDC_UNREGISTER_BUFFER_DONE;
data = (u32 *)event.u.data;
data[0] = cbuf->buf.index;
data[1] = cbuf->buf.type;
data[2] = cbuf->buf.fd;
data[3] = cbuf->buf.offset;
v4l2_event_queue_fh(&inst->event_handler, &event);
mutex_lock(&inst->cvpbufs.lock);
list_del(&cbuf->list);
mutex_unlock(&inst->cvpbufs.lock);
kfree(cbuf);
cbuf = NULL;
exit:
put_inst(inst);
}
static void print_cvp_cycles(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
struct msm_vidc_inst *temp;
if (!inst || !inst->core)
return;
core = inst->core;
mutex_lock(&core->lock);
list_for_each_entry(temp, &core->instances, list) {
if (temp->session_type == MSM_VIDC_CVP) {
dprintk(VIDC_ERR, "session %#x, vpss %d ise %d\n",
hash32_ptr(temp->session),
temp->clk_data.vpss_cycles,
temp->clk_data.ise_cycles);
}
}
mutex_unlock(&core->lock);
}
static bool msm_cvp_check_session_supported(struct msm_vidc_inst *inst,
u32 vpss_cycles, u32 ise_cycles)
{
struct msm_vidc_core *core;
struct msm_vidc_inst *temp;
u32 total_vpss_cycles = 0;
u32 total_ise_cycles = 0;
if (!inst || !inst->core) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return false;
}
core = inst->core;
mutex_lock(&core->lock);
list_for_each_entry(temp, &core->instances, list) {
if (temp->session_type == MSM_VIDC_CVP) {
total_vpss_cycles += inst->clk_data.vpss_cycles;
total_ise_cycles += inst->clk_data.ise_cycles;
}
}
mutex_unlock(&core->lock);
if ((total_vpss_cycles > MAX_CVP_VPSS_CYCLES) ||
(total_ise_cycles > MAX_CVP_ISE_CYCLES))
return false;
return true;
}
static int msm_cvp_scale_clocks_and_bus(struct msm_vidc_inst *inst)
{
int rc = 0;
if (!inst || !inst->core) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
rc = msm_vidc_set_clocks(inst->core);
if (rc) {
dprintk(VIDC_ERR,
"%s: failed set_clocks for inst %pK (%#x)\n",
__func__, inst, hash32_ptr(inst->session));
goto exit;
}
rc = msm_comm_vote_bus(inst->core);
if (rc) {
dprintk(VIDC_ERR,
"%s: failed vote_bus for inst %pK (%#x)\n",
__func__, inst, hash32_ptr(inst->session));
goto exit;
}
exit:
return rc;
}
static int msm_cvp_get_session_info(struct msm_vidc_inst *inst,
struct msm_cvp_session_info *session)
{
int rc = 0;
if (!inst || !inst->core || !session) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
session->session_id = hash32_ptr(inst->session);
dprintk(VIDC_DBG, "%s: id 0x%x\n", __func__, session->session_id);
return rc;
}
static int msm_cvp_request_power(struct msm_vidc_inst *inst,
struct msm_cvp_request_power *power)
{
int rc = 0;
if (!inst || !power) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
dprintk(VIDC_DBG,
"%s: clock_cycles_a %d, clock_cycles_b %d, ddr_bw %d sys_cache_bw %d\n",
__func__, power->clock_cycles_a, power->clock_cycles_b,
power->ddr_bw, power->sys_cache_bw);
rc = msm_cvp_check_session_supported(inst, power->clock_cycles_a,
power->clock_cycles_b);
if (!rc) {
dprintk(VIDC_ERR,
"%s: session %#x rejected, cycles: vpss %d, ise %d\n",
__func__, hash32_ptr(inst->session),
power->clock_cycles_a, power->clock_cycles_b);
print_cvp_cycles(inst);
msm_comm_kill_session(inst);
return -EOVERFLOW;
}
inst->clk_data.min_freq = max(power->clock_cycles_a,
power->clock_cycles_b);
/* convert client provided bps into kbps as expected by driver */
inst->clk_data.ddr_bw = power->ddr_bw / 1000;
inst->clk_data.sys_cache_bw = power->sys_cache_bw / 1000;
rc = msm_cvp_scale_clocks_and_bus(inst);
if (rc) {
dprintk(VIDC_ERR,
"%s: failed to scale clocks and bus for inst %pK (%#x)\n",
__func__, inst, hash32_ptr(inst->session));
goto exit;
}
if (!inst->clk_data.min_freq && !inst->clk_data.ddr_bw &&
!inst->clk_data.sys_cache_bw) {
rc = msm_cvp_inst_pause(inst);
if (rc) {
dprintk(VIDC_ERR,
"%s: failed to pause inst %pK (%#x)\n",
__func__, inst, hash32_ptr(inst->session));
goto exit;
}
} else {
rc = msm_cvp_inst_resume(inst);
if (rc) {
dprintk(VIDC_ERR,
"%s: failed to resume inst %pK (%#x)\n",
__func__, inst, hash32_ptr(inst->session));
goto exit;
}
}
exit:
return rc;
}
static int msm_cvp_register_buffer(struct msm_vidc_inst *inst,
struct msm_cvp_buffer *buf)
{
int rc = 0;
bool found;
struct hfi_device *hdev;
struct msm_vidc_cvp_buffer *cbuf;
struct vidc_register_buffer vbuf;
if (!inst || !inst->core || !buf) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
hdev = inst->core->device;
print_client_buffer(VIDC_DBG, "register", inst, buf);
mutex_lock(&inst->cvpbufs.lock);
found = false;
list_for_each_entry(cbuf, &inst->cvpbufs.list, list) {
if (cbuf->buf.index == buf->index &&
cbuf->buf.fd == buf->fd &&
cbuf->buf.offset == buf->offset) {
found = true;
break;
}
}
mutex_unlock(&inst->cvpbufs.lock);
if (found) {
print_client_buffer(VIDC_ERR, "duplicate", inst, buf);
return -EINVAL;
}
cbuf = kzalloc(sizeof(struct msm_vidc_cvp_buffer), GFP_KERNEL);
if (!cbuf) {
dprintk(VIDC_ERR, "%s: cbuf alloc failed\n", __func__);
return -ENOMEM;
}
mutex_lock(&inst->cvpbufs.lock);
list_add_tail(&cbuf->list, &inst->cvpbufs.list);
mutex_unlock(&inst->cvpbufs.lock);
memcpy(&cbuf->buf, buf, sizeof(struct msm_cvp_buffer));
cbuf->smem.buffer_type = get_hal_buftype(__func__, buf->type);
cbuf->smem.fd = buf->fd;
cbuf->smem.offset = buf->offset;
cbuf->smem.size = buf->size;
rc = inst->smem_ops->smem_map_dma_buf(inst, &cbuf->smem);
if (rc) {
print_client_buffer(VIDC_ERR, "map failed", inst, buf);
goto exit;
}
memset(&vbuf, 0, sizeof(struct vidc_register_buffer));
vbuf.index = buf->index;
vbuf.type = get_hal_buftype(__func__, buf->type);
vbuf.size = buf->size;
vbuf.device_addr = cbuf->smem.device_addr;
vbuf.client_data = cbuf->smem.device_addr;
vbuf.response_required = true;
rc = call_hfi_op(hdev, session_register_buffer,
(void *)inst->session, &vbuf);
if (rc) {
print_cvp_buffer(VIDC_ERR, "register failed", inst, cbuf);
goto exit;
}
return rc;
exit:
if (cbuf->smem.device_addr)
inst->smem_ops->smem_unmap_dma_buf(inst, &cbuf->smem);
mutex_lock(&inst->cvpbufs.lock);
list_del(&cbuf->list);
mutex_unlock(&inst->cvpbufs.lock);
kfree(cbuf);
cbuf = NULL;
return rc;
}
static int msm_cvp_unregister_buffer(struct msm_vidc_inst *inst,
struct msm_cvp_buffer *buf)
{
int rc = 0;
bool found;
struct hfi_device *hdev;
struct msm_vidc_cvp_buffer *cbuf;
struct vidc_unregister_buffer vbuf;
if (!inst || !inst->core || !buf) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
hdev = inst->core->device;
print_client_buffer(VIDC_DBG, "unregister", inst, buf);
mutex_lock(&inst->cvpbufs.lock);
found = false;
list_for_each_entry(cbuf, &inst->cvpbufs.list, list) {
if (cbuf->buf.index == buf->index &&
cbuf->buf.fd == buf->fd &&
cbuf->buf.offset == buf->offset) {
found = true;
break;
}
}
mutex_unlock(&inst->cvpbufs.lock);
if (!found) {
print_client_buffer(VIDC_ERR, "invalid", inst, buf);
return -EINVAL;
}
memset(&vbuf, 0, sizeof(struct vidc_unregister_buffer));
vbuf.index = cbuf->buf.index;
vbuf.type = get_hal_buftype(__func__, cbuf->buf.type);
vbuf.size = cbuf->buf.size;
vbuf.device_addr = cbuf->smem.device_addr;
vbuf.client_data = cbuf->smem.device_addr;
vbuf.response_required = true;
rc = call_hfi_op(hdev, session_unregister_buffer,
(void *)inst->session, &vbuf);
if (rc)
print_cvp_buffer(VIDC_ERR, "unregister failed", inst, cbuf);
return rc;
}
int msm_vidc_cvp(struct msm_vidc_inst *inst, struct msm_vidc_arg *arg)
{
int rc = 0;
if (!inst || !arg) {
dprintk(VIDC_ERR, "%s: invalid args\n", __func__);
return -EINVAL;
}
switch (arg->type) {
case MSM_CVP_GET_SESSION_INFO:
{
struct msm_cvp_session_info *session =
(struct msm_cvp_session_info *)&arg->data.session;
rc = msm_cvp_get_session_info(inst, session);
break;
}
case MSM_CVP_REQUEST_POWER:
{
struct msm_cvp_request_power *power =
(struct msm_cvp_request_power *)&arg->data.req_power;
rc = msm_cvp_request_power(inst, power);
break;
}
case MSM_CVP_REGISTER_BUFFER:
{
struct msm_cvp_buffer *buf =
(struct msm_cvp_buffer *)&arg->data.regbuf;
rc = msm_cvp_register_buffer(inst, buf);
break;
}
case MSM_CVP_UNREGISTER_BUFFER:
{
struct msm_cvp_buffer *buf =
(struct msm_cvp_buffer *)&arg->data.unregbuf;
rc = msm_cvp_unregister_buffer(inst, buf);
break;
}
default:
dprintk(VIDC_ERR, "%s: unknown arg type 0x%x\n",
__func__, arg->type);
rc = -ENOTSUPP;
break;
}
return rc;
}
static struct msm_vidc_ctrl msm_cvp_ctrls[] = {
{
.id = V4L2_CID_MPEG_VIDC_VIDEO_SECURE,
.name = "Secure mode",
.type = V4L2_CTRL_TYPE_BUTTON,
.minimum = 0,
.maximum = 1,
.default_value = 0,
.step = 1,
.menu_skip_mask = 0,
.qmenu = NULL,
},
};
int msm_cvp_ctrl_init(struct msm_vidc_inst *inst,
const struct v4l2_ctrl_ops *ctrl_ops)
{
return msm_comm_ctrl_init(inst, msm_cvp_ctrls,
ARRAY_SIZE(msm_cvp_ctrls), ctrl_ops);
}
int msm_cvp_inst_pause(struct msm_vidc_inst *inst)
{
int rc;
struct hfi_device *hdev;
if (!inst || !inst->core || !inst->core->device) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
hdev = inst->core->device;
rc = call_hfi_op(hdev, session_pause, (void *)inst->session);
if (rc)
dprintk(VIDC_ERR, "%s: failed to pause inst %pK (%#x)\n",
__func__, inst, hash32_ptr(inst->session));
return rc;
}
int msm_cvp_inst_resume(struct msm_vidc_inst *inst)
{
int rc;
struct hfi_device *hdev;
if (!inst || !inst->core || !inst->core->device) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
hdev = inst->core->device;
rc = call_hfi_op(hdev, session_resume, (void *)inst->session);
if (rc)
dprintk(VIDC_ERR, "%s: failed to resume inst %pK (%#x)\n",
__func__, inst, hash32_ptr(inst->session));
return rc;
}
int msm_cvp_inst_deinit(struct msm_vidc_inst *inst)
{
int rc = 0;
struct msm_vidc_cvp_buffer *cbuf, *temp;
if (!inst || !inst->core) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
dprintk(VIDC_DBG, "%s: inst %pK (%#x)\n", __func__,
inst, hash32_ptr(inst->session));
rc = msm_comm_try_state(inst, MSM_VIDC_CLOSE_DONE);
if (rc)
dprintk(VIDC_ERR, "%s: close failed\n", __func__);
mutex_lock(&inst->cvpbufs.lock);
list_for_each_entry_safe(cbuf, temp, &inst->cvpbufs.list, list) {
print_cvp_buffer(VIDC_ERR, "unregistered", inst, cbuf);
rc = inst->smem_ops->smem_unmap_dma_buf(inst, &cbuf->smem);
if (rc)
dprintk(VIDC_ERR, "%s: unmap failed\n", __func__);
list_del(&cbuf->list);
kfree(cbuf);
}
mutex_unlock(&inst->cvpbufs.lock);
inst->clk_data.min_freq = 0;
inst->clk_data.ddr_bw = 0;
inst->clk_data.sys_cache_bw = 0;
rc = msm_cvp_scale_clocks_and_bus(inst);
if (rc)
dprintk(VIDC_ERR, "%s: failed to scale_clocks_and_bus\n",
__func__);
return rc;
}
int msm_cvp_inst_init(struct msm_vidc_inst *inst)
{
int rc = 0;
if (!inst) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
dprintk(VIDC_DBG, "%s: inst %pK (%#x)\n", __func__,
inst, hash32_ptr(inst->session));
/* set default frequency */
inst->clk_data.core_id = VIDC_CORE_ID_2;
inst->clk_data.min_freq = 1000;
inst->clk_data.ddr_bw = 1000;
inst->clk_data.sys_cache_bw = 1000;
return rc;
}

25
drivers/media/platform/msm/vidc/msm_cvp.h Normal file
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@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_VIDC_CVP_H_
#define _MSM_VIDC_CVP_H_
#include "msm_vidc_internal.h"
#include "msm_vidc_common.h"
#include "msm_vidc_clocks.h"
#include "msm_vidc_debug.h"
void handle_session_register_buffer_done(enum hal_command_response cmd,
void *resp);
void handle_session_unregister_buffer_done(enum hal_command_response cmd,
void *resp);
int msm_vidc_cvp(struct msm_vidc_inst *inst, struct msm_vidc_arg *arg);
int msm_cvp_inst_init(struct msm_vidc_inst *inst);
int msm_cvp_inst_deinit(struct msm_vidc_inst *inst);
int msm_cvp_inst_pause(struct msm_vidc_inst *inst);
int msm_cvp_inst_resume(struct msm_vidc_inst *inst);
int msm_cvp_ctrl_init(struct msm_vidc_inst *inst,
const struct v4l2_ctrl_ops *ctrl_ops);
#endif

593
drivers/media/platform/msm/vidc/msm_smem.c Normal file
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@ -0,0 +1,593 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#include <asm/dma-iommu.h>
#include <linux/dma-buf.h>
#include <linux/dma-direction.h>
#include <linux/iommu.h>
#include <linux/msm_dma_iommu_mapping.h>
#include <linux/msm_ion.h>
#include <linux/ion_kernel.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "msm_vidc.h"
#include "msm_vidc_debug.h"
#include "msm_vidc_resources.h"
static int msm_dma_get_device_address(struct dma_buf *dbuf, unsigned long align,
dma_addr_t *iova, unsigned long *buffer_size,
unsigned long flags, enum hal_buffer buffer_type,
unsigned long session_type, struct msm_vidc_platform_resources *res,
struct dma_mapping_info *mapping_info)
{
int rc = 0;
struct dma_buf_attachment *attach;
struct sg_table *table = NULL;
struct context_bank_info *cb = NULL;
if (!dbuf || !iova || !buffer_size || !mapping_info) {
dprintk(VIDC_ERR, "Invalid params: %pK, %pK, %pK, %pK\n",
dbuf, iova, buffer_size, mapping_info);
return -EINVAL;
}
if (is_iommu_present(res)) {
cb = msm_smem_get_context_bank(
session_type, (flags & SMEM_SECURE),
res, buffer_type);
if (!cb) {
dprintk(VIDC_ERR,
"%s: Failed to get context bank device\n",
__func__);
rc = -EIO;
goto mem_map_failed;
}
/* Check if the dmabuf size matches expected size */
if (dbuf->size < *buffer_size) {
rc = -EINVAL;
dprintk(VIDC_ERR,
"Size mismatch: Dmabuf size: %zu Expected Size: %lu",
dbuf->size, *buffer_size);
msm_vidc_res_handle_fatal_hw_error(res,
true);
goto mem_buf_size_mismatch;
}
/* Prepare a dma buf for dma on the given device */
attach = dma_buf_attach(dbuf, cb->dev);
if (IS_ERR_OR_NULL(attach)) {
rc = PTR_ERR(attach) ? PTR_ERR(attach) : -ENOMEM;
dprintk(VIDC_ERR, "Failed to attach dmabuf\n");
goto mem_buf_attach_failed;
}
/*
* Get the scatterlist for the given attachment
* Mapping of sg is taken care by map attachment
*/
attach->dma_map_attrs = DMA_ATTR_DELAYED_UNMAP;
/*
* We do not need dma_map function to perform cache operations
* on the whole buffer size and hence pass skip sync flag.
* We do the required cache operations separately for the
* required buffer size
*/
attach->dma_map_attrs |= DMA_ATTR_SKIP_CPU_SYNC;
if (res->sys_cache_present)
attach->dma_map_attrs |=
DMA_ATTR_IOMMU_USE_UPSTREAM_HINT;
table = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
if (IS_ERR_OR_NULL(table)) {
rc = PTR_ERR(table) ? PTR_ERR(table) : -ENOMEM;
dprintk(VIDC_ERR, "Failed to map table\n");
goto mem_map_table_failed;
}
/* debug trace's need to be updated later */
trace_msm_smem_buffer_iommu_op_start("MAP", 0, 0,
align, *iova, *buffer_size);
if (table->sgl) {
*iova = table->sgl->dma_address;
*buffer_size = table->sgl->dma_length;
} else {
dprintk(VIDC_ERR, "sgl is NULL\n");
rc = -ENOMEM;
goto mem_map_sg_failed;
}
mapping_info->dev = cb->dev;
mapping_info->mapping = cb->mapping;
mapping_info->table = table;
mapping_info->attach = attach;
mapping_info->buf = dbuf;
mapping_info->cb_info = (void *)cb;
trace_msm_smem_buffer_iommu_op_end("MAP", 0, 0,
align, *iova, *buffer_size);
} else {
dprintk(VIDC_DBG, "iommu not present, use phys mem addr\n");
}
return 0;
mem_map_sg_failed:
dma_buf_unmap_attachment(attach, table, DMA_BIDIRECTIONAL);
mem_map_table_failed:
dma_buf_detach(dbuf, attach);
mem_buf_size_mismatch:
mem_buf_attach_failed:
mem_map_failed:
return rc;
}
static int msm_dma_put_device_address(u32 flags,
struct dma_mapping_info *mapping_info,
enum hal_buffer buffer_type)
{
int rc = 0;
if (!mapping_info) {
dprintk(VIDC_WARN, "Invalid mapping_info\n");
return -EINVAL;
}
if (!mapping_info->dev || !mapping_info->table ||
!mapping_info->buf || !mapping_info->attach ||
!mapping_info->cb_info) {
dprintk(VIDC_WARN, "Invalid params\n");
return -EINVAL;
}
trace_msm_smem_buffer_iommu_op_start("UNMAP", 0, 0, 0, 0, 0);
dma_buf_unmap_attachment(mapping_info->attach,
mapping_info->table, DMA_BIDIRECTIONAL);
dma_buf_detach(mapping_info->buf, mapping_info->attach);
trace_msm_smem_buffer_iommu_op_end("UNMAP", 0, 0, 0, 0, 0);
mapping_info->dev = NULL;
mapping_info->mapping = NULL;
mapping_info->table = NULL;
mapping_info->attach = NULL;
mapping_info->buf = NULL;
mapping_info->cb_info = NULL;
return rc;
}
struct dma_buf *msm_smem_get_dma_buf(int fd)
{
struct dma_buf *dma_buf;
dma_buf = dma_buf_get(fd);
if (IS_ERR_OR_NULL(dma_buf)) {
dprintk(VIDC_ERR, "Failed to get dma_buf for %d, error %ld\n",
fd, PTR_ERR(dma_buf));
dma_buf = NULL;
}
return dma_buf;
}
void msm_smem_put_dma_buf(void *dma_buf)
{
if (!dma_buf) {
dprintk(VIDC_ERR, "%s: NULL dma_buf\n", __func__);
return;
}
dma_buf_put((struct dma_buf *)dma_buf);
}
int msm_smem_map_dma_buf(struct msm_vidc_inst *inst, struct msm_smem *smem)
{
int rc = 0;
dma_addr_t iova = 0;
u32 temp = 0;
unsigned long buffer_size = 0;
unsigned long align = SZ_4K;
struct dma_buf *dbuf;
unsigned long ion_flags = 0;
if (!inst || !smem) {
dprintk(VIDC_ERR, "%s: Invalid params: %pK %pK\n",
__func__, inst, smem);
rc = -EINVAL;
goto exit;
}
if (smem->refcount) {
smem->refcount++;
goto exit;
}
dbuf = msm_smem_get_dma_buf(smem->fd);
if (!dbuf) {
rc = -EINVAL;
goto exit;
}
smem->dma_buf = dbuf;
rc = dma_buf_get_flags(dbuf, &ion_flags);
if (rc) {
dprintk(VIDC_ERR, "Failed to get dma buf flags: %d\n", rc);
goto exit;
}
if (ion_flags & ION_FLAG_CACHED)
smem->flags |= SMEM_CACHED;
if (ion_flags & ION_FLAG_SECURE)
smem->flags |= SMEM_SECURE;
buffer_size = smem->size;
rc = msm_dma_get_device_address(dbuf, align, &iova, &buffer_size,
smem->flags, smem->buffer_type, inst->session_type,
&(inst->core->resources), &smem->mapping_info);
if (rc) {
dprintk(VIDC_ERR, "Failed to get device address: %d\n", rc);
goto exit;
}
temp = (u32)iova;
if ((dma_addr_t)temp != iova) {
dprintk(VIDC_ERR, "iova(%pa) truncated to %#x", &iova, temp);
rc = -EINVAL;
goto exit;
}
smem->device_addr = (u32)iova + smem->offset;
smem->refcount++;
exit:
return rc;
}
int msm_smem_unmap_dma_buf(struct msm_vidc_inst *inst, struct msm_smem *smem)
{
int rc = 0;
if (!inst || !smem) {
dprintk(VIDC_ERR, "%s: Invalid params: %pK %pK\n",
__func__, inst, smem);
rc = -EINVAL;
goto exit;
}
if (smem->refcount) {
smem->refcount--;
} else {
dprintk(VIDC_WARN,
"unmap called while refcount is zero already\n");
return -EINVAL;
}
if (smem->refcount)
goto exit;
rc = msm_dma_put_device_address(smem->flags, &smem->mapping_info,
smem->buffer_type);
if (rc) {
dprintk(VIDC_ERR, "Failed to put device address: %d\n", rc);
goto exit;
}
msm_smem_put_dma_buf(smem->dma_buf);
smem->device_addr = 0x0;
smem->dma_buf = NULL;
exit:
return rc;
}
static int get_secure_flag_for_buffer_type(
u32 session_type, enum hal_buffer buffer_type)
{
switch (buffer_type) {
case HAL_BUFFER_INPUT:
if (session_type == MSM_VIDC_ENCODER)
return ION_FLAG_CP_PIXEL;
else
return ION_FLAG_CP_BITSTREAM;
case HAL_BUFFER_OUTPUT:
case HAL_BUFFER_OUTPUT2:
if (session_type == MSM_VIDC_ENCODER)
return ION_FLAG_CP_BITSTREAM;
else
return ION_FLAG_CP_PIXEL;
case HAL_BUFFER_INTERNAL_SCRATCH:
return ION_FLAG_CP_BITSTREAM;
case HAL_BUFFER_INTERNAL_SCRATCH_1:
return ION_FLAG_CP_NON_PIXEL;
case HAL_BUFFER_INTERNAL_SCRATCH_2:
return ION_FLAG_CP_PIXEL;
case HAL_BUFFER_INTERNAL_PERSIST:
if (session_type == MSM_VIDC_ENCODER)
return ION_FLAG_CP_NON_PIXEL;
else
return ION_FLAG_CP_BITSTREAM;
case HAL_BUFFER_INTERNAL_PERSIST_1:
return ION_FLAG_CP_NON_PIXEL;
default:
WARN(1, "No matching secure flag for buffer type : %x\n",
buffer_type);
return -EINVAL;
}
}
static int alloc_dma_mem(size_t size, u32 align, u32 flags,
enum hal_buffer buffer_type, int map_kernel,
struct msm_vidc_platform_resources *res, u32 session_type,
struct msm_smem *mem)
{
dma_addr_t iova = 0;
unsigned long buffer_size = 0;
unsigned long heap_mask = 0;
int rc = 0;
int ion_flags = 0;
struct dma_buf *dbuf = NULL;
if (!res) {
dprintk(VIDC_ERR, "%s: NULL res\n", __func__);
return -EINVAL;
}
align = ALIGN(align, SZ_4K);
size = ALIGN(size, SZ_4K);
if (is_iommu_present(res)) {
if (flags & SMEM_ADSP) {
dprintk(VIDC_DBG, "Allocating from ADSP heap\n");
heap_mask = ION_HEAP(ION_ADSP_HEAP_ID);
} else {
heap_mask = ION_HEAP(ION_SYSTEM_HEAP_ID);
}
} else {
dprintk(VIDC_DBG,
"allocate shared memory from adsp heap size %zx align %d\n",
size, align);
heap_mask = ION_HEAP(ION_ADSP_HEAP_ID);
}
if (flags & SMEM_CACHED)
ion_flags |= ION_FLAG_CACHED;
if ((flags & SMEM_SECURE) ||
(buffer_type == HAL_BUFFER_INTERNAL_PERSIST &&
session_type == MSM_VIDC_ENCODER)) {
int secure_flag =
get_secure_flag_for_buffer_type(
session_type, buffer_type);
if (secure_flag < 0) {
rc = secure_flag;
goto fail_shared_mem_alloc;
}
ion_flags |= ION_FLAG_SECURE | secure_flag;
heap_mask = ION_HEAP(ION_SECURE_HEAP_ID);
if (res->slave_side_cp) {
heap_mask = ION_HEAP(ION_CP_MM_HEAP_ID);
size = ALIGN(size, SZ_1M);
align = ALIGN(size, SZ_1M);
}
flags |= SMEM_SECURE;
}
trace_msm_smem_buffer_dma_op_start("ALLOC", (u32)buffer_type,
heap_mask, size, align, flags, map_kernel);
dbuf = ion_alloc(size, heap_mask, ion_flags);
if (IS_ERR_OR_NULL(dbuf)) {
dprintk(VIDC_ERR,
"Failed to allocate shared memory = %zx, %#x\n",
size, flags);
rc = -ENOMEM;
goto fail_shared_mem_alloc;
}
trace_msm_smem_buffer_dma_op_end("ALLOC", (u32)buffer_type,
heap_mask, size, align, flags, map_kernel);
mem->flags = flags;
mem->buffer_type = buffer_type;
mem->offset = 0;
mem->size = size;
mem->dma_buf = dbuf;
mem->kvaddr = NULL;
rc = msm_dma_get_device_address(dbuf, align, &iova,
&buffer_size, flags, buffer_type,
session_type, res, &mem->mapping_info);
if (rc) {
dprintk(VIDC_ERR, "Failed to get device address: %d\n",
rc);
goto fail_device_address;
}
mem->device_addr = (u32)iova;
if ((dma_addr_t)mem->device_addr != iova) {
dprintk(VIDC_ERR, "iova(%pa) truncated to %#x",
&iova, mem->device_addr);
goto fail_device_address;
}
if (map_kernel) {
dma_buf_begin_cpu_access(dbuf, DMA_BIDIRECTIONAL);
mem->kvaddr = dma_buf_vmap(dbuf);
if (!mem->kvaddr) {
dprintk(VIDC_ERR,
"Failed to map shared mem in kernel\n");
rc = -EIO;
goto fail_map;
}
}
dprintk(VIDC_DBG,
"%s: dma_buf = %pK, device_addr = %x, size = %d, kvaddr = %pK, buffer_type = %#x, flags = %#lx\n",
__func__, mem->dma_buf, mem->device_addr, mem->size,
mem->kvaddr, mem->buffer_type, mem->flags);
return rc;
fail_map:
if (map_kernel)
dma_buf_end_cpu_access(dbuf, DMA_BIDIRECTIONAL);
fail_device_address:
dma_buf_put(dbuf);
fail_shared_mem_alloc:
return rc;
}
static int free_dma_mem(struct msm_smem *mem)
{
dprintk(VIDC_DBG,
"%s: dma_buf = %pK, device_addr = %x, size = %d, kvaddr = %pK, buffer_type = %#x\n",
__func__, mem->dma_buf, mem->device_addr, mem->size,
mem->kvaddr, mem->buffer_type);
if (mem->device_addr) {
msm_dma_put_device_address(mem->flags,
&mem->mapping_info, mem->buffer_type);
mem->device_addr = 0x0;
}
if (mem->kvaddr) {
dma_buf_vunmap(mem->dma_buf, mem->kvaddr);
mem->kvaddr = NULL;
dma_buf_end_cpu_access(mem->dma_buf, DMA_BIDIRECTIONAL);
}
if (mem->dma_buf) {
trace_msm_smem_buffer_dma_op_start("FREE",
(u32)mem->buffer_type, -1, mem->size, -1,
mem->flags, -1);
dma_buf_put(mem->dma_buf);
mem->dma_buf = NULL;
trace_msm_smem_buffer_dma_op_end("FREE", (u32)mem->buffer_type,
-1, mem->size, -1, mem->flags, -1);
}
return 0;
}
int msm_smem_alloc(size_t size, u32 align, u32 flags,
enum hal_buffer buffer_type, int map_kernel,
void *res, u32 session_type, struct msm_smem *smem)
{
int rc = 0;
if (!smem || !size) {
dprintk(VIDC_ERR, "%s: NULL smem or %d size\n",
__func__, (u32)size);
return -EINVAL;
}
rc = alloc_dma_mem(size, align, flags, buffer_type, map_kernel,
(struct msm_vidc_platform_resources *)res,
session_type, smem);
return rc;
}
int msm_smem_free(struct msm_smem *smem)
{
int rc = 0;
if (!smem) {
dprintk(VIDC_ERR, "NULL smem passed\n");
return -EINVAL;
}
rc = free_dma_mem(smem);
return rc;
};
int msm_smem_cache_operations(struct dma_buf *dbuf,
enum smem_cache_ops cache_op, unsigned long offset, unsigned long size)
{
int rc = 0;
unsigned long flags = 0;
if (!dbuf) {
dprintk(VIDC_ERR, "%s: Invalid params\n", __func__);
return -EINVAL;
}
/* Return if buffer doesn't support caching */
rc = dma_buf_get_flags(dbuf, &flags);
if (rc) {
dprintk(VIDC_ERR, "%s: dma_buf_get_flags failed, err %d\n", rc);
return rc;
} else if (!(flags & ION_FLAG_CACHED)) {
return rc;
}
switch (cache_op) {
case SMEM_CACHE_CLEAN:
case SMEM_CACHE_CLEAN_INVALIDATE:
rc = dma_buf_begin_cpu_access_partial(dbuf, DMA_TO_DEVICE,
offset, size);
if (rc)
break;
rc = dma_buf_end_cpu_access_partial(dbuf, DMA_TO_DEVICE,
offset, size);
break;
case SMEM_CACHE_INVALIDATE:
rc = dma_buf_begin_cpu_access_partial(dbuf, DMA_TO_DEVICE,
offset, size);
if (rc)
break;
rc = dma_buf_end_cpu_access_partial(dbuf, DMA_FROM_DEVICE,
offset, size);
break;
default:
dprintk(VIDC_ERR, "%s: cache (%d) operation not supported\n",
__func__, cache_op);
rc = -EINVAL;
break;
}
return rc;
}
struct context_bank_info *msm_smem_get_context_bank(u32 session_type,
bool is_secure, struct msm_vidc_platform_resources *res,
enum hal_buffer buffer_type)
{
struct context_bank_info *cb = NULL, *match = NULL;
/*
* HAL_BUFFER_INPUT is directly mapped to bitstream CB in DT
* as the buffer type structure was initially designed
* just for decoder. For Encoder, input should be mapped to
* yuvpixel CB. Persist is mapped to nonpixel CB.
* So swap the buffer types just in this local scope.
*/
if (is_secure && session_type == MSM_VIDC_ENCODER) {
if (buffer_type == HAL_BUFFER_INPUT)
buffer_type = HAL_BUFFER_OUTPUT;
else if (buffer_type == HAL_BUFFER_OUTPUT)
buffer_type = HAL_BUFFER_INPUT;
else if (buffer_type == HAL_BUFFER_INTERNAL_PERSIST)
buffer_type = HAL_BUFFER_INTERNAL_PERSIST_1;
}
list_for_each_entry(cb, &res->context_banks, list) {
if (cb->is_secure == is_secure &&
cb->buffer_type & buffer_type) {
match = cb;
break;
}
}
if (!match)
dprintk(VIDC_ERR,
"%s: cb not found for buffer_type %x, is_secure %d\n",
__func__, buffer_type, is_secure);
return match;
}

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drivers/media/platform/msm/vidc/msm_v4l2_private.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include "msm_v4l2_private.h"
static int convert_from_user(struct msm_vidc_arg *kp, unsigned long arg)
{
int rc = 0;
int i;
struct msm_vidc_arg __user *up = compat_ptr(arg);
if (!kp || !up) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
if (get_user(kp->type, &up->type))
return -EFAULT;
switch (kp->type) {
case MSM_CVP_GET_SESSION_INFO:
{
struct msm_cvp_session_info *k, *u;
k = &kp->data.session;
u = &up->data.session;
if (get_user(k->session_id, &u->session_id))
return -EFAULT;
for (i = 0; i < 10; i++)
if (get_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
case MSM_CVP_REQUEST_POWER:
{
struct msm_cvp_request_power *k, *u;
k = &kp->data.req_power;
u = &up->data.req_power;
if (get_user(k->clock_cycles_a, &u->clock_cycles_a) ||
get_user(k->clock_cycles_b, &u->clock_cycles_b) ||
get_user(k->ddr_bw, &u->ddr_bw) ||
get_user(k->sys_cache_bw, &u->sys_cache_bw))
return -EFAULT;
for (i = 0; i < 8; i++)
if (get_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
case MSM_CVP_REGISTER_BUFFER:
{
struct msm_cvp_buffer *k, *u;
k = &kp->data.regbuf;
u = &up->data.regbuf;
if (get_user(k->type, &u->type) ||
get_user(k->index, &u->index) ||
get_user(k->fd, &u->fd) ||
get_user(k->size, &u->size) ||
get_user(k->offset, &u->offset) ||
get_user(k->pixelformat, &u->pixelformat) ||
get_user(k->flags, &u->flags))
return -EFAULT;
for (i = 0; i < 5; i++)
if (get_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
case MSM_CVP_UNREGISTER_BUFFER:
{
struct msm_cvp_buffer *k, *u;
k = &kp->data.unregbuf;
u = &up->data.unregbuf;
if (get_user(k->type, &u->type) ||
get_user(k->index, &u->index) ||
get_user(k->fd, &u->fd) ||
get_user(k->size, &u->size) ||
get_user(k->offset, &u->offset) ||
get_user(k->pixelformat, &u->pixelformat) ||
get_user(k->flags, &u->flags))
return -EFAULT;
for (i = 0; i < 5; i++)
if (get_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
default:
dprintk(VIDC_ERR, "%s: unknown cmd type 0x%x\n",
__func__, kp->type);
rc = -EINVAL;
break;
}
return rc;
}
static int convert_to_user(struct msm_vidc_arg *kp, unsigned long arg)
{
int rc = 0;
int i;
struct msm_vidc_arg __user *up = compat_ptr(arg);
if (!kp || !up) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
if (put_user(kp->type, &up->type))
return -EFAULT;
switch (kp->type) {
case MSM_CVP_GET_SESSION_INFO:
{
struct msm_cvp_session_info *k, *u;
k = &kp->data.session;
u = &up->data.session;
if (put_user(k->session_id, &u->session_id))
return -EFAULT;
for (i = 0; i < 10; i++)
if (put_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
case MSM_CVP_REQUEST_POWER:
{
struct msm_cvp_request_power *k, *u;
k = &kp->data.req_power;
u = &up->data.req_power;
if (put_user(k->clock_cycles_a, &u->clock_cycles_a) ||
put_user(k->clock_cycles_b, &u->clock_cycles_b) ||
put_user(k->ddr_bw, &u->ddr_bw) ||
put_user(k->sys_cache_bw, &u->sys_cache_bw))
return -EFAULT;
for (i = 0; i < 8; i++)
if (put_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
case MSM_CVP_REGISTER_BUFFER:
{
struct msm_cvp_buffer *k, *u;
k = &kp->data.regbuf;
u = &up->data.regbuf;
if (put_user(k->type, &u->type) ||
put_user(k->index, &u->index) ||
put_user(k->fd, &u->fd) ||
put_user(k->size, &u->size) ||
put_user(k->offset, &u->offset) ||
put_user(k->pixelformat, &u->pixelformat) ||
put_user(k->flags, &u->flags))
return -EFAULT;
for (i = 0; i < 5; i++)
if (put_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
case MSM_CVP_UNREGISTER_BUFFER:
{
struct msm_cvp_buffer *k, *u;
k = &kp->data.unregbuf;
u = &up->data.unregbuf;
if (put_user(k->type, &u->type) ||
put_user(k->index, &u->index) ||
put_user(k->fd, &u->fd) ||
put_user(k->size, &u->size) ||
put_user(k->offset, &u->offset) ||
put_user(k->pixelformat, &u->pixelformat) ||
put_user(k->flags, &u->flags))
return -EFAULT;
for (i = 0; i < 5; i++)
if (put_user(k->reserved[i], &u->reserved[i]))
return -EFAULT;
break;
}
default:
dprintk(VIDC_ERR, "%s: unknown cmd type 0x%x\n",
__func__, kp->type);
rc = -EINVAL;
break;
}
return rc;
}
long msm_v4l2_private(struct file *filp, unsigned int cmd, unsigned long arg)
{
int rc;
struct msm_vidc_inst *inst;
struct msm_vidc_arg karg;
if (!filp || !filp->private_data) {
dprintk(VIDC_ERR, "%s: invalid params\n", __func__);
return -EINVAL;
}
inst = container_of(filp->private_data, struct msm_vidc_inst,
event_handler);
memset(&karg, 0, sizeof(struct msm_vidc_arg));
/*
* the arg points to user space memory and needs
* to be converted to kernel space before using it.
* Check do_video_ioctl() for more details.
*/
if (convert_from_user(&karg, arg))
return -EFAULT;
rc = msm_vidc_private((void *)inst, cmd, &karg);
if (rc) {
dprintk(VIDC_ERR, "%s: failed cmd type %x\n",
__func__, karg.type);
return -EINVAL;
}
if (convert_to_user(&karg, arg))
return -EFAULT;
return rc;
}

14
drivers/media/platform/msm/vidc/msm_v4l2_private.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_V4L2_PRIVATE_H_
#define _MSM_V4L2_PRIVATE_H_
#include <media/msm_vidc_private.h>
#include "msm_vidc_debug.h"
long msm_v4l2_private(struct file *file, unsigned int cmd, unsigned long arg);
#endif

830
drivers/media/platform/msm/vidc/msm_v4l2_vidc.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#include <linux/debugfs.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/version.h>
#include <linux/io.h>
#include "msm_vidc.h"
#include "msm_vidc_common.h"
#include "msm_vidc_debug.h"
#include "msm_vidc_internal.h"
#include "msm_vidc_res_parse.h"
#include "msm_vidc_resources.h"
#include "venus_boot.h"
#include "vidc_hfi_api.h"
#include "msm_v4l2_private.h"
#include "msm_vidc_clocks.h"
#define BASE_DEVICE_NUMBER 32
struct msm_vidc_drv *vidc_driver;
static inline struct msm_vidc_inst *get_vidc_inst(struct file *filp, void *fh)
{
if (!filp->private_data)
return NULL;
return container_of(filp->private_data,
struct msm_vidc_inst, event_handler);
}
static int msm_v4l2_open(struct file *filp)
{
struct video_device *vdev = video_devdata(filp);
struct msm_video_device *vid_dev =
container_of(vdev, struct msm_video_device, vdev);
struct msm_vidc_core *core = video_drvdata(filp);
struct msm_vidc_inst *vidc_inst;
trace_msm_v4l2_vidc_open_start("msm v4l2_open start");
vidc_inst = msm_vidc_open(core->id, vid_dev->type);
if (!vidc_inst) {
dprintk(VIDC_ERR,
"Failed to create video instance, core: %d, type = %d\n",
core->id, vid_dev->type);
return -ENOMEM;
}
clear_bit(V4L2_FL_USES_V4L2_FH, &vdev->flags);
filp->private_data = &(vidc_inst->event_handler);
trace_msm_v4l2_vidc_open_end("msm v4l2_open end");
return 0;
}
static int msm_v4l2_close(struct file *filp)
{
int rc = 0;
struct msm_vidc_inst *vidc_inst;
trace_msm_v4l2_vidc_close_start("msm v4l2_close start");
vidc_inst = get_vidc_inst(filp, NULL);
rc = msm_vidc_close(vidc_inst);
filp->private_data = NULL;
trace_msm_v4l2_vidc_close_end("msm v4l2_close end");
return rc;
}
static int msm_v4l2_querycap(struct file *filp, void *fh,
struct v4l2_capability *cap)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(filp, fh);
return msm_vidc_querycap((void *)vidc_inst, cap);
}
int msm_v4l2_enum_fmt(struct file *file, void *fh,
struct v4l2_fmtdesc *f)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_enum_fmt((void *)vidc_inst, f);
}
int msm_v4l2_s_fmt(struct file *file, void *fh,
struct v4l2_format *f)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_s_fmt((void *)vidc_inst, f);
}
int msm_v4l2_g_fmt(struct file *file, void *fh,
struct v4l2_format *f)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_g_fmt((void *)vidc_inst, f);
}
int msm_v4l2_s_ctrl(struct file *file, void *fh,
struct v4l2_control *a)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_s_ctrl((void *)vidc_inst, a);
}
int msm_v4l2_g_ctrl(struct file *file, void *fh,
struct v4l2_control *a)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_g_ctrl((void *)vidc_inst, a);
}
int msm_v4l2_s_ext_ctrl(struct file *file, void *fh,
struct v4l2_ext_controls *a)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_s_ext_ctrl((void *)vidc_inst, a);
}
int msm_v4l2_g_ext_ctrl(struct file *file, void *fh,
struct v4l2_ext_controls *a)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_g_ext_ctrl((void *)vidc_inst, a);
}
int msm_v4l2_reqbufs(struct file *file, void *fh,
struct v4l2_requestbuffers *b)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_reqbufs((void *)vidc_inst, b);
}
int msm_v4l2_qbuf(struct file *file, void *fh,
struct v4l2_buffer *b)
{
return msm_vidc_qbuf(get_vidc_inst(file, fh), b);
}
int msm_v4l2_dqbuf(struct file *file, void *fh,
struct v4l2_buffer *b)
{
return msm_vidc_dqbuf(get_vidc_inst(file, fh), b);
}
int msm_v4l2_streamon(struct file *file, void *fh,
enum v4l2_buf_type i)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_streamon((void *)vidc_inst, i);
}
int msm_v4l2_streamoff(struct file *file, void *fh,
enum v4l2_buf_type i)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_streamoff((void *)vidc_inst, i);
}
static int msm_v4l2_subscribe_event(struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub)
{
struct msm_vidc_inst *vidc_inst = container_of(fh,
struct msm_vidc_inst, event_handler);
return msm_vidc_subscribe_event((void *)vidc_inst, sub);
}
static int msm_v4l2_unsubscribe_event(struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub)
{
struct msm_vidc_inst *vidc_inst = container_of(fh,
struct msm_vidc_inst, event_handler);
return msm_vidc_unsubscribe_event((void *)vidc_inst, sub);
}
static int msm_v4l2_decoder_cmd(struct file *file, void *fh,
struct v4l2_decoder_cmd *dec)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_comm_cmd((void *)vidc_inst, (union msm_v4l2_cmd *)dec);
}
static int msm_v4l2_encoder_cmd(struct file *file, void *fh,
struct v4l2_encoder_cmd *enc)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_comm_cmd((void *)vidc_inst, (union msm_v4l2_cmd *)enc);
}
static int msm_v4l2_s_parm(struct file *file, void *fh,
struct v4l2_streamparm *a)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_comm_s_parm(vidc_inst, a);
}
static int msm_v4l2_g_parm(struct file *file, void *fh,
struct v4l2_streamparm *a)
{
return 0;
}
static int msm_v4l2_g_crop(struct file *file, void *fh,
struct v4l2_crop *a)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_g_crop(vidc_inst, a);
}
static int msm_v4l2_enum_framesizes(struct file *file, void *fh,
struct v4l2_frmsizeenum *fsize)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_enum_framesizes((void *)vidc_inst, fsize);
}
static int msm_v4l2_queryctrl(struct file *file, void *fh,
struct v4l2_queryctrl *ctrl)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_query_ctrl((void *)vidc_inst, ctrl);
}
static long msm_v4l2_default(struct file *file, void *fh,
bool valid_prio, unsigned int cmd, void *arg)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
return msm_vidc_private((void *)vidc_inst, cmd, arg);
}
const struct v4l2_ioctl_ops msm_v4l2_ioctl_ops = {
.vidioc_querycap = msm_v4l2_querycap,
.vidioc_enum_fmt_vid_cap_mplane = msm_v4l2_enum_fmt,
.vidioc_enum_fmt_vid_out_mplane = msm_v4l2_enum_fmt,
.vidioc_s_fmt_vid_cap_mplane = msm_v4l2_s_fmt,
.vidioc_s_fmt_vid_out_mplane = msm_v4l2_s_fmt,
.vidioc_g_fmt_vid_cap_mplane = msm_v4l2_g_fmt,
.vidioc_g_fmt_vid_out_mplane = msm_v4l2_g_fmt,
.vidioc_reqbufs = msm_v4l2_reqbufs,
.vidioc_qbuf = msm_v4l2_qbuf,
.vidioc_dqbuf = msm_v4l2_dqbuf,
.vidioc_streamon = msm_v4l2_streamon,
.vidioc_streamoff = msm_v4l2_streamoff,
.vidioc_s_ctrl = msm_v4l2_s_ctrl,
.vidioc_g_ctrl = msm_v4l2_g_ctrl,
.vidioc_queryctrl = msm_v4l2_queryctrl,
.vidioc_s_ext_ctrls = msm_v4l2_s_ext_ctrl,
.vidioc_g_ext_ctrls = msm_v4l2_g_ext_ctrl,
.vidioc_subscribe_event = msm_v4l2_subscribe_event,
.vidioc_unsubscribe_event = msm_v4l2_unsubscribe_event,
.vidioc_decoder_cmd = msm_v4l2_decoder_cmd,
.vidioc_encoder_cmd = msm_v4l2_encoder_cmd,
.vidioc_s_parm = msm_v4l2_s_parm,
.vidioc_g_parm = msm_v4l2_g_parm,
.vidioc_g_crop = msm_v4l2_g_crop,
.vidioc_enum_framesizes = msm_v4l2_enum_framesizes,
.vidioc_default = msm_v4l2_default,
};
static const struct v4l2_ioctl_ops msm_v4l2_enc_ioctl_ops = { 0 };
static unsigned int msm_v4l2_poll(struct file *filp,
struct poll_table_struct *pt)
{
struct msm_vidc_inst *vidc_inst = get_vidc_inst(filp, NULL);
return msm_vidc_poll((void *)vidc_inst, filp, pt);
}
static const struct v4l2_file_operations msm_v4l2_vidc_fops = {
.owner = THIS_MODULE,
.open = msm_v4l2_open,
.release = msm_v4l2_close,
.unlocked_ioctl = video_ioctl2,
.compat_ioctl32 = msm_v4l2_private,
.poll = msm_v4l2_poll,
};
void msm_vidc_release_video_device(struct video_device *pvdev)
{
}
static int read_platform_resources(struct msm_vidc_core *core,
struct platform_device *pdev)
{
int rc = 0;
if (!core || !pdev) {
dprintk(VIDC_ERR, "%s: Invalid params %pK %pK\n",
__func__, core, pdev);
return -EINVAL;
}
core->hfi_type = VIDC_HFI_VENUS;
core->resources.pdev = pdev;
if (pdev->dev.of_node) {
/* Target supports DT, parse from it */
rc = read_platform_resources_from_drv_data(core);
rc = read_platform_resources_from_dt(&core->resources);
} else {
dprintk(VIDC_ERR, "pdev node is NULL\n");
rc = -EINVAL;
}
return rc;
}
static int msm_vidc_initialize_core(struct platform_device *pdev,
struct msm_vidc_core *core)
{
int i = 0;
int rc = 0;
if (!core)
return -EINVAL;
rc = read_platform_resources(core, pdev);
if (rc) {
dprintk(VIDC_ERR, "Failed to get platform resources\n");
return rc;
}
INIT_LIST_HEAD(&core->instances);
mutex_init(&core->lock);
core->state = VIDC_CORE_UNINIT;
for (i = SYS_MSG_INDEX(SYS_MSG_START);
i <= SYS_MSG_INDEX(SYS_MSG_END); i++) {
init_completion(&core->completions[i]);
}
INIT_DELAYED_WORK(&core->fw_unload_work, msm_vidc_fw_unload_handler);
INIT_WORK(&core->ssr_work, msm_vidc_ssr_handler);
msm_vidc_init_core_clk_ops(core);
return rc;
}
static ssize_t link_name_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct msm_vidc_core *core = dev_get_drvdata(dev);
if (core)
if (dev == &core->vdev[MSM_VIDC_DECODER].vdev.dev)
return snprintf(buf, PAGE_SIZE, "venus_dec");
else if (dev == &core->vdev[MSM_VIDC_ENCODER].vdev.dev)
return snprintf(buf, PAGE_SIZE, "venus_enc");
else if (dev == &core->vdev[MSM_VIDC_CVP].vdev.dev)
return snprintf(buf, PAGE_SIZE, "venus_cvp");
else
return 0;
else
return 0;
}
static DEVICE_ATTR_RO(link_name);
static ssize_t pwr_collapse_delay_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
unsigned long val = 0;
int rc = 0;
struct msm_vidc_core *core = NULL;
rc = kstrtoul(buf, 0, &val);
if (rc)
return rc;
else if (!val)
return -EINVAL;
core = get_vidc_core(MSM_VIDC_CORE_VENUS);
if (!core)
return -EINVAL;
core->resources.msm_vidc_pwr_collapse_delay = val;
return count;
}
static ssize_t pwr_collapse_delay_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct msm_vidc_core *core = NULL;
core = get_vidc_core(MSM_VIDC_CORE_VENUS);
if (!core)
return -EINVAL;
return snprintf(buf, PAGE_SIZE, "%u\n",
core->resources.msm_vidc_pwr_collapse_delay);
}
static DEVICE_ATTR_RW(pwr_collapse_delay);
static ssize_t thermal_level_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n", vidc_driver->thermal_level);
}
static ssize_t thermal_level_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int rc = 0, val = 0;
rc = kstrtoint(buf, 0, &val);
if (rc || val < 0) {
dprintk(VIDC_WARN,
"Invalid thermal level value: %s\n", buf);
return -EINVAL;
}
dprintk(VIDC_DBG, "Thermal level old %d new %d\n",
vidc_driver->thermal_level, val);
if (val == vidc_driver->thermal_level)
return count;
vidc_driver->thermal_level = val;
msm_comm_handle_thermal_event();
return count;
}
static DEVICE_ATTR_RW(thermal_level);
static ssize_t sku_version_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return scnprintf(buf, PAGE_SIZE, "%d",
vidc_driver->sku_version);
}
static DEVICE_ATTR_RO(sku_version);
static struct attribute *msm_vidc_core_attrs[] = {
&dev_attr_pwr_collapse_delay.attr,
&dev_attr_thermal_level.attr,
&dev_attr_sku_version.attr,
NULL
};
static struct attribute_group msm_vidc_core_attr_group = {
.attrs = msm_vidc_core_attrs,
};
static const struct of_device_id msm_vidc_dt_match[] = {
{.compatible = "qcom,msm-vidc"},
{.compatible = "qcom,msm-vidc,context-bank"},
{.compatible = "qcom,msm-vidc,bus"},
{.compatible = "qcom,msm-vidc,mem-cdsp"},
{}
};
static int msm_vidc_register_video_device(enum session_type sess_type,
int nr, struct msm_vidc_core *core, struct device *dev)
{
int rc = 0;
core->vdev[sess_type].vdev.release =
msm_vidc_release_video_device;
core->vdev[sess_type].vdev.fops = &msm_v4l2_vidc_fops;
core->vdev[sess_type].vdev.ioctl_ops = &msm_v4l2_ioctl_ops;
core->vdev[sess_type].vdev.vfl_dir = VFL_DIR_M2M;
core->vdev[sess_type].type = sess_type;
core->vdev[sess_type].vdev.v4l2_dev = &core->v4l2_dev;
rc = video_register_device(&core->vdev[sess_type].vdev,
VFL_TYPE_GRABBER, nr);
if (rc) {
dprintk(VIDC_ERR, "Failed to register the video device\n");
return rc;
}
video_set_drvdata(&core->vdev[sess_type].vdev, core);
dev = &core->vdev[sess_type].vdev.dev;
rc = device_create_file(dev, &dev_attr_link_name);
if (rc) {
dprintk(VIDC_ERR, "Failed to create video device file\n");
video_unregister_device(&core->vdev[sess_type].vdev);
return rc;
}
return 0;
}
static int msm_vidc_probe_vidc_device(struct platform_device *pdev)
{
int rc = 0;
struct msm_vidc_core *core;
struct device *dev = NULL;
int nr = BASE_DEVICE_NUMBER;
if (!vidc_driver) {
dprintk(VIDC_ERR, "Invalid vidc driver\n");
return -EINVAL;
}
core = kzalloc(sizeof(*core), GFP_KERNEL);
if (!core)
return -ENOMEM;
core->platform_data = vidc_get_drv_data(&pdev->dev);
dev_set_drvdata(&pdev->dev, core);
rc = msm_vidc_initialize_core(pdev, core);
if (rc) {
dprintk(VIDC_ERR, "Failed to init core\n");
goto err_core_init;
}
rc = sysfs_create_group(&pdev->dev.kobj, &msm_vidc_core_attr_group);
if (rc) {
dprintk(VIDC_ERR,
"Failed to create attributes\n");
goto err_core_init;
}
core->id = MSM_VIDC_CORE_VENUS;
rc = v4l2_device_register(&pdev->dev, &core->v4l2_dev);
if (rc) {
dprintk(VIDC_ERR, "Failed to register v4l2 device\n");
goto err_v4l2_register;
}
/* setup the decoder device */
rc = msm_vidc_register_video_device(MSM_VIDC_DECODER,
nr, core, dev);
if (rc) {
dprintk(VIDC_ERR, "Failed to register video decoder\n");
goto err_dec;
}
/* setup the encoder device */
rc = msm_vidc_register_video_device(MSM_VIDC_ENCODER,
nr + 1, core, dev);
if (rc) {
dprintk(VIDC_ERR, "Failed to register video encoder\n");
goto err_enc;
}
/* setup the cvp device */
if (core->resources.domain_cvp) {
rc = msm_vidc_register_video_device(MSM_VIDC_CVP,
nr + 2, core, dev);
if (rc) {
dprintk(VIDC_ERR, "Failed to register video CVP\n");
goto err_cvp;
}
}
/* finish setting up the 'core' */
mutex_lock(&vidc_driver->lock);
if (vidc_driver->num_cores + 1 > MSM_VIDC_CORES_MAX) {
mutex_unlock(&vidc_driver->lock);
dprintk(VIDC_ERR, "Maximum cores already exist, core_no = %d\n",
vidc_driver->num_cores);
goto err_cores_exceeded;
}
vidc_driver->num_cores++;
mutex_unlock(&vidc_driver->lock);
core->device = vidc_hfi_initialize(core->hfi_type, core->id,
&core->resources, &handle_cmd_response);
if (IS_ERR_OR_NULL(core->device)) {
mutex_lock(&vidc_driver->lock);
vidc_driver->num_cores--;
mutex_unlock(&vidc_driver->lock);
rc = PTR_ERR(core->device) ?
PTR_ERR(core->device) : -EBADHANDLE;
if (rc != -EPROBE_DEFER)
dprintk(VIDC_ERR, "Failed to create HFI device\n");
else
dprintk(VIDC_DBG, "msm_vidc: request probe defer\n");
goto err_cores_exceeded;
}
mutex_lock(&vidc_driver->lock);
list_add_tail(&core->list, &vidc_driver->cores);
mutex_unlock(&vidc_driver->lock);
core->debugfs_root = msm_vidc_debugfs_init_core(
core, vidc_driver->debugfs_root);
vidc_driver->sku_version = core->resources.sku_version;
dprintk(VIDC_DBG, "populating sub devices\n");
/*
* Trigger probe for each sub-device i.e. qcom,msm-vidc,context-bank.
* When msm_vidc_probe is called for each sub-device, parse the
* context-bank details and store it in core->resources.context_banks
* list.
*/
rc = of_platform_populate(pdev->dev.of_node, msm_vidc_dt_match, NULL,
&pdev->dev);
if (rc) {
dprintk(VIDC_ERR, "Failed to trigger probe for sub-devices\n");
goto err_fail_sub_device_probe;
}
return rc;
err_fail_sub_device_probe:
vidc_hfi_deinitialize(core->hfi_type, core->device);
err_cores_exceeded:
if (core->resources.domain_cvp) {
device_remove_file(&core->vdev[MSM_VIDC_CVP].vdev.dev,
&dev_attr_link_name);
video_unregister_device(&core->vdev[MSM_VIDC_CVP].vdev);
}
err_cvp:
device_remove_file(&core->vdev[MSM_VIDC_ENCODER].vdev.dev,
&dev_attr_link_name);
video_unregister_device(&core->vdev[MSM_VIDC_ENCODER].vdev);
err_enc:
device_remove_file(&core->vdev[MSM_VIDC_DECODER].vdev.dev,
&dev_attr_link_name);
video_unregister_device(&core->vdev[MSM_VIDC_DECODER].vdev);
err_dec:
v4l2_device_unregister(&core->v4l2_dev);
err_v4l2_register:
sysfs_remove_group(&pdev->dev.kobj, &msm_vidc_core_attr_group);
err_core_init:
dev_set_drvdata(&pdev->dev, NULL);
kfree(core);
return rc;
}
static int msm_vidc_probe_mem_cdsp(struct platform_device *pdev)
{
return read_mem_cdsp_resources_from_dt(pdev);
}
static int msm_vidc_probe_context_bank(struct platform_device *pdev)
{
return read_context_bank_resources_from_dt(pdev);
}
static int msm_vidc_probe_bus(struct platform_device *pdev)
{
return read_bus_resources_from_dt(pdev);
}
static int msm_vidc_probe(struct platform_device *pdev)
{
/*
* Sub devices probe will be triggered by of_platform_populate() towards
* the end of the probe function after msm-vidc device probe is
* completed. Return immediately after completing sub-device probe.
*/
if (of_device_is_compatible(pdev->dev.of_node, "qcom,msm-vidc")) {
return msm_vidc_probe_vidc_device(pdev);
} else if (of_device_is_compatible(pdev->dev.of_node,
"qcom,msm-vidc,bus")) {
return msm_vidc_probe_bus(pdev);
} else if (of_device_is_compatible(pdev->dev.of_node,
"qcom,msm-vidc,context-bank")) {
return msm_vidc_probe_context_bank(pdev);
} else if (of_device_is_compatible(pdev->dev.of_node,
"qcom,msm-vidc,mem-cdsp")) {
return msm_vidc_probe_mem_cdsp(pdev);
}
/* How did we end up here? */
MSM_VIDC_ERROR(1);
return -EINVAL;
}
static int msm_vidc_remove(struct platform_device *pdev)
{
int rc = 0;
struct msm_vidc_core *core;
if (!pdev) {
dprintk(VIDC_ERR, "%s invalid input %pK", __func__, pdev);
return -EINVAL;
}
core = dev_get_drvdata(&pdev->dev);
if (!core) {
dprintk(VIDC_ERR, "%s invalid core", __func__);
return -EINVAL;
}
if (core->resources.use_non_secure_pil)
venus_boot_deinit();
vidc_hfi_deinitialize(core->hfi_type, core->device);
if (core->resources.domain_cvp) {
device_remove_file(&core->vdev[MSM_VIDC_CVP].vdev.dev,
&dev_attr_link_name);
video_unregister_device(&core->vdev[MSM_VIDC_CVP].vdev);
}
device_remove_file(&core->vdev[MSM_VIDC_ENCODER].vdev.dev,
&dev_attr_link_name);
video_unregister_device(&core->vdev[MSM_VIDC_ENCODER].vdev);
device_remove_file(&core->vdev[MSM_VIDC_DECODER].vdev.dev,
&dev_attr_link_name);
video_unregister_device(&core->vdev[MSM_VIDC_DECODER].vdev);
v4l2_device_unregister(&core->v4l2_dev);
msm_vidc_free_platform_resources(&core->resources);
sysfs_remove_group(&pdev->dev.kobj, &msm_vidc_core_attr_group);
dev_set_drvdata(&pdev->dev, NULL);
mutex_destroy(&core->lock);
kfree(core);
return rc;
}
static int msm_vidc_pm_suspend(struct device *dev)
{
int rc = 0;
struct msm_vidc_core *core;
/*
* Bail out if
* - driver possibly not probed yet
* - not the main device. We don't support power management on
* subdevices (e.g. context banks)
*/
if (!dev || !dev->driver ||
!of_device_is_compatible(dev->of_node, "qcom,msm-vidc"))
return 0;
core = dev_get_drvdata(dev);
if (!core) {
dprintk(VIDC_ERR, "%s invalid core\n", __func__);
return -EINVAL;
}
rc = msm_vidc_suspend(core->id);
if (rc == -ENOTSUPP)
rc = 0;
else if (rc)
dprintk(VIDC_WARN, "Failed to suspend: %d\n", rc);
return rc;
}
static int msm_vidc_pm_resume(struct device *dev)
{
dprintk(VIDC_INFO, "%s\n", __func__);
return 0;
}
static const struct dev_pm_ops msm_vidc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_vidc_pm_suspend, msm_vidc_pm_resume)
};
MODULE_DEVICE_TABLE(of, msm_vidc_dt_match);
static struct platform_driver msm_vidc_driver = {
.probe = msm_vidc_probe,
.remove = msm_vidc_remove,
.driver = {
.name = "msm_vidc_v4l2",
.of_match_table = msm_vidc_dt_match,
.pm = &msm_vidc_pm_ops,
},
};
static int __init msm_vidc_init(void)
{
int rc = 0;
vidc_driver = kzalloc(sizeof(*vidc_driver),
GFP_KERNEL);
if (!vidc_driver) {
dprintk(VIDC_ERR,
"Failed to allocate memroy for msm_vidc_drv\n");
return -ENOMEM;
}
INIT_LIST_HEAD(&vidc_driver->cores);
mutex_init(&vidc_driver->lock);
vidc_driver->debugfs_root = msm_vidc_debugfs_init_drv();
if (!vidc_driver->debugfs_root)
dprintk(VIDC_ERR,
"Failed to create debugfs for msm_vidc\n");
rc = platform_driver_register(&msm_vidc_driver);
if (rc) {
dprintk(VIDC_ERR,
"Failed to register platform driver\n");
debugfs_remove_recursive(vidc_driver->debugfs_root);
kfree(vidc_driver);
vidc_driver = NULL;
}
return rc;
}
static void __exit msm_vidc_exit(void)
{
platform_driver_unregister(&msm_vidc_driver);
debugfs_remove_recursive(vidc_driver->debugfs_root);
mutex_destroy(&vidc_driver->lock);
kfree(vidc_driver);
vidc_driver = NULL;
}
module_init(msm_vidc_init);
module_exit(msm_vidc_exit);
MODULE_LICENSE("GPL v2");

1308
drivers/media/platform/msm/vidc/msm_vdec.c Normal file
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drivers/media/platform/msm/vidc/msm_vdec.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_VDEC_H_
#define _MSM_VDEC_H_
#include "msm_vidc.h"
#include "msm_vidc_internal.h"
#define MSM_VDEC_DVC_NAME "msm_vidc_vdec"
int msm_vdec_inst_init(struct msm_vidc_inst *inst);
int msm_vdec_ctrl_init(struct msm_vidc_inst *inst,
const struct v4l2_ctrl_ops *ctrl_ops);
int msm_vdec_enum_fmt(void *instance, struct v4l2_fmtdesc *f);
int msm_vdec_s_fmt(void *instance, struct v4l2_format *f);
int msm_vdec_s_ctrl(void *instance, struct v4l2_ctrl *ctrl);
int msm_vdec_g_ctrl(void *instance, struct v4l2_ctrl *ctrl);
#endif

2272
drivers/media/platform/msm/vidc/msm_venc.c Normal file
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drivers/media/platform/msm/vidc/msm_venc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_VENC_H_
#define _MSM_VENC_H_
#include "msm_vidc.h"
#include "msm_vidc_internal.h"
#define MSM_VENC_DVC_NAME "msm_vidc_venc"
int msm_venc_inst_init(struct msm_vidc_inst *inst);
int msm_venc_ctrl_init(struct msm_vidc_inst *inst,
const struct v4l2_ctrl_ops *ctrl_ops);
int msm_venc_enum_fmt(void *instance, struct v4l2_fmtdesc *f);
int msm_venc_s_fmt(void *instance, struct v4l2_format *f);
int msm_venc_s_ctrl(void *instance, struct v4l2_ctrl *ctrl);
#endif

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drivers/media/platform/msm/vidc/msm_vidc.c Normal file
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drivers/media/platform/msm/vidc/msm_vidc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_VIDC_H_
#define _MSM_VIDC_H_
#include <linux/poll.h>
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/msm_ion.h>
#include <media/msm_vidc_private.h>
#include <media/msm_vidc_utils.h>
#define HAL_BUFFER_MAX 0xe
#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_MODE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 22)
enum v4l2_mpeg_vidc_video_decoder_multi_stream {
V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_PRIMARY = 0,
V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_SECONDARY = 1,
};
enum smem_type {
SMEM_DMA = 1,
};
enum smem_prop {
SMEM_UNCACHED = 0x1,
SMEM_CACHED = 0x2,
SMEM_SECURE = 0x4,
SMEM_ADSP = 0x8,
};
/* NOTE: if you change this enum you MUST update the
* "buffer-type-tz-usage-table" for any affected target
* in arch/arm/boot/dts/<arch>.dtsi
*/
enum hal_buffer {
HAL_BUFFER_NONE = 0x0,
HAL_BUFFER_INPUT = 0x1,
HAL_BUFFER_OUTPUT = 0x2,
HAL_BUFFER_OUTPUT2 = 0x4,
HAL_BUFFER_EXTRADATA_INPUT = 0x8,
HAL_BUFFER_EXTRADATA_OUTPUT = 0x10,
HAL_BUFFER_EXTRADATA_OUTPUT2 = 0x20,
HAL_BUFFER_INTERNAL_SCRATCH = 0x40,
HAL_BUFFER_INTERNAL_SCRATCH_1 = 0x80,
HAL_BUFFER_INTERNAL_SCRATCH_2 = 0x100,
HAL_BUFFER_INTERNAL_PERSIST = 0x200,
HAL_BUFFER_INTERNAL_PERSIST_1 = 0x400,
HAL_BUFFER_INTERNAL_CMD_QUEUE = 0x800,
HAL_BUFFER_INTERNAL_RECON = 0x1000,
};
struct dma_mapping_info {
struct device *dev;
struct dma_iommu_mapping *mapping;
struct sg_table *table;
struct dma_buf_attachment *attach;
struct dma_buf *buf;
void *cb_info;
};
struct msm_smem {
u32 refcount;
int fd;
void *dma_buf;
void *kvaddr;
u32 device_addr;
dma_addr_t dma_handle;
unsigned int offset;
unsigned int size;
unsigned long flags;
enum hal_buffer buffer_type;
struct dma_mapping_info mapping_info;
};
enum smem_cache_ops {
SMEM_CACHE_CLEAN,
SMEM_CACHE_INVALIDATE,
SMEM_CACHE_CLEAN_INVALIDATE,
};
enum core_id {
MSM_VIDC_CORE_VENUS = 0,
MSM_VIDC_CORE_Q6,
MSM_VIDC_CORES_MAX,
};
enum session_type {
MSM_VIDC_ENCODER = 0,
MSM_VIDC_DECODER,
MSM_VIDC_CVP,
MSM_VIDC_UNKNOWN,
MSM_VIDC_MAX_DEVICES = MSM_VIDC_UNKNOWN,
};
union msm_v4l2_cmd {
struct v4l2_decoder_cmd dec;
struct v4l2_encoder_cmd enc;
};
void *msm_vidc_open(int core_id, int session_type);
int msm_vidc_close(void *instance);
int msm_vidc_suspend(int core_id);
int msm_vidc_querycap(void *instance, struct v4l2_capability *cap);
int msm_vidc_enum_fmt(void *instance, struct v4l2_fmtdesc *f);
int msm_vidc_s_fmt(void *instance, struct v4l2_format *f);
int msm_vidc_g_fmt(void *instance, struct v4l2_format *f);
int msm_vidc_s_ctrl(void *instance, struct v4l2_control *a);
int msm_vidc_s_ext_ctrl(void *instance, struct v4l2_ext_controls *a);
int msm_vidc_g_ext_ctrl(void *instance, struct v4l2_ext_controls *a);
int msm_vidc_g_ctrl(void *instance, struct v4l2_control *a);
int msm_vidc_reqbufs(void *instance, struct v4l2_requestbuffers *b);
int msm_vidc_release_buffer(void *instance, int buffer_type,
unsigned int buffer_index);
int msm_vidc_qbuf(void *instance, struct v4l2_buffer *b);
int msm_vidc_dqbuf(void *instance, struct v4l2_buffer *b);
int msm_vidc_streamon(void *instance, enum v4l2_buf_type i);
int msm_vidc_query_ctrl(void *instance, struct v4l2_queryctrl *ctrl);
int msm_vidc_streamoff(void *instance, enum v4l2_buf_type i);
int msm_vidc_comm_cmd(void *instance, union msm_v4l2_cmd *cmd);
int msm_vidc_poll(void *instance, struct file *filp,
struct poll_table_struct *pt);
int msm_vidc_subscribe_event(void *instance,
const struct v4l2_event_subscription *sub);
int msm_vidc_unsubscribe_event(void *instance,
const struct v4l2_event_subscription *sub);
int msm_vidc_dqevent(void *instance, struct v4l2_event *event);
int msm_vidc_g_crop(void *instance, struct v4l2_crop *a);
int msm_vidc_enum_framesizes(void *instance, struct v4l2_frmsizeenum *fsize);
int msm_vidc_private(void *vidc_inst, unsigned int cmd,
struct msm_vidc_arg *arg);
#endif

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drivers/media/platform/msm/vidc/msm_vidc_ar50_dyn_gov.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include "governor.h"
#include "fixedpoint.h"
#include "msm_vidc_internal.h"
#include "msm_vidc_debug.h"
#include "vidc_hfi_api.h"
#define COMPRESSION_RATIO_MAX 5
enum governor_mode {
GOVERNOR_DDR,
GOVERNOR_LLCC,
};
struct governor {
enum governor_mode mode;
struct devfreq_governor devfreq_gov;
};
/*
* Minimum dimensions that the governor is willing to calculate
* bandwidth for. This means that anything bandwidth(0, 0) ==
* bandwidth(BASELINE_DIMENSIONS.width, BASELINE_DIMENSIONS.height)
*/
static const struct {
int height, width;
} BASELINE_DIMENSIONS = {
.width = 1280,
.height = 720,
};
/*
* These are hardcoded AB values that the governor votes for in certain
* situations, where a certain bus frequency is desired. It isn't exactly
* scalable since different platforms have different bus widths, but we'll
* deal with that in the future.
*/
static const unsigned long NOMINAL_BW_MBPS = 6000 /* ideally 320 Mhz */,
SVS_BW_MBPS = 2000 /* ideally 100 Mhz */;
/* converts Mbps to bps (the "b" part can be bits or bytes based on context) */
#define kbps(__mbps) ((__mbps) * 1000)
#define bps(__mbps) (kbps(__mbps) * 1000)
#define GENERATE_COMPRESSION_PROFILE(__bpp, __worst) { \
.bpp = __bpp, \
.ratio = __worst, \
}
/*
* The below table is a structural representation of the following table:
* Resolution | Bitrate | Compression Ratio |
* ............|............|.........................................|
* Width Height|Average High|Avg_8bpc Worst_8bpc Avg_10bpc Worst_10bpc|
* 1280 720| 7 14| 1.69 1.28 1.49 1.23|
* 1920 1080| 20 40| 1.69 1.28 1.49 1.23|
* 2560 1440| 32 64| 2.2 1.26 1.97 1.22|
* 3840 2160| 42 84| 2.2 1.26 1.97 1.22|
* 4096 2160| 44 88| 2.2 1.26 1.97 1.22|
* 4096 2304| 48 96| 2.2 1.26 1.97 1.22|
*/
static struct lut {
int frame_size; /* width x height */
int frame_rate;
unsigned long bitrate;
struct {
int bpp;
fp_t ratio;
} compression_ratio[COMPRESSION_RATIO_MAX];
} const LUT[] = {
{
.frame_size = 1280 * 720,
.frame_rate = 30,
.bitrate = 14,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 28, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 23, 100)),
}
},
{
.frame_size = 1280 * 720,
.frame_rate = 60,
.bitrate = 22,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 28, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 23, 100)),
}
},
{
.frame_size = 1920 * 1088,
.frame_rate = 30,
.bitrate = 40,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 28, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 23, 100)),
}
},
{
.frame_size = 1920 * 1088,
.frame_rate = 60,
.bitrate = 64,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 28, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 23, 100)),
}
},
{
.frame_size = 2560 * 1440,
.frame_rate = 30,
.bitrate = 64,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
{
.frame_size = 2560 * 1440,
.frame_rate = 60,
.bitrate = 102,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
{
.frame_size = 3840 * 2160,
.frame_rate = 30,
.bitrate = 84,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
{
.frame_size = 3840 * 2160,
.frame_rate = 60,
.bitrate = 134,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
{
.frame_size = 4096 * 2160,
.frame_rate = 30,
.bitrate = 88,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
{
.frame_size = 4096 * 2160,
.frame_rate = 60,
.bitrate = 141,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
{
.frame_size = 4096 * 2304,
.frame_rate = 30,
.bitrate = 96,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
{
.frame_size = 4096 * 2304,
.frame_rate = 60,
.bitrate = 154,
.compression_ratio = {
GENERATE_COMPRESSION_PROFILE(8,
FP(1, 26, 100)),
GENERATE_COMPRESSION_PROFILE(10,
FP(1, 22, 100)),
}
},
};
static struct lut const *__lut(int width, int height, int fps)
{
int frame_size = height * width, c = 0;
do {
if (LUT[c].frame_size >= frame_size && LUT[c].frame_rate >= fps)
return &LUT[c];
} while (++c < ARRAY_SIZE(LUT));
return &LUT[ARRAY_SIZE(LUT) - 1];
}
static fp_t __compression_ratio(struct lut const *entry, int bpp)
{
int c = 0;
for (c = 0; c < COMPRESSION_RATIO_MAX; ++c) {
if (entry->compression_ratio[c].bpp == bpp)
return entry->compression_ratio[c].ratio;
}
WARN(true, "Shouldn't be here, LUT possibly corrupted?\n");
return FP_ZERO; /* impossible */
}
#define DUMP_HEADER_MAGIC 0xdeadbeef
#define DUMP_FP_FMT "%FP" /* special format for fp_t */
struct dump {
char *key;
char *format;
size_t val;
};
static void __dump(struct dump dump[], int len)
{
int c = 0;
for (c = 0; c < len; ++c) {
char format_line[128] = "", formatted_line[128] = "";
if (dump[c].val == DUMP_HEADER_MAGIC) {
snprintf(formatted_line, sizeof(formatted_line), "%s\n",
dump[c].key);
} else {
bool fp_format = !strcmp(dump[c].format, DUMP_FP_FMT);
if (!fp_format) {
snprintf(format_line, sizeof(format_line),
" %-35s: %s\n", dump[c].key,
dump[c].format);
snprintf(formatted_line, sizeof(formatted_line),
format_line, dump[c].val);
} else {
size_t integer_part, fractional_part;
integer_part = fp_int(dump[c].val);
fractional_part = fp_frac(dump[c].val);
snprintf(formatted_line, sizeof(formatted_line),
" %-35s: %zd + %zd/%zd\n",
dump[c].key, integer_part,
fractional_part,
fp_frac_base());
}
}
dprintk(VIDC_DBG, "%s", formatted_line);
}
}
static unsigned long __calculate_vpe(struct vidc_bus_vote_data *d,
enum governor_mode gm)
{
return 0;
}
static bool __ubwc(enum hal_uncompressed_format f)
{
switch (f) {
case HAL_COLOR_FORMAT_NV12_UBWC:
case HAL_COLOR_FORMAT_NV12_TP10_UBWC:
return true;
default:
return false;
}
}
static int __bpp(enum hal_uncompressed_format f)
{
switch (f) {
case HAL_COLOR_FORMAT_NV12:
case HAL_COLOR_FORMAT_NV21:
case HAL_COLOR_FORMAT_NV12_UBWC:
return 8;
case HAL_COLOR_FORMAT_NV12_TP10_UBWC:
case HAL_COLOR_FORMAT_P010:
return 10;
default:
dprintk(VIDC_ERR,
"What's this? We don't support this colorformat (%x)",
f);
return INT_MAX;
}
}
static unsigned long __calculate_decoder(struct vidc_bus_vote_data *d,
enum governor_mode gm)
{
/*
* XXX: Don't fool around with any of the hardcoded numbers unless you
* know /exactly/ what you're doing. Many of these numbers are
* measured heuristics and hardcoded numbers taken from the firmware.
*/
/* Decoder parameters */
int width, height, lcu_size, dpb_bpp, opb_bpp, fps, opb_factor;
bool unified_dpb_opb, dpb_compression_enabled, opb_compression_enabled,
llc_ref_read_l2_cache_enabled = false,
llc_vpss_ds_line_buf_enabled = false;
fp_t dpb_opb_scaling_ratio, dpb_read_compression_factor,
dpb_write_compression_factor, opb_compression_factor,
qsmmu_bw_overhead_factor, height_ratio;
/* Derived parameters */
int lcu_per_frame, tnbr_per_lcu, colocated_bytes_per_lcu;
unsigned long bitrate;
fp_t bins_to_bit_factor, dpb_write_factor, ten_bpc_packing_factor,
ten_bpc_bpp_factor, vsp_read_factor, vsp_write_factor,
bw_for_1x_8bpc, dpb_bw_for_1x,
motion_vector_complexity = 0, row_cache_penalty = 0, opb_bw = 0,
dpb_total = 0;
/* Output parameters */
struct {
fp_t vsp_read, vsp_write, collocated_read, collocated_write,
line_buffer_read, line_buffer_write, recon_read,
recon_write, opb_read, opb_write, dpb_read, dpb_write,
total;
} ddr = {0};
struct {
fp_t dpb_read, opb_read, total;
} llc = {0};
unsigned long ret = 0;
unsigned int integer_part, frac_part;
width = max(d->input_width, BASELINE_DIMENSIONS.width);
height = max(d->input_height, BASELINE_DIMENSIONS.height);
lcu_size = d->lcu_size;
dpb_bpp = d->num_formats >= 1 ? __bpp(d->color_formats[0]) : INT_MAX;
opb_bpp = d->num_formats >= 2 ? __bpp(d->color_formats[1]) : dpb_bpp;
fps = d->fps;
unified_dpb_opb = d->num_formats == 1;
dpb_opb_scaling_ratio = fp_div(FP_INT(
(int)(d->input_width * d->input_height)),
FP_INT((int)(d->output_width * d->output_height)));
height_ratio = fp_div(d->input_height, d->output_height);
dpb_compression_enabled = d->num_formats >= 1 &&
__ubwc(d->color_formats[0]);
opb_compression_enabled = d->num_formats >= 2 &&
__ubwc(d->color_formats[1]);
/*
* Convert Q16 number into Integer and Fractional part upto 2 places.
* Ex : 105752 / 65536 = 1.61; 1.61 in Q16 = 105752;
* Integer part = 105752 / 65536 = 1;
* Reminder = 105752 - 1 * 65536 = 40216;
* Fractional part = 40216 * 100 / 65536 = 61;
* Now converto to FP(1, 61, 100) for below code.
*/
integer_part = d->compression_ratio >> 16;
frac_part =
((d->compression_ratio - (integer_part << 16)) * 100) >> 16;
dpb_read_compression_factor = FP(integer_part, frac_part, 100);
integer_part = d->complexity_factor >> 16;
frac_part =
((d->complexity_factor - (integer_part << 16)) * 100) >> 16;
motion_vector_complexity = FP(integer_part, frac_part, 100);
dpb_write_compression_factor = !dpb_compression_enabled ? FP_ONE :
__compression_ratio(__lut(width, height, fps), opb_bpp);
dpb_write_compression_factor = d->use_dpb_read ?
dpb_read_compression_factor :
dpb_write_compression_factor;
opb_compression_factor = !opb_compression_enabled ? FP_ONE :
__compression_ratio(__lut(width, height, fps), opb_bpp);
llc_ref_read_l2_cache_enabled = llc_vpss_ds_line_buf_enabled = false;
if (d->use_sys_cache) {
llc_ref_read_l2_cache_enabled = true;
llc_vpss_ds_line_buf_enabled = true;
}
/* Derived parameters setup */
lcu_per_frame = DIV_ROUND_UP(width, lcu_size) *
DIV_ROUND_UP(height, lcu_size);
bitrate = __lut(width, height, fps)->bitrate;
bins_to_bit_factor = d->work_mode == VIDC_WORK_MODE_1 ?
FP_INT(0) : FP_INT(4);
vsp_read_factor = bins_to_bit_factor + FP_INT(2);
dpb_write_factor = FP(1, 5, 100);
ten_bpc_packing_factor = FP(1, 67, 1000);
ten_bpc_bpp_factor = FP(1, 1, 4);
vsp_write_factor = bins_to_bit_factor;
tnbr_per_lcu = lcu_size == 16 ? 128 :
lcu_size == 32 ? 64 : 128;
colocated_bytes_per_lcu = lcu_size == 16 ? 16 :
lcu_size == 32 ? 64 : 256;
/* ........................................ for DDR */
ddr.vsp_read = fp_div(fp_mult(FP_INT(bitrate),
vsp_read_factor), FP_INT(8));
ddr.vsp_write = fp_div(fp_mult(FP_INT(bitrate),
vsp_write_factor), FP_INT(8));
ddr.collocated_read = FP_INT(lcu_per_frame *
colocated_bytes_per_lcu * fps / bps(1));
ddr.collocated_write = FP_INT(lcu_per_frame *
colocated_bytes_per_lcu * fps / bps(1));
ddr.line_buffer_read = FP_INT(tnbr_per_lcu *
lcu_per_frame * fps / bps(1));
ddr.line_buffer_write = ddr.line_buffer_read;
bw_for_1x_8bpc = fp_div(FP_INT((int)(width * height)), FP_INT(32 * 8));
bw_for_1x_8bpc = fp_mult(bw_for_1x_8bpc,
fp_div(FP_INT(((int)(256 * fps))), FP_INT(1000 * 1000)));
dpb_bw_for_1x = dpb_bpp == 8 ? bw_for_1x_8bpc :
fp_mult(bw_for_1x_8bpc, fp_mult(ten_bpc_packing_factor,
ten_bpc_bpp_factor));
ddr.dpb_read = fp_div(fp_mult(fp_mult(dpb_bw_for_1x,
motion_vector_complexity), dpb_write_factor),
dpb_read_compression_factor);
ddr.dpb_write = fp_div(fp_mult(dpb_bw_for_1x, dpb_write_factor),
dpb_write_compression_factor);
dpb_total = ddr.dpb_read + ddr.dpb_write;
if (llc_ref_read_l2_cache_enabled) {
row_cache_penalty = FP(1, 30, 100);
ddr.dpb_read = fp_div(ddr.dpb_read, row_cache_penalty);
llc.dpb_read = dpb_total - ddr.dpb_read;
}
opb_factor = dpb_bpp == 8 ? 8 : 4;
ddr.opb_read = unified_dpb_opb ? 0 : opb_compression_enabled ?
fp_div(fp_mult(fp_div(dpb_bw_for_1x, dpb_opb_scaling_ratio),
FP_INT(opb_factor)), height_ratio) : 0;
ddr.opb_write = unified_dpb_opb ? 0 : opb_compression_enabled ?
ddr.dpb_read : fp_div(fp_div(fp_mult(dpb_bw_for_1x,
FP(1, 50, 100)), dpb_opb_scaling_ratio),
opb_compression_factor);
if (llc_vpss_ds_line_buf_enabled) {
llc.opb_read = ddr.opb_read;
ddr.opb_write -= ddr.opb_read;
ddr.opb_read = 0;
}
ddr.total = ddr.vsp_read + ddr.vsp_write +
ddr.collocated_read + ddr.collocated_write +
ddr.opb_read + ddr.opb_write +
ddr.dpb_read + ddr.dpb_write;
qsmmu_bw_overhead_factor = FP(1, 3, 100);
ddr.total = fp_mult(ddr.total, qsmmu_bw_overhead_factor);
llc.total = llc.dpb_read + llc.opb_read;
/* Dump all the variables for easier debugging */
if (msm_vidc_dyn_gov_debug) {
struct dump dump[] = {
{"DECODER PARAMETERS", "", DUMP_HEADER_MAGIC},
{"LCU size", "%d", lcu_size},
{"DPB bitdepth", "%d", dpb_bpp},
{"frame rate", "%d", fps},
{"DPB/OPB unified", "%d", unified_dpb_opb},
{"DPB/OPB downscaling ratio", DUMP_FP_FMT,
dpb_opb_scaling_ratio},
{"DPB compression", "%d", dpb_compression_enabled},
{"OPB compression", "%d", opb_compression_enabled},
{"DPB Read compression factor", DUMP_FP_FMT,
dpb_read_compression_factor},
{"DPB Write compression factor", DUMP_FP_FMT,
dpb_write_compression_factor},
{"OPB compression factor", DUMP_FP_FMT,
opb_compression_factor},
{"frame width", "%d", width},
{"frame height", "%d", height},
{"DERIVED PARAMETERS (1)", "", DUMP_HEADER_MAGIC},
{"LCUs/frame", "%d", lcu_per_frame},
{"bitrate (Mbit/sec)", "%d", bitrate},
{"bins to bit factor", DUMP_FP_FMT, bins_to_bit_factor},
{"DPB write factor", DUMP_FP_FMT, dpb_write_factor},
{"10bpc packing factor", DUMP_FP_FMT,
ten_bpc_packing_factor},
{"10bpc,BPP factor", DUMP_FP_FMT, ten_bpc_bpp_factor},
{"VSP read factor", DUMP_FP_FMT, vsp_read_factor},
{"VSP write factor", DUMP_FP_FMT, vsp_write_factor},
{"TNBR/LCU", "%d", tnbr_per_lcu},
{"colocated bytes/LCU", "%d", colocated_bytes_per_lcu},
{"B/W for 1x (NV12 8bpc)", DUMP_FP_FMT, bw_for_1x_8bpc},
{"DPB B/W For 1x (NV12)", DUMP_FP_FMT, dpb_bw_for_1x},
{"DERIVED PARAMETERS (2)", "", DUMP_HEADER_MAGIC},
{"MV complexity", DUMP_FP_FMT, motion_vector_complexity},
{"row cache penalty", DUMP_FP_FMT, row_cache_penalty},
{"qsmmu_bw_overhead_factor", DUMP_FP_FMT,
qsmmu_bw_overhead_factor},
{"OPB B/W (single instance)", DUMP_FP_FMT, opb_bw},
{"INTERMEDIATE DDR B/W", "", DUMP_HEADER_MAGIC},
{"VSP read", DUMP_FP_FMT, ddr.vsp_read},
{"VSP write", DUMP_FP_FMT, ddr.vsp_write},
{"collocated read", DUMP_FP_FMT, ddr.collocated_read},
{"collocated write", DUMP_FP_FMT, ddr.collocated_write},
{"line buffer read", DUMP_FP_FMT, ddr.line_buffer_read},
{"line buffer write", DUMP_FP_FMT, ddr.line_buffer_write},
{"recon read", DUMP_FP_FMT, ddr.recon_read},
{"recon write", DUMP_FP_FMT, ddr.recon_write},
{"OPB read", DUMP_FP_FMT, ddr.opb_read},
{"OPB write", DUMP_FP_FMT, ddr.opb_write},
{"DPB read", DUMP_FP_FMT, ddr.dpb_read},
{"DPB write", DUMP_FP_FMT, ddr.dpb_write},
{"LLC DPB read", DUMP_FP_FMT, llc.dpb_read},
{"LLC OPB read", DUMP_FP_FMT, llc.opb_read},
};
__dump(dump, ARRAY_SIZE(dump));
}
switch (gm) {
case GOVERNOR_DDR:
ret = kbps(fp_round(ddr.total));
break;
case GOVERNOR_LLCC:
ret = kbps(fp_round(llc.total));
break;
default:
dprintk(VIDC_ERR, "%s - Unknown governor\n", __func__);
}
return ret;
}
static unsigned long __calculate_encoder(struct vidc_bus_vote_data *d,
enum governor_mode gm)
{
/*
* XXX: Don't fool around with any of the hardcoded numbers unless you
* know /exactly/ what you're doing. Many of these numbers are
* measured heuristics and hardcoded numbers taken from the firmware.
*/
/* Encoder Parameters */
int width, height, fps, dpb_bpp, lcu_per_frame, lcu_size,
vertical_tile_width, colocated_bytes_per_lcu, bitrate,
ref_overlap_bw_factor;
enum hal_uncompressed_format dpb_color_format, original_color_format;
bool dpb_compression_enabled, original_compression_enabled,
work_mode_1, low_power, rotation, cropping_or_scaling,
b_frames_enabled = false,
llc_dual_core_ref_read_buf_enabled = false,
llc_top_line_buf_enabled = false,
llc_ref_chroma_cache_enabled = false;
fp_t dpb_compression_factor, original_compression_factor,
input_compression_factor, qsmmu_bw_overhead_factor,
ref_y_bw_factor, ref_cb_cr_bw_factor, ten_bpc_bpp_factor,
bw_for_1x_8bpc, dpb_bw_for_1x, ref_cb_cr_read,
bins_to_bit_factor, ref_y_read, ten_bpc_packing_factor,
dpb_write_factor, ref_overlap_bw, llc_ref_y_read,
llc_ref_cb_cr_read;
fp_t integer_part, frac_part;
unsigned long ret = 0;
/* Output parameters */
struct {
fp_t vsp_read, vsp_write, collocated_read, collocated_write,
line_buffer_read, line_buffer_write, original_read,
original_write, dpb_read, dpb_write, total;
} ddr = {0};
struct {
fp_t dpb_read, line_buffer, total;
} llc = {0};
/* Encoder Parameters setup */
ten_bpc_packing_factor = FP(1, 67, 1000);
ten_bpc_bpp_factor = FP(1, 1, 4);
rotation = false;
cropping_or_scaling = false;
vertical_tile_width = 960;
ref_y_bw_factor = FP(1, 30, 100);
ref_cb_cr_bw_factor = FP(1, 50, 100);
dpb_write_factor = FP(1, 8, 100);
/* Derived Parameters */
lcu_size = d->lcu_size;
fps = d->fps;
b_frames_enabled = d->b_frames_enabled;
width = max(d->input_width, BASELINE_DIMENSIONS.width);
height = max(d->input_height, BASELINE_DIMENSIONS.height);
bitrate = __lut(width, height, fps)->bitrate;
lcu_per_frame = DIV_ROUND_UP(width, lcu_size) *
DIV_ROUND_UP(height, lcu_size);
dpb_color_format = HAL_COLOR_FORMAT_NV12_UBWC;
original_color_format = d->num_formats >= 1 ?
d->color_formats[0] : HAL_UNUSED_COLOR;
dpb_bpp = d->num_formats >= 1 ? __bpp(d->color_formats[0]) : INT_MAX;
dpb_compression_enabled = __ubwc(dpb_color_format);
original_compression_enabled = __ubwc(original_color_format);
work_mode_1 = d->work_mode == VIDC_WORK_MODE_1;
low_power = d->power_mode == VIDC_POWER_LOW;
bins_to_bit_factor = work_mode_1 ?
FP_INT(0) : FP_INT(4);
if (d->use_sys_cache) {
llc_dual_core_ref_read_buf_enabled = true;
llc_ref_chroma_cache_enabled = true;
}
/*
* Convert Q16 number into Integer and Fractional part upto 2 places.
* Ex : 105752 / 65536 = 1.61; 1.61 in Q16 = 105752;
* Integer part = 105752 / 65536 = 1;
* Reminder = 105752 - 1 * 65536 = 40216;
* Fractional part = 40216 * 100 / 65536 = 61;
* Now converto to FP(1, 61, 100) for below code.
*/
integer_part = d->compression_ratio >> 16;
frac_part =
((d->compression_ratio - (integer_part * 65536)) * 100) >> 16;
dpb_compression_factor = FP(integer_part, frac_part, 100);
integer_part = d->input_cr >> 16;
frac_part =
((d->input_cr - (integer_part * 65536)) * 100) >> 16;
input_compression_factor = FP(integer_part, frac_part, 100);
original_compression_factor =
original_compression_enabled ? d->use_dpb_read ?
dpb_compression_factor : input_compression_factor :
FP_ONE;
ddr.vsp_read = fp_mult(fp_div(FP_INT(bitrate), FP_INT(8)),
bins_to_bit_factor);
ddr.vsp_write = ddr.vsp_read + fp_div(FP_INT(bitrate), FP_INT(8));
colocated_bytes_per_lcu = lcu_size == 16 ? 16 :
lcu_size == 32 ? 64 : 256;
ddr.collocated_read = FP_INT(lcu_per_frame *
colocated_bytes_per_lcu * fps / bps(1));
ddr.collocated_write = ddr.collocated_read;
ddr.line_buffer_read = FP_INT(16 * lcu_per_frame * fps / bps(1));
ddr.line_buffer_write = ddr.line_buffer_read;
llc.line_buffer = ddr.line_buffer_read + ddr.line_buffer_write;
if (llc_top_line_buf_enabled)
ddr.line_buffer_read = ddr.line_buffer_write = FP_INT(0);
llc.line_buffer -= (ddr.line_buffer_read + ddr.line_buffer_write);
bw_for_1x_8bpc = fp_div(FP_INT((int)(width * height)), FP_INT(32 * 8));
bw_for_1x_8bpc = fp_mult(bw_for_1x_8bpc,
fp_div(FP_INT(((int)(256 * fps))), FP_INT(1000 * 1000)));
dpb_bw_for_1x = dpb_bpp == 8 ? bw_for_1x_8bpc :
fp_mult(bw_for_1x_8bpc, fp_mult(ten_bpc_packing_factor,
ten_bpc_bpp_factor));
ddr.original_read = fp_div(fp_mult(FP(1, 50, 100), dpb_bw_for_1x),
input_compression_factor);
ddr.original_write = FP_ZERO;
ref_y_bw_factor =
width == vertical_tile_width ? FP_INT(1) : ref_y_bw_factor;
ref_y_read = fp_mult(ref_y_bw_factor, dpb_bw_for_1x);
ref_y_read = fp_div(ref_y_read, dpb_compression_factor);
ref_y_read =
b_frames_enabled ? fp_mult(ref_y_read, FP_INT(2)) : ref_y_read;
llc_ref_y_read = ref_y_read;
if (llc_dual_core_ref_read_buf_enabled)
ref_y_read = fp_div(ref_y_read, FP_INT(2));
llc_ref_y_read -= ref_y_read;
ref_cb_cr_read = fp_mult(ref_cb_cr_bw_factor, dpb_bw_for_1x);
ref_cb_cr_read = fp_div(ref_cb_cr_read, dpb_compression_factor);
ref_cb_cr_read =
b_frames_enabled ? fp_mult(ref_cb_cr_read, FP_INT(2)) :
ref_cb_cr_read;
llc_ref_cb_cr_read = ref_cb_cr_read;
if (llc_ref_chroma_cache_enabled)
ref_cb_cr_read = fp_div(ref_cb_cr_read, ref_cb_cr_bw_factor);
if (llc_dual_core_ref_read_buf_enabled)
ref_cb_cr_read = fp_div(ref_cb_cr_read, FP_INT(2));
llc_ref_cb_cr_read -= ref_cb_cr_read;
ddr.dpb_write = fp_mult(dpb_write_factor, dpb_bw_for_1x);
ddr.dpb_write = fp_mult(ddr.dpb_write, FP(1, 50, 100));
ddr.dpb_write = fp_div(ddr.dpb_write, input_compression_factor);
ref_overlap_bw_factor =
width <= vertical_tile_width ? FP_INT(0) : FP_INT(1);
ref_overlap_bw = fp_mult(ddr.dpb_write, ref_overlap_bw_factor);
ref_overlap_bw = fp_div(ref_overlap_bw, dpb_write_factor);
ref_overlap_bw = fp_mult(ref_overlap_bw,
(dpb_write_factor - FP_INT(1)));
ddr.dpb_read = ref_y_read + ref_cb_cr_read + ref_overlap_bw;
llc.dpb_read = llc_ref_y_read + llc_ref_cb_cr_read;
ddr.total = ddr.vsp_read + ddr.vsp_write +
ddr.collocated_read + ddr.collocated_write +
ddr.line_buffer_read + ddr.line_buffer_write +
ddr.original_read + ddr.original_write +
ddr.dpb_read + ddr.dpb_write;
llc.total = llc.dpb_read + llc.line_buffer;
qsmmu_bw_overhead_factor = FP(1, 3, 100);
ddr.total = fp_mult(ddr.total, qsmmu_bw_overhead_factor);
if (msm_vidc_dyn_gov_debug) {
struct dump dump[] = {
{"ENCODER PARAMETERS", "", DUMP_HEADER_MAGIC},
{"width", "%d", width},
{"height", "%d", height},
{"DPB format", "%#x", dpb_color_format},
{"original frame format", "%#x", original_color_format},
{"fps", "%d", fps},
{"DPB compression enable", "%d", dpb_compression_enabled},
{"original compression enable", "%d",
original_compression_enabled},
{"low power mode", "%d", low_power},
{"Work Mode", "%d", work_mode_1},
{"DPB compression factor", DUMP_FP_FMT,
dpb_compression_factor},
{"original compression factor", DUMP_FP_FMT,
original_compression_factor},
{"rotation", "%d", rotation},
{"cropping or scaling", "%d", cropping_or_scaling},
{"DERIVED PARAMETERS", "", DUMP_HEADER_MAGIC},
{"LCU size", "%d", lcu_size},
{"bitrate (Mbit/sec)", "%lu", bitrate},
{"bins to bit factor", DUMP_FP_FMT, bins_to_bit_factor},
{"qsmmu_bw_overhead_factor",
DUMP_FP_FMT, qsmmu_bw_overhead_factor},
{"INTERMEDIATE B/W DDR", "", DUMP_HEADER_MAGIC},
{"ref_y_read", DUMP_FP_FMT, ref_y_read},
{"ref_cb_cr_read", DUMP_FP_FMT, ref_cb_cr_read},
{"ref_overlap_bw", DUMP_FP_FMT, ref_overlap_bw},
{"VSP read", DUMP_FP_FMT, ddr.vsp_read},
{"VSP write", DUMP_FP_FMT, ddr.vsp_write},
{"collocated read", DUMP_FP_FMT, ddr.collocated_read},
{"collocated write", DUMP_FP_FMT, ddr.collocated_write},
{"line buffer read", DUMP_FP_FMT, ddr.line_buffer_read},
{"line buffer write", DUMP_FP_FMT, ddr.line_buffer_write},
{"original read", DUMP_FP_FMT, ddr.original_read},
{"original write", DUMP_FP_FMT, ddr.original_write},
{"DPB read", DUMP_FP_FMT, ddr.dpb_read},
{"DPB write", DUMP_FP_FMT, ddr.dpb_write},
{"LLC DPB read", DUMP_FP_FMT, llc.dpb_read},
{"LLC Line buffer", DUMP_FP_FMT, llc.line_buffer},
};
__dump(dump, ARRAY_SIZE(dump));
}
switch (gm) {
case GOVERNOR_DDR:
ret = kbps(fp_round(ddr.total));
break;
case GOVERNOR_LLCC:
ret = kbps(fp_round(llc.total));
break;
default:
dprintk(VIDC_ERR, "%s - Unknown governor\n", __func__);
}
return ret;
}
static unsigned long __calculate(struct vidc_bus_vote_data *d,
enum governor_mode gm)
{
unsigned long (*calc[])(struct vidc_bus_vote_data *,
enum governor_mode) = {
[HAL_VIDEO_DOMAIN_VPE] = __calculate_vpe,
[HAL_VIDEO_DOMAIN_ENCODER] = __calculate_encoder,
[HAL_VIDEO_DOMAIN_DECODER] = __calculate_decoder,
};
if (d->domain >= ARRAY_SIZE(calc)) {
dprintk(VIDC_ERR, "%s: invalid domain %d\n",
__func__, d->domain);
return 0;
}
return calc[d->domain](d, gm);
}
static int __get_target_freq(struct devfreq *dev, unsigned long *freq)
{
unsigned long ab_kbps = 0, c = 0;
struct devfreq_dev_status stats = {0};
struct msm_vidc_gov_data *vidc_data = NULL;
struct governor *gov = NULL;
if (!dev || !freq)
return -EINVAL;
gov = container_of(dev->governor,
struct governor, devfreq_gov);
dev->profile->get_dev_status(dev->dev.parent, &stats);
vidc_data = (struct msm_vidc_gov_data *)stats.private_data;
if (!vidc_data || !vidc_data->data_count)
goto exit;
for (c = 0; c < vidc_data->data_count; ++c) {
if (vidc_data->data->power_mode == VIDC_POWER_TURBO) {
ab_kbps = INT_MAX;
goto exit;
}
}
for (c = 0; c < vidc_data->data_count; ++c)
ab_kbps += __calculate(&vidc_data->data[c], gov->mode);
exit:
*freq = clamp(ab_kbps, dev->min_freq, dev->max_freq ?
dev->max_freq : UINT_MAX);
trace_msm_vidc_perf_bus_vote(gov->devfreq_gov.name, *freq);
return 0;
}
static int __event_handler(struct devfreq *devfreq, unsigned int event,
void *data)
{
int rc = 0;
if (!devfreq)
return -EINVAL;
switch (event) {
case DEVFREQ_GOV_START:
case DEVFREQ_GOV_RESUME:
case DEVFREQ_GOV_SUSPEND:
mutex_lock(&devfreq->lock);
rc = update_devfreq(devfreq);
mutex_unlock(&devfreq->lock);
break;
}
return rc;
}
static struct governor governors[] = {
{
.mode = GOVERNOR_DDR,
.devfreq_gov = {
.name = "vidc-ar50-ddr",
.get_target_freq = __get_target_freq,
.event_handler = __event_handler,
},
},
{
.mode = GOVERNOR_LLCC,
.devfreq_gov = {
.name = "vidc-ar50-llcc",
.get_target_freq = __get_target_freq,
.event_handler = __event_handler,
},
},
};
static int __init msm_vidc_ar50_bw_gov_init(void)
{
int c = 0, rc = 0;
for (c = 0; c < ARRAY_SIZE(governors); ++c) {
dprintk(VIDC_DBG, "Adding governor %s\n",
governors[c].devfreq_gov.name);
rc = devfreq_add_governor(&governors[c].devfreq_gov);
if (rc) {
dprintk(VIDC_ERR, "Error adding governor %s: %d\n",
governors[c].devfreq_gov.name, rc);
break;
}
}
return rc;
}
module_init(msm_vidc_ar50_bw_gov_init);
static void __exit msm_vidc_ar50_bw_gov_exit(void)
{
int c = 0;
for (c = 0; c < ARRAY_SIZE(governors); ++c) {
dprintk(VIDC_DBG, "Removing governor %s\n",
governors[c].devfreq_gov.name);
devfreq_remove_governor(&governors[c].devfreq_gov);
}
}
module_exit(msm_vidc_ar50_bw_gov_exit);
MODULE_LICENSE("GPL v2");

1645
drivers/media/platform/msm/vidc/msm_vidc_clocks.c Normal file
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drivers/media/platform/msm/vidc/msm_vidc_clocks.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_VIDC_CLOCKS_H_
#define _MSM_VIDC_CLOCKS_H_
#include "msm_vidc_internal.h"
/* extra o/p buffers in case of encoder dcvs */
#define DCVS_ENC_EXTRA_INPUT_BUFFERS 4
/* extra o/p buffers in case of decoder dcvs */
#define DCVS_DEC_EXTRA_OUTPUT_BUFFERS 4
void msm_clock_data_reset(struct msm_vidc_inst *inst);
int msm_vidc_validate_operating_rate(struct msm_vidc_inst *inst,
u32 operating_rate);
int msm_vidc_get_extra_buff_count(struct msm_vidc_inst *inst,
enum hal_buffer buffer_type);
int msm_vidc_set_clocks(struct msm_vidc_core *core);
int msm_comm_vote_bus(struct msm_vidc_core *core);
int msm_dcvs_try_enable(struct msm_vidc_inst *inst);
int msm_vidc_get_mbs_per_frame(struct msm_vidc_inst *inst);
int msm_comm_scale_clocks_and_bus(struct msm_vidc_inst *inst);
int msm_comm_init_clocks_and_bus_data(struct msm_vidc_inst *inst);
void msm_comm_free_freq_table(struct msm_vidc_inst *inst);
int msm_vidc_decide_work_route(struct msm_vidc_inst *inst);
int msm_vidc_decide_work_mode(struct msm_vidc_inst *inst);
int msm_vidc_decide_core_and_power_mode(struct msm_vidc_inst *inst);
void msm_print_core_status(struct msm_vidc_core *core, u32 core_id);
void msm_vidc_clear_freq_entry(struct msm_vidc_inst *inst,
u32 device_addr);
void msm_comm_free_input_cr_table(struct msm_vidc_inst *inst);
void msm_comm_update_input_cr(struct msm_vidc_inst *inst, u32 index,
u32 cr);
void update_recon_stats(struct msm_vidc_inst *inst,
struct recon_stats_type *recon_stats);
void msm_vidc_init_core_clk_ops(struct msm_vidc_core *core);
#endif

6753
drivers/media/platform/msm/vidc/msm_vidc_common.c Normal file
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drivers/media/platform/msm/vidc/msm_vidc_common.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_VIDC_COMMON_H_
#define _MSM_VIDC_COMMON_H_
#include "msm_vidc_internal.h"
#include "msm_vidc_debug.h"
#define MAX_DEC_BATCH_SIZE 6
#define MAX_DEC_BATCH_WIDTH 1920
#define MAX_DEC_BATCH_HEIGHT 1088
#define SKIP_BATCH_WINDOW 100
#define MIN_FRAME_QUALITY 0
#define MAX_FRAME_QUALITY 100
#define DEFAULT_FRAME_QUALITY 80
#define FRAME_QUALITY_STEP 1
#define HEIC_GRID_DIMENSION 512
#define CBR_MB_LIMIT (((1280+15)/16)*((720+15)/16)*30)
#define CBR_VFR_MB_LIMIT (((640+15)/16)*((480+15)/16)*30)
struct vb2_buf_entry {
struct list_head list;
struct vb2_buffer *vb;
};
struct getprop_buf {
struct list_head list;
void *data;
};
enum load_calc_quirks {
LOAD_CALC_NO_QUIRKS = 0,
LOAD_CALC_IGNORE_TURBO_LOAD = 1 << 0,
LOAD_CALC_IGNORE_THUMBNAIL_LOAD = 1 << 1,
LOAD_CALC_IGNORE_NON_REALTIME_LOAD = 1 << 2,
};
static inline bool is_turbo_session(struct msm_vidc_inst *inst)
{
return !!(inst->flags & VIDC_TURBO);
}
static inline bool is_thumbnail_session(struct msm_vidc_inst *inst)
{
return !!(inst->flags & VIDC_THUMBNAIL);
}
static inline bool is_low_power_session(struct msm_vidc_inst *inst)
{
return !!(inst->flags & VIDC_LOW_POWER);
}
static struct v4l2_ctrl *get_ctrl_from_cluster(int id,
struct v4l2_ctrl **cluster, int ncontrols)
{
int c;
for (c = 0; c < ncontrols; ++c)
if (cluster[c]->id == id)
return cluster[c];
return NULL;
}
static inline struct v4l2_ctrl *try_get_ctrl(int __ctrl_id,
struct v4l2_ctrl *ctrl)
{
struct v4l2_ctrl *__temp;
__temp = get_ctrl_from_cluster(
__ctrl_id,
ctrl->cluster, ctrl->ncontrols);
if (!__temp) {
dprintk(VIDC_ERR, "Can't find %s (%x) in cluster\n",
__ctrl_id, __ctrl_id);
/* Clusters are hardcoded, if we can't find */
/* something, then things are massively screwed up */
MSM_VIDC_ERROR(1);
}
return __temp;
}
static inline bool is_realtime_session(struct msm_vidc_inst *inst)
{
return !!(inst->flags & VIDC_REALTIME);
}
static inline bool is_decode_session(struct msm_vidc_inst *inst)
{
return inst->session_type == MSM_VIDC_DECODER;
}
static inline bool is_encode_session(struct msm_vidc_inst *inst)
{
return inst->session_type == MSM_VIDC_ENCODER;
}
static inline bool is_primary_output_mode(struct msm_vidc_inst *inst)
{
return inst->stream_output_mode == HAL_VIDEO_DECODER_PRIMARY;
}
static inline bool is_secondary_output_mode(struct msm_vidc_inst *inst)
{
return inst->stream_output_mode == HAL_VIDEO_DECODER_SECONDARY;
}
static inline int msm_comm_g_ctrl(struct msm_vidc_inst *inst,
struct v4l2_control *ctrl)
{
return v4l2_g_ctrl(&inst->ctrl_handler, ctrl);
}
static inline int msm_comm_s_ctrl(struct msm_vidc_inst *inst,
struct v4l2_control *ctrl)
{
return v4l2_s_ctrl(NULL, &inst->ctrl_handler, ctrl);
}
bool is_batching_allowed(struct msm_vidc_inst *inst);
enum hal_buffer get_hal_buffer_type(unsigned int type,
unsigned int plane_num);
void put_inst(struct msm_vidc_inst *inst);
struct msm_vidc_inst *get_inst(struct msm_vidc_core *core,
void *session_id);
void change_inst_state(struct msm_vidc_inst *inst, enum instance_state state);
struct msm_vidc_core *get_vidc_core(int core_id);
const struct msm_vidc_format *msm_comm_get_pixel_fmt_index(
const struct msm_vidc_format fmt[], int size, int index, int fmt_type);
struct msm_vidc_format *msm_comm_get_pixel_fmt_fourcc(
struct msm_vidc_format fmt[], int size, int fourcc, int fmt_type);
struct msm_vidc_format_constraint *msm_comm_get_pixel_fmt_constraints(
struct msm_vidc_format_constraint fmt[], int size, int fourcc);
int msm_comm_set_color_format_constraints(struct msm_vidc_inst *inst,
enum hal_buffer buffer_type,
struct msm_vidc_format_constraint *pix_constraint);
struct buf_queue *msm_comm_get_vb2q(
struct msm_vidc_inst *inst, enum v4l2_buf_type type);
int msm_comm_try_state(struct msm_vidc_inst *inst, int state);
int msm_comm_try_get_bufreqs(struct msm_vidc_inst *inst);
int msm_comm_try_set_prop(struct msm_vidc_inst *inst,
enum hal_property ptype, void *pdata);
int msm_comm_try_get_prop(struct msm_vidc_inst *inst,
enum hal_property ptype, union hal_get_property *hprop);
int msm_comm_set_recon_buffers(struct msm_vidc_inst *inst);
int msm_comm_set_scratch_buffers(struct msm_vidc_inst *inst);
int msm_comm_set_persist_buffers(struct msm_vidc_inst *inst);
int msm_comm_set_buffer_count(struct msm_vidc_inst *inst,
int host_count, int act_count, enum hal_buffer type);
int msm_comm_set_output_buffers(struct msm_vidc_inst *inst);
int msm_comm_queue_output_buffers(struct msm_vidc_inst *inst);
int msm_comm_qbuf(struct msm_vidc_inst *inst, struct msm_vidc_buffer *mbuf);
int msm_comm_qbufs(struct msm_vidc_inst *inst);
void msm_comm_flush_dynamic_buffers(struct msm_vidc_inst *inst);
int msm_comm_flush(struct msm_vidc_inst *inst, u32 flags);
int msm_comm_release_scratch_buffers(struct msm_vidc_inst *inst,
bool check_for_reuse);
int msm_comm_release_persist_buffers(struct msm_vidc_inst *inst);
int msm_comm_release_recon_buffers(struct msm_vidc_inst *inst);
void msm_comm_release_eos_buffers(struct msm_vidc_inst *inst);
int msm_comm_release_output_buffers(struct msm_vidc_inst *inst,
bool force_release);
void msm_comm_validate_output_buffers(struct msm_vidc_inst *inst);
int msm_comm_force_cleanup(struct msm_vidc_inst *inst);
int msm_comm_suspend(int core_id);
int msm_comm_reset_bufreqs(struct msm_vidc_inst *inst,
enum hal_buffer buf_type);
int msm_comm_copy_bufreqs(struct msm_vidc_inst *inst,
enum hal_buffer src_type, enum hal_buffer dst_type);
struct hal_buffer_requirements *get_buff_req_buffer(
struct msm_vidc_inst *inst, u32 buffer_type);
#define IS_PRIV_CTRL(idx) (\
(V4L2_CTRL_ID2WHICH(idx) == V4L2_CTRL_CLASS_MPEG) && \
V4L2_CTRL_DRIVER_PRIV(idx))
void msm_comm_session_clean(struct msm_vidc_inst *inst);
int msm_comm_kill_session(struct msm_vidc_inst *inst);
void msm_comm_generate_session_error(struct msm_vidc_inst *inst);
void msm_comm_generate_sys_error(struct msm_vidc_inst *inst);
enum multi_stream msm_comm_get_stream_output_mode(struct msm_vidc_inst *inst);
int msm_comm_set_stream_output_mode(struct msm_vidc_inst *inst,
enum multi_stream mode);
enum hal_buffer msm_comm_get_hal_output_buffer(struct msm_vidc_inst *inst);
int msm_comm_smem_alloc(struct msm_vidc_inst *inst, size_t size, u32 align,
u32 flags, enum hal_buffer buffer_type, int map_kernel,
struct msm_smem *smem);
void msm_comm_smem_free(struct msm_vidc_inst *inst, struct msm_smem *smem);
int msm_comm_smem_cache_operations(struct msm_vidc_inst *inst,
struct msm_smem *mem, enum smem_cache_ops cache_ops);
enum hal_video_codec get_hal_codec(int fourcc);
enum hal_domain get_hal_domain(int session_type);
int msm_comm_check_core_init(struct msm_vidc_core *core);
int msm_comm_get_inst_load(struct msm_vidc_inst *inst,
enum load_calc_quirks quirks);
int msm_comm_get_inst_load_per_core(struct msm_vidc_inst *inst,
enum load_calc_quirks quirks);
int msm_comm_get_load(struct msm_vidc_core *core,
enum session_type type, enum load_calc_quirks quirks);
int msm_comm_set_color_format(struct msm_vidc_inst *inst,
enum hal_buffer buffer_type, int fourcc);
int msm_comm_g_ctrl(struct msm_vidc_inst *inst, struct v4l2_control *ctrl);
int msm_comm_s_ctrl(struct msm_vidc_inst *inst, struct v4l2_control *ctrl);
int msm_comm_g_ctrl_for_id(struct msm_vidc_inst *inst, int id);
int msm_comm_ctrl_init(struct msm_vidc_inst *inst,
struct msm_vidc_ctrl *drv_ctrls, u32 num_ctrls,
const struct v4l2_ctrl_ops *ctrl_ops);
int msm_comm_ctrl_deinit(struct msm_vidc_inst *inst);
void msm_comm_cleanup_internal_buffers(struct msm_vidc_inst *inst);
int msm_vidc_comm_s_parm(struct msm_vidc_inst *inst, struct v4l2_streamparm *a);
bool msm_comm_turbo_session(struct msm_vidc_inst *inst);
void msm_comm_print_inst_info(struct msm_vidc_inst *inst);
int msm_comm_v4l2_to_hal(int id, int value);
int msm_comm_hal_to_v4l2(int id, int value);
int msm_comm_get_v4l2_profile(int fourcc, int profile);
int msm_comm_get_v4l2_level(int fourcc, int level);
int msm_comm_session_continue(void *instance);
int msm_vidc_send_pending_eos_buffers(struct msm_vidc_inst *inst);
enum hal_uncompressed_format msm_comm_get_hal_uncompressed(int fourcc);
u32 get_frame_size_nv12(int plane, u32 height, u32 width);
u32 get_frame_size_nv12_512(int plane, u32 height, u32 width);
u32 get_frame_size_nv12_ubwc(int plane, u32 height, u32 width);
u32 get_frame_size_rgba(int plane, u32 height, u32 width);
u32 get_frame_size_nv21(int plane, u32 height, u32 width);
u32 get_frame_size_tp10_ubwc(int plane, u32 height, u32 width);
u32 get_frame_size_p010(int plane, u32 height, u32 width);
struct vb2_buffer *msm_comm_get_vb_using_vidc_buffer(
struct msm_vidc_inst *inst, struct msm_vidc_buffer *mbuf);
struct msm_vidc_buffer *msm_comm_get_buffer_using_device_planes(
struct msm_vidc_inst *inst, u32 type, u32 *planes);
struct msm_vidc_buffer *msm_comm_get_vidc_buffer(struct msm_vidc_inst *inst,
struct vb2_buffer *vb2);
void msm_comm_put_vidc_buffer(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
void handle_release_buffer_reference(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
int msm_comm_vb2_buffer_done(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
int msm_comm_flush_vidc_buffer(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
int msm_comm_unmap_vidc_buffer(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
bool msm_comm_compare_dma_plane(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf, unsigned long *dma_planes, u32 i);
bool msm_comm_compare_dma_planes(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf, unsigned long *dma_planes);
bool msm_comm_compare_vb2_plane(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf, struct vb2_buffer *vb2, u32 i);
bool msm_comm_compare_vb2_planes(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf, struct vb2_buffer *vb2);
bool msm_comm_compare_device_plane(struct msm_vidc_buffer *mbuf,
u32 type, u32 *planes, u32 i);
bool msm_comm_compare_device_planes(struct msm_vidc_buffer *mbuf,
u32 type, u32 *planes);
int msm_comm_qbuf_cache_operations(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
int msm_comm_dqbuf_cache_operations(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
void print_vidc_buffer(u32 tag, const char *str, struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
void print_vb2_buffer(u32 tag, const char *str, struct msm_vidc_inst *inst,
struct vb2_buffer *vb2);
void print_v4l2_buffer(u32 tag, const char *str, struct msm_vidc_inst *inst,
struct v4l2_buffer *v4l2);
void kref_put_mbuf(struct msm_vidc_buffer *mbuf);
bool kref_get_mbuf(struct msm_vidc_inst *inst, struct msm_vidc_buffer *mbuf);
void msm_comm_store_mark_data(struct msm_vidc_list *data_list,
u32 index, u32 mark_data, u32 mark_target);
void msm_comm_fetch_mark_data(struct msm_vidc_list *data_list,
u32 index, u32 *mark_data, u32 *mark_target);
int msm_comm_release_mark_data(struct msm_vidc_inst *inst);
int msm_comm_qbuf_decode_batch(struct msm_vidc_inst *inst,
struct msm_vidc_buffer *mbuf);
int msm_comm_num_queued_bufs(struct msm_vidc_inst *inst, u32 type);
int msm_comm_set_extradata(struct msm_vidc_inst *inst, uint32_t extradata_id,
uint32_t value);
#endif

520
drivers/media/platform/msm/vidc/msm_vidc_debug.c Normal file
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@ -0,0 +1,520 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#define CREATE_TRACE_POINTS
#define MAX_SSR_STRING_LEN 10
#include "msm_vidc_debug.h"
#include "vidc_hfi_api.h"
int msm_vidc_debug = VIDC_ERR | VIDC_WARN;
EXPORT_SYMBOL(msm_vidc_debug);
int msm_vidc_debug_out = VIDC_OUT_PRINTK;
EXPORT_SYMBOL(msm_vidc_debug_out);
int msm_vidc_fw_debug = 0x18;
int msm_vidc_fw_debug_mode = 1;
int msm_vidc_fw_low_power_mode = 1;
bool msm_vidc_fw_coverage = !true;
bool msm_vidc_thermal_mitigation_disabled = !true;
int msm_vidc_clock_voting = !1;
bool msm_vidc_syscache_disable = !true;
bool msm_vidc_dyn_gov_debug = !true;
#define MAX_DBG_BUF_SIZE 4096
#define DYNAMIC_BUF_OWNER(__binfo) ({ \
atomic_read(&__binfo->ref_count) >= 2 ? "video driver" : "firmware";\
})
struct core_inst_pair {
struct msm_vidc_core *core;
struct msm_vidc_inst *inst;
};
static u32 write_str(char *buffer,
size_t size, const char *fmt, ...)
{
va_list args;
u32 len;
va_start(args, fmt);
len = vscnprintf(buffer, size, fmt, args);
va_end(args);
return len;
}
static ssize_t core_info_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct msm_vidc_core *core = file->private_data;
struct hfi_device *hdev;
struct hal_fw_info fw_info = { {0} };
char *dbuf, *cur, *end;
int i = 0, rc = 0;
ssize_t len = 0;
if (!core || !core->device) {
dprintk(VIDC_ERR, "Invalid params, core: %pK\n", core);
return 0;
}
dbuf = kzalloc(MAX_DBG_BUF_SIZE, GFP_KERNEL);
if (!dbuf) {
dprintk(VIDC_ERR, "%s: Allocation failed!\n", __func__);
return -ENOMEM;
}
cur = dbuf;
end = cur + MAX_DBG_BUF_SIZE;
hdev = core->device;
cur += write_str(cur, end - cur, "===============================\n");
cur += write_str(cur, end - cur, "CORE %d: %pK\n", core->id, core);
cur += write_str(cur, end - cur, "===============================\n");
cur += write_str(cur, end - cur, "Core state: %d\n", core->state);
rc = call_hfi_op(hdev, get_fw_info, hdev->hfi_device_data, &fw_info);
if (rc) {
dprintk(VIDC_WARN, "Failed to read FW info\n");
goto err_fw_info;
}
cur += write_str(cur, end - cur,
"FW version : %s\n", &fw_info.version);
cur += write_str(cur, end - cur,
"base addr: 0x%x\n", fw_info.base_addr);
cur += write_str(cur, end - cur,
"register_base: 0x%x\n", fw_info.register_base);
cur += write_str(cur, end - cur,
"register_size: %u\n", fw_info.register_size);
cur += write_str(cur, end - cur, "irq: %u\n", fw_info.irq);
err_fw_info:
for (i = SYS_MSG_START; i < SYS_MSG_END; i++) {
cur += write_str(cur, end - cur, "completions[%d]: %s\n", i,
completion_done(&core->completions[SYS_MSG_INDEX(i)]) ?
"pending" : "done");
}
len = simple_read_from_buffer(buf, count, ppos,
dbuf, cur - dbuf);
kfree(dbuf);
return len;
}
static const struct file_operations core_info_fops = {
.open = simple_open,
.read = core_info_read,
};
static ssize_t trigger_ssr_write(struct file *filp, const char __user *buf,
size_t count, loff_t *ppos)
{
unsigned long ssr_trigger_val = 0;
int rc = 0;
struct msm_vidc_core *core = filp->private_data;
size_t size = MAX_SSR_STRING_LEN;
char kbuf[MAX_SSR_STRING_LEN + 1] = {0};
if (!buf)
return -EINVAL;
if (!count)
goto exit;
if (count < size)
size = count;
if (copy_from_user(kbuf, buf, size)) {
dprintk(VIDC_WARN, "%s User memory fault\n", __func__);
rc = -EFAULT;
goto exit;
}
rc = kstrtoul(kbuf, 0, &ssr_trigger_val);
if (rc) {
dprintk(VIDC_WARN, "returning error err %d\n", rc);
rc = -EINVAL;
} else {
msm_vidc_trigger_ssr(core, ssr_trigger_val);
rc = count;
}
exit:
return rc;
}
static const struct file_operations ssr_fops = {
.open = simple_open,
.write = trigger_ssr_write,
};
struct dentry *msm_vidc_debugfs_init_drv(void)
{
bool ok = false;
struct dentry *dir = NULL;
dir = debugfs_create_dir("msm_vidc", NULL);
if (IS_ERR_OR_NULL(dir)) {
dir = NULL;
goto failed_create_dir;
}
#define __debugfs_create(__type, __name, __value) ({ \
struct dentry *f = debugfs_create_##__type(__name, 0644, \
dir, __value); \
if (IS_ERR_OR_NULL(f)) { \
dprintk(VIDC_ERR, "Failed creating debugfs file '%pd/%s'\n", \
dir, __name); \
f = NULL; \
} \
f; \
})
ok =
__debugfs_create(x32, "debug_level", &msm_vidc_debug) &&
__debugfs_create(x32, "fw_level", &msm_vidc_fw_debug) &&
__debugfs_create(u32, "fw_debug_mode", &msm_vidc_fw_debug_mode) &&
__debugfs_create(bool, "fw_coverage", &msm_vidc_fw_coverage) &&
__debugfs_create(u32, "fw_low_power_mode",
&msm_vidc_fw_low_power_mode) &&
__debugfs_create(u32, "debug_output", &msm_vidc_debug_out) &&
__debugfs_create(bool, "disable_thermal_mitigation",
&msm_vidc_thermal_mitigation_disabled) &&
__debugfs_create(u32, "core_clock_voting",
&msm_vidc_clock_voting) &&
__debugfs_create(bool, "disable_video_syscache",
&msm_vidc_syscache_disable);
__debugfs_create(bool, "dyn_gov_debug",
&msm_vidc_dyn_gov_debug);
#undef __debugfs_create
if (!ok)
goto failed_create_dir;
return dir;
failed_create_dir:
if (dir)
debugfs_remove_recursive(vidc_driver->debugfs_root);
return NULL;
}
struct dentry *msm_vidc_debugfs_init_core(struct msm_vidc_core *core,
struct dentry *parent)
{
struct dentry *dir = NULL;
char debugfs_name[MAX_DEBUGFS_NAME];
if (!core) {
dprintk(VIDC_ERR, "Invalid params, core: %pK\n", core);
goto failed_create_dir;
}
snprintf(debugfs_name, MAX_DEBUGFS_NAME, "core%d", core->id);
dir = debugfs_create_dir(debugfs_name, parent);
if (!dir) {
dprintk(VIDC_ERR, "Failed to create debugfs for msm_vidc\n");
goto failed_create_dir;
}
if (!debugfs_create_file("info", 0444, dir, core, &core_info_fops)) {
dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
goto failed_create_dir;
}
if (!debugfs_create_file("trigger_ssr", 0200,
dir, core, &ssr_fops)) {
dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
goto failed_create_dir;
}
failed_create_dir:
return dir;
}
static int inst_info_open(struct inode *inode, struct file *file)
{
dprintk(VIDC_INFO, "Open inode ptr: %pK\n", inode->i_private);
file->private_data = inode->i_private;
return 0;
}
static int publish_unreleased_reference(struct msm_vidc_inst *inst,
char **dbuf, char *end)
{
struct msm_vidc_buffer *temp = NULL;
char *cur = *dbuf;
if (!inst) {
dprintk(VIDC_ERR, "%s: invalid param\n", __func__);
return -EINVAL;
}
if (inst->buffer_mode_set[CAPTURE_PORT] == HAL_BUFFER_MODE_DYNAMIC) {
cur += write_str(cur, end - cur, "Pending buffer references\n");
mutex_lock(&inst->registeredbufs.lock);
list_for_each_entry(temp, &inst->registeredbufs.list, list) {
struct vb2_buffer *vb2 = &temp->vvb.vb2_buf;
if (vb2->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
cur += write_str(cur, end - cur,
"\tbuffer: %#x fd[0] = %d size %d refcount = %d\n",
temp->smem[0].device_addr,
vb2->planes[0].m.fd,
vb2->planes[0].length,
temp->smem[0].refcount);
}
}
mutex_unlock(&inst->registeredbufs.lock);
}
*dbuf = cur;
return 0;
}
static void put_inst_helper(struct kref *kref)
{
struct msm_vidc_inst *inst = container_of(kref,
struct msm_vidc_inst, kref);
msm_vidc_destroy(inst);
}
static ssize_t inst_info_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct core_inst_pair *idata = file->private_data;
struct msm_vidc_core *core;
struct msm_vidc_inst *inst, *temp = NULL;
char *dbuf, *cur, *end;
int i, j;
ssize_t len = 0;
if (!idata || !idata->core || !idata->inst) {
dprintk(VIDC_ERR, "%s: Invalid params\n", __func__);
return 0;
}
core = idata->core;
inst = idata->inst;
mutex_lock(&core->lock);
list_for_each_entry(temp, &core->instances, list) {
if (temp == inst)
break;
}
inst = ((temp == inst) && kref_get_unless_zero(&inst->kref)) ?
inst : NULL;
mutex_unlock(&core->lock);
if (!inst) {
dprintk(VIDC_ERR, "%s: Instance has become obsolete", __func__);
return 0;
}
dbuf = kzalloc(MAX_DBG_BUF_SIZE, GFP_KERNEL);
if (!dbuf) {
dprintk(VIDC_ERR, "%s: Allocation failed!\n", __func__);
len = -ENOMEM;
goto failed_alloc;
}
cur = dbuf;
end = cur + MAX_DBG_BUF_SIZE;
cur += write_str(cur, end - cur, "==============================\n");
cur += write_str(cur, end - cur, "INSTANCE: %pK (%s)\n", inst,
inst->session_type == MSM_VIDC_ENCODER ? "Encoder" : "Decoder");
cur += write_str(cur, end - cur, "==============================\n");
cur += write_str(cur, end - cur, "core: %pK\n", inst->core);
cur += write_str(cur, end - cur, "height: %d\n",
inst->prop.height[CAPTURE_PORT]);
cur += write_str(cur, end - cur, "width: %d\n",
inst->prop.width[CAPTURE_PORT]);
cur += write_str(cur, end - cur, "fps: %d\n", inst->prop.fps);
cur += write_str(cur, end - cur, "state: %d\n", inst->state);
cur += write_str(cur, end - cur, "secure: %d\n",
!!(inst->flags & VIDC_SECURE));
cur += write_str(cur, end - cur, "-----------Formats-------------\n");
for (i = 0; i < MAX_PORT_NUM; i++) {
cur += write_str(cur, end - cur, "capability: %s\n",
i == OUTPUT_PORT ? "Output" : "Capture");
cur += write_str(cur, end - cur, "name : %s\n",
inst->fmts[i].name);
cur += write_str(cur, end - cur, "planes : %d\n",
inst->bufq[i].num_planes);
cur += write_str(cur, end - cur,
"type: %s\n", inst->fmts[i].type == OUTPUT_PORT ?
"Output" : "Capture");
switch (inst->buffer_mode_set[i]) {
case HAL_BUFFER_MODE_STATIC:
cur += write_str(cur, end - cur,
"buffer mode : %s\n", "static");
break;
case HAL_BUFFER_MODE_DYNAMIC:
cur += write_str(cur, end - cur,
"buffer mode : %s\n", "dynamic");
break;
default:
cur += write_str(cur, end - cur,
"buffer mode : unsupported\n");
}
cur += write_str(cur, end - cur, "count: %u\n",
inst->bufq[i].vb2_bufq.num_buffers);
for (j = 0; j < inst->bufq[i].num_planes; j++)
cur += write_str(cur, end - cur,
"size for plane %d: %u\n",
j, inst->bufq[i].plane_sizes[j]);
if (i < MAX_PORT_NUM - 1)
cur += write_str(cur, end - cur, "\n");
}
cur += write_str(cur, end - cur, "-------------------------------\n");
for (i = SESSION_MSG_START; i < SESSION_MSG_END; i++) {
cur += write_str(cur, end - cur, "completions[%d]: %s\n", i,
completion_done(&inst->completions[SESSION_MSG_INDEX(i)]) ?
"pending" : "done");
}
cur += write_str(cur, end - cur, "ETB Count: %d\n", inst->count.etb);
cur += write_str(cur, end - cur, "EBD Count: %d\n", inst->count.ebd);
cur += write_str(cur, end - cur, "FTB Count: %d\n", inst->count.ftb);
cur += write_str(cur, end - cur, "FBD Count: %d\n", inst->count.fbd);
publish_unreleased_reference(inst, &cur, end);
len = simple_read_from_buffer(buf, count, ppos,
dbuf, cur - dbuf);
kfree(dbuf);
failed_alloc:
kref_put(&inst->kref, put_inst_helper);
return len;
}
static int inst_info_release(struct inode *inode, struct file *file)
{
dprintk(VIDC_INFO, "Release inode ptr: %pK\n", inode->i_private);
file->private_data = NULL;
return 0;
}
static const struct file_operations inst_info_fops = {
.open = inst_info_open,
.read = inst_info_read,
.release = inst_info_release,
};
struct dentry *msm_vidc_debugfs_init_inst(struct msm_vidc_inst *inst,
struct dentry *parent)
{
struct dentry *dir = NULL, *info = NULL;
char debugfs_name[MAX_DEBUGFS_NAME];
struct core_inst_pair *idata = NULL;
if (!inst) {
dprintk(VIDC_ERR, "Invalid params, inst: %pK\n", inst);
goto exit;
}
snprintf(debugfs_name, MAX_DEBUGFS_NAME, "inst_%p", inst);
idata = kzalloc(sizeof(struct core_inst_pair), GFP_KERNEL);
if (!idata) {
dprintk(VIDC_ERR, "%s: Allocation failed!\n", __func__);
goto exit;
}
idata->core = inst->core;
idata->inst = inst;
dir = debugfs_create_dir(debugfs_name, parent);
if (!dir) {
dprintk(VIDC_ERR, "Failed to create debugfs for msm_vidc\n");
goto failed_create_dir;
}
info = debugfs_create_file("info", 0444, dir,
idata, &inst_info_fops);
if (!info) {
dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
goto failed_create_file;
}
dir->d_inode->i_private = info->d_inode->i_private;
inst->debug.pdata[FRAME_PROCESSING].sampling = true;
return dir;
failed_create_file:
debugfs_remove_recursive(dir);
dir = NULL;
failed_create_dir:
kfree(idata);
exit:
return dir;
}
void msm_vidc_debugfs_deinit_inst(struct msm_vidc_inst *inst)
{
struct dentry *dentry = NULL;
if (!inst || !inst->debugfs_root)
return;
dentry = inst->debugfs_root;
if (dentry->d_inode) {
dprintk(VIDC_INFO, "Destroy %pK\n", dentry->d_inode->i_private);
kfree(dentry->d_inode->i_private);
dentry->d_inode->i_private = NULL;
}
debugfs_remove_recursive(dentry);
inst->debugfs_root = NULL;
}
void msm_vidc_debugfs_update(struct msm_vidc_inst *inst,
enum msm_vidc_debugfs_event e)
{
struct msm_vidc_debug *d = &inst->debug;
char a[64] = "Frame processing";
switch (e) {
case MSM_VIDC_DEBUGFS_EVENT_ETB:
inst->count.etb++;
if (inst->count.ebd && inst->count.ftb > inst->count.fbd) {
d->pdata[FRAME_PROCESSING].name[0] = '\0';
tic(inst, FRAME_PROCESSING, a);
}
break;
case MSM_VIDC_DEBUGFS_EVENT_EBD:
inst->count.ebd++;
if (inst->count.ebd && inst->count.ebd == inst->count.etb) {
toc(inst, FRAME_PROCESSING);
dprintk(VIDC_PROF, "EBD: FW needs input buffers\n");
}
if (inst->count.ftb == inst->count.fbd)
dprintk(VIDC_PROF, "EBD: FW needs output buffers\n");
break;
case MSM_VIDC_DEBUGFS_EVENT_FTB: {
inst->count.ftb++;
if (inst->count.ebd && inst->count.etb > inst->count.ebd) {
d->pdata[FRAME_PROCESSING].name[0] = '\0';
tic(inst, FRAME_PROCESSING, a);
}
}
break;
case MSM_VIDC_DEBUGFS_EVENT_FBD:
inst->count.fbd++;
inst->debug.samples++;
if (inst->count.fbd &&
inst->count.fbd == inst->count.ftb) {
toc(inst, FRAME_PROCESSING);
dprintk(VIDC_PROF, "FBD: FW needs output buffers\n");
}
if (inst->count.etb == inst->count.ebd)
dprintk(VIDC_PROF, "FBD: FW needs input buffers\n");
break;
default:
dprintk(VIDC_ERR, "Invalid state in debugfs: %d\n", e);
break;
}
}

189
drivers/media/platform/msm/vidc/msm_vidc_debug.h Normal file
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@ -0,0 +1,189 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __MSM_VIDC_DEBUG__
#define __MSM_VIDC_DEBUG__
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/types.h>
#include "msm_vidc_internal.h"
#include "trace/events/msm_vidc_events.h"
#ifndef VIDC_DBG_LABEL
#define VIDC_DBG_LABEL "msm_vidc"
#endif
#define VIDC_DBG_TAG VIDC_DBG_LABEL ": %4s: "
/* To enable messages OR these values and
* echo the result to debugfs file.
*
* To enable all messages set debug_level = 0x101F
*/
enum vidc_msg_prio {
VIDC_ERR = 0x0001,
VIDC_WARN = 0x0002,
VIDC_INFO = 0x0004,
VIDC_DBG = 0x0008,
VIDC_PROF = 0x0010,
VIDC_PKT = 0x0020,
VIDC_FW = 0x1000,
};
enum vidc_msg_out {
VIDC_OUT_PRINTK = 0,
};
enum msm_vidc_debugfs_event {
MSM_VIDC_DEBUGFS_EVENT_ETB,
MSM_VIDC_DEBUGFS_EVENT_EBD,
MSM_VIDC_DEBUGFS_EVENT_FTB,
MSM_VIDC_DEBUGFS_EVENT_FBD,
};
extern int msm_vidc_debug;
extern int msm_vidc_debug_out;
extern int msm_vidc_fw_debug;
extern int msm_vidc_fw_debug_mode;
extern int msm_vidc_fw_low_power_mode;
extern bool msm_vidc_fw_coverage;
extern bool msm_vidc_thermal_mitigation_disabled;
extern int msm_vidc_clock_voting;
extern bool msm_vidc_syscache_disable;
extern bool msm_vidc_dyn_gov_debug;
#define dprintk(__level, __fmt, ...) \
do { \
if (msm_vidc_debug & __level) { \
if (msm_vidc_debug_out == VIDC_OUT_PRINTK) { \
pr_info(VIDC_DBG_TAG __fmt, \
get_debug_level_str(__level), \
##__VA_ARGS__); \
} \
} \
} while (0)
#define MSM_VIDC_ERROR(value) \
do { if (value) \
dprintk(VIDC_DBG, "BugOn"); \
BUG_ON(value); \
} while (0)
struct dentry *msm_vidc_debugfs_init_drv(void);
struct dentry *msm_vidc_debugfs_init_core(struct msm_vidc_core *core,
struct dentry *parent);
struct dentry *msm_vidc_debugfs_init_inst(struct msm_vidc_inst *inst,
struct dentry *parent);
void msm_vidc_debugfs_deinit_inst(struct msm_vidc_inst *inst);
void msm_vidc_debugfs_update(struct msm_vidc_inst *inst,
enum msm_vidc_debugfs_event e);
static inline char *get_debug_level_str(int level)
{
switch (level) {
case VIDC_ERR:
return "err";
case VIDC_WARN:
return "warn";
case VIDC_INFO:
return "info";
case VIDC_DBG:
return "dbg";
case VIDC_PROF:
return "prof";
case VIDC_PKT:
return "pkt";
case VIDC_FW:
return "fw";
default:
return "???";
}
}
static inline void tic(struct msm_vidc_inst *i, enum profiling_points p,
char *b)
{
struct timeval __ddl_tv;
if (!i->debug.pdata[p].name[0])
memcpy(i->debug.pdata[p].name, b, 64);
if ((msm_vidc_debug & VIDC_PROF) &&
i->debug.pdata[p].sampling) {
do_gettimeofday(&__ddl_tv);
i->debug.pdata[p].start =
(__ddl_tv.tv_sec * 1000) + (__ddl_tv.tv_usec / 1000);
i->debug.pdata[p].sampling = false;
}
}
static inline void toc(struct msm_vidc_inst *i, enum profiling_points p)
{
struct timeval __ddl_tv;
if ((msm_vidc_debug & VIDC_PROF) &&
!i->debug.pdata[p].sampling) {
do_gettimeofday(&__ddl_tv);
i->debug.pdata[p].stop = (__ddl_tv.tv_sec * 1000)
+ (__ddl_tv.tv_usec / 1000);
i->debug.pdata[p].cumulative += i->debug.pdata[p].stop -
i->debug.pdata[p].start;
i->debug.pdata[p].sampling = true;
}
}
static inline void show_stats(struct msm_vidc_inst *i)
{
int x;
for (x = 0; x < MAX_PROFILING_POINTS; x++) {
if (i->debug.pdata[x].name[0] &&
(msm_vidc_debug & VIDC_PROF)) {
if (i->debug.samples) {
dprintk(VIDC_PROF, "%s averaged %d ms/sample\n",
i->debug.pdata[x].name,
i->debug.pdata[x].cumulative /
i->debug.samples);
}
dprintk(VIDC_PROF, "%s Samples: %d\n",
i->debug.pdata[x].name,
i->debug.samples);
}
}
}
static inline void msm_vidc_res_handle_fatal_hw_error(
struct msm_vidc_platform_resources *resources,
bool enable_fatal)
{
enable_fatal &= resources->debug_timeout;
MSM_VIDC_ERROR(enable_fatal);
}
static inline void msm_vidc_handle_hw_error(struct msm_vidc_core *core)
{
bool enable_fatal = true;
/*
* In current implementation user-initiated SSR triggers
* a fatal error from hardware. However, there is no way
* to know if fatal error is due to SSR or not. Handle
* user SSR as non-fatal.
*/
if (core->trigger_ssr) {
core->trigger_ssr = false;
enable_fatal = false;
}
/* Video driver can decide FATAL handling of HW errors
* based on multiple factors. This condition check will
* be enhanced later.
*/
msm_vidc_res_handle_fatal_hw_error(&core->resources, enable_fatal);
}
#endif

1016
drivers/media/platform/msm/vidc/msm_vidc_dyn_gov.c Normal file
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File diff suppressed because it is too large Load diff

555
drivers/media/platform/msm/vidc/msm_vidc_internal.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_VIDC_INTERNAL_H_
#define _MSM_VIDC_INTERNAL_H_
#include <linux/atomic.h>
#include <linux/list.h>
#include <linux/time.h>
#include <linux/types.h>
#include <linux/completion.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/msm-bus.h>
#include <linux/msm-bus-board.h>
#include <linux/kref.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <media/v4l2-ctrls.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-v4l2.h>
#include "msm_vidc.h"
#include <media/msm_media_info.h>
#include "vidc_hfi_api.h"
#define MSM_VIDC_DRV_NAME "msm_vidc_driver"
/* kernel/msm-4.19 */
#define MSM_VIDC_VERSION ((0 << 16) + (4 << 8) + 19)
#define MAX_DEBUGFS_NAME 50
#define DEFAULT_TIMEOUT 3
#define DEFAULT_HEIGHT 1088
#define DEFAULT_WIDTH 1920
#define MIN_SUPPORTED_WIDTH 32
#define MIN_SUPPORTED_HEIGHT 32
#define DEFAULT_FPS 15
#define MIN_NUM_OUTPUT_BUFFERS 1
#define MIN_NUM_OUTPUT_BUFFERS_VP9 6
#define MIN_NUM_CAPTURE_BUFFERS 1
#define MAX_NUM_OUTPUT_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
#define MAX_NUM_CAPTURE_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
#define MAX_SUPPORTED_INSTANCES 16
/* Maintains the number of FTB's between each FBD over a window */
#define DCVS_FTB_WINDOW 16
#define V4L2_EVENT_VIDC_BASE 10
#define SYS_MSG_START HAL_SYS_INIT_DONE
#define SYS_MSG_END HAL_SYS_ERROR
#define SESSION_MSG_START HAL_SESSION_EVENT_CHANGE
#define SESSION_MSG_END HAL_SESSION_ERROR
#define SYS_MSG_INDEX(__msg) (__msg - SYS_MSG_START)
#define SESSION_MSG_INDEX(__msg) (__msg - SESSION_MSG_START)
#define MAX_NAME_LENGTH 64
#define EXTRADATA_IDX(__num_planes) ((__num_planes) ? (__num_planes) - 1 : 0)
#define NUM_MBS_PER_SEC(__height, __width, __fps) \
(NUM_MBS_PER_FRAME(__height, __width) * __fps)
#define NUM_MBS_PER_FRAME(__height, __width) \
((ALIGN(__height, 16) / 16) * (ALIGN(__width, 16) / 16))
#define call_core_op(c, op, ...) \
(((c) && (c)->core_ops && (c)->core_ops->op) ? \
((c)->core_ops->op(__VA_ARGS__)) : 0)
struct msm_vidc_inst;
enum vidc_ports {
OUTPUT_PORT,
CAPTURE_PORT,
MAX_PORT_NUM
};
enum vidc_core_state {
VIDC_CORE_UNINIT = 0,
VIDC_CORE_INIT,
VIDC_CORE_INIT_DONE,
};
/*
* Do not change the enum values unless
* you know what you are doing
*/
enum instance_state {
MSM_VIDC_CORE_UNINIT_DONE = 0x0001,
MSM_VIDC_CORE_INIT,
MSM_VIDC_CORE_INIT_DONE,
MSM_VIDC_OPEN,
MSM_VIDC_OPEN_DONE,
MSM_VIDC_LOAD_RESOURCES,
MSM_VIDC_LOAD_RESOURCES_DONE,
MSM_VIDC_START,
MSM_VIDC_START_DONE,
MSM_VIDC_STOP,
MSM_VIDC_STOP_DONE,
MSM_VIDC_RELEASE_RESOURCES,
MSM_VIDC_RELEASE_RESOURCES_DONE,
MSM_VIDC_CLOSE,
MSM_VIDC_CLOSE_DONE,
MSM_VIDC_CORE_UNINIT,
MSM_VIDC_CORE_INVALID
};
struct buf_info {
struct list_head list;
struct vb2_buffer *buf;
};
struct msm_vidc_list {
struct list_head list;
struct mutex lock;
};
static inline void INIT_MSM_VIDC_LIST(struct msm_vidc_list *mlist)
{
mutex_init(&mlist->lock);
INIT_LIST_HEAD(&mlist->list);
}
static inline void DEINIT_MSM_VIDC_LIST(struct msm_vidc_list *mlist)
{
mutex_destroy(&mlist->lock);
}
enum buffer_owner {
DRIVER,
FIRMWARE,
CLIENT,
MAX_OWNER
};
struct vidc_freq_data {
struct list_head list;
u32 device_addr;
unsigned long freq;
bool turbo;
};
struct vidc_input_cr_data {
struct list_head list;
u32 index;
u32 input_cr;
};
struct recon_buf {
struct list_head list;
u32 buffer_index;
u32 CR;
u32 CF;
};
struct eos_buf {
struct list_head list;
struct msm_smem smem;
};
struct internal_buf {
struct list_head list;
enum hal_buffer buffer_type;
struct msm_smem smem;
enum buffer_owner buffer_ownership;
bool mark_remove;
};
struct msm_vidc_csc_coeff {
u32 *vpe_csc_custom_matrix_coeff;
u32 *vpe_csc_custom_bias_coeff;
u32 *vpe_csc_custom_limit_coeff;
};
struct msm_vidc_buf_data {
struct list_head list;
u32 index;
u32 mark_data;
u32 mark_target;
};
struct msm_vidc_common_data {
char key[128];
int value;
};
struct msm_vidc_codec_data {
u32 fourcc;
enum session_type session_type;
int vpp_cycles;
int vsp_cycles;
int low_power_cycles;
};
enum efuse_purpose {
SKU_VERSION = 0,
};
enum sku_version {
SKU_VERSION_0 = 0,
SKU_VERSION_1,
SKU_VERSION_2,
};
struct msm_vidc_efuse_data {
u32 start_address;
u32 size;
u32 mask;
u32 shift;
enum efuse_purpose purpose;
};
enum vpu_version {
VPU_VERSION_4 = 1,
VPU_VERSION_5,
};
#define IS_VPU_4(ver) \
(ver == VPU_VERSION_4)
#define IS_VPU_5(ver) \
(ver == VPU_VERSION_5)
struct msm_vidc_platform_data {
struct msm_vidc_common_data *common_data;
unsigned int common_data_length;
struct msm_vidc_codec_data *codec_data;
unsigned int codec_data_length;
struct msm_vidc_csc_coeff csc_data;
struct msm_vidc_efuse_data *efuse_data;
unsigned int efuse_data_length;
unsigned int sku_version;
phys_addr_t gcc_register_base;
uint32_t gcc_register_size;
uint32_t vpu_ver;
};
struct msm_vidc_format {
char name[MAX_NAME_LENGTH];
u8 description[32];
u32 fourcc;
int type;
u32 (*get_frame_size)(int plane, u32 height, u32 width);
bool defer_outputs;
u32 input_min_count;
u32 output_min_count;
};
struct msm_vidc_format_constraint {
u32 fourcc;
u32 num_planes;
u32 y_stride_multiples;
u32 y_max_stride;
u32 y_min_plane_buffer_height_multiple;
u32 y_buffer_alignment;
u32 uv_stride_multiples;
u32 uv_max_stride;
u32 uv_min_plane_buffer_height_multiple;
u32 uv_buffer_alignment;
};
struct msm_vidc_drv {
struct mutex lock;
struct list_head cores;
int num_cores;
struct dentry *debugfs_root;
int thermal_level;
u32 sku_version;
};
struct msm_video_device {
int type;
struct video_device vdev;
};
struct session_crop {
u32 left;
u32 top;
u32 width;
u32 height;
};
struct session_prop {
u32 width[MAX_PORT_NUM];
u32 height[MAX_PORT_NUM];
struct session_crop crop_info;
u32 fps;
u32 bitrate;
};
struct buf_queue {
struct vb2_queue vb2_bufq;
struct mutex lock;
unsigned int plane_sizes[VB2_MAX_PLANES];
int num_planes;
};
enum profiling_points {
SYS_INIT = 0,
SESSION_INIT,
LOAD_RESOURCES,
FRAME_PROCESSING,
FW_IDLE,
MAX_PROFILING_POINTS,
};
struct buf_count {
int etb;
int ftb;
int fbd;
int ebd;
};
struct batch_mode {
bool enable;
u32 size;
};
enum dcvs_flags {
MSM_VIDC_DCVS_INCR = BIT(0),
MSM_VIDC_DCVS_DECR = BIT(1),
};
struct clock_data {
int buffer_counter;
u64 load;
u64 load_low;
u64 load_norm;
u64 load_high;
int min_threshold;
int max_threshold;
enum hal_buffer buffer_type;
bool dcvs_mode;
unsigned long bitrate;
unsigned long min_freq;
unsigned long curr_freq;
u32 vpss_cycles;
u32 ise_cycles;
u32 ddr_bw;
u32 sys_cache_bw;
u32 operating_rate;
struct msm_vidc_codec_data *entry;
u32 core_id;
u32 dpb_fourcc;
u32 opb_fourcc;
enum hal_work_mode work_mode;
bool low_latency_mode;
bool turbo_mode;
u32 work_route;
u32 dcvs_flags;
};
struct profile_data {
int start;
int stop;
int cumulative;
char name[64];
int sampling;
int average;
};
struct msm_vidc_debug {
struct profile_data pdata[MAX_PROFILING_POINTS];
int profile;
int samples;
};
enum msm_vidc_modes {
VIDC_SECURE = BIT(0),
VIDC_TURBO = BIT(1),
VIDC_THUMBNAIL = BIT(2),
VIDC_LOW_POWER = BIT(3),
VIDC_REALTIME = BIT(4),
};
struct msm_vidc_core_ops {
unsigned long (*calc_freq)(struct msm_vidc_inst *inst, u32 filled_len);
int (*decide_work_route)(struct msm_vidc_inst *inst);
int (*decide_work_mode)(struct msm_vidc_inst *inst);
};
struct msm_vidc_core {
struct list_head list;
struct mutex lock;
int id;
struct hfi_device *device;
struct msm_vidc_platform_data *platform_data;
struct msm_video_device vdev[MSM_VIDC_MAX_DEVICES];
struct v4l2_device v4l2_dev;
struct list_head instances;
struct dentry *debugfs_root;
enum vidc_core_state state;
struct completion completions[SYS_MSG_END - SYS_MSG_START + 1];
enum msm_vidc_hfi_type hfi_type;
struct msm_vidc_platform_resources resources;
u32 enc_codec_supported;
u32 dec_codec_supported;
u32 codec_count;
struct msm_vidc_capability *capabilities;
struct delayed_work fw_unload_work;
struct work_struct ssr_work;
enum hal_ssr_trigger_type ssr_type;
bool smmu_fault_handled;
bool trigger_ssr;
unsigned long min_freq;
unsigned long curr_freq;
struct msm_vidc_core_ops *core_ops;
};
struct msm_vidc_inst;
struct msm_vidc_inst_smem_ops {
int (*smem_map_dma_buf)(struct msm_vidc_inst *inst,
struct msm_smem *smem);
int (*smem_unmap_dma_buf)(struct msm_vidc_inst *inst,
struct msm_smem *smem);
};
struct msm_vidc_inst {
struct list_head list;
struct mutex sync_lock, lock, flush_lock;
struct msm_vidc_core *core;
enum session_type session_type;
void *session;
struct session_prop prop;
enum instance_state state;
struct msm_vidc_format fmts[MAX_PORT_NUM];
struct buf_queue bufq[MAX_PORT_NUM];
struct msm_vidc_list freqs;
struct msm_vidc_list input_crs;
struct msm_vidc_list scratchbufs;
struct msm_vidc_list persistbufs;
struct msm_vidc_list pending_getpropq;
struct msm_vidc_list outputbufs;
struct msm_vidc_list reconbufs;
struct msm_vidc_list eosbufs;
struct msm_vidc_list registeredbufs;
struct msm_vidc_list cvpbufs;
struct msm_vidc_list etb_data;
struct msm_vidc_list fbd_data;
struct buffer_requirements buff_req;
struct v4l2_ctrl_handler ctrl_handler;
struct completion completions[SESSION_MSG_END - SESSION_MSG_START + 1];
struct v4l2_ctrl **cluster;
struct v4l2_fh event_handler;
struct msm_smem *extradata_handle;
bool in_reconfig;
u32 reconfig_width;
u32 reconfig_height;
struct dentry *debugfs_root;
void *priv;
struct msm_vidc_debug debug;
struct buf_count count;
struct clock_data clk_data;
enum msm_vidc_modes flags;
struct msm_vidc_capability capability;
u32 buffer_size_limit;
enum buffer_mode_type buffer_mode_set[MAX_PORT_NUM];
enum multi_stream stream_output_mode;
struct v4l2_ctrl **ctrls;
int bit_depth;
struct kref kref;
bool in_flush;
u32 pic_struct;
u32 colour_space;
u32 profile;
u32 level;
u32 entropy_mode;
u32 grid_enable;
u32 frame_quality;
struct msm_vidc_codec_data *codec_data;
struct hal_hdr10_pq_sei hdr10_sei_params;
struct batch_mode batch;
struct msm_vidc_inst_smem_ops *smem_ops;
};
extern struct msm_vidc_drv *vidc_driver;
struct msm_vidc_ctrl_cluster {
struct v4l2_ctrl **cluster;
struct list_head list;
};
struct msm_vidc_ctrl {
u32 id;
char name[MAX_NAME_LENGTH];
enum v4l2_ctrl_type type;
s64 minimum;
s64 maximum;
s64 default_value;
u32 step;
u32 menu_skip_mask;
u32 flags;
const char * const *qmenu;
};
void handle_cmd_response(enum hal_command_response cmd, void *data);
int msm_vidc_trigger_ssr(struct msm_vidc_core *core,
enum hal_ssr_trigger_type type);
int msm_vidc_noc_error_info(struct msm_vidc_core *core);
bool heic_encode_session_supported(struct msm_vidc_inst *inst);
int msm_vidc_check_session_supported(struct msm_vidc_inst *inst);
int msm_vidc_check_scaling_supported(struct msm_vidc_inst *inst);
void msm_vidc_queue_v4l2_event(struct msm_vidc_inst *inst, int event_type);
enum msm_vidc_flags {
MSM_VIDC_FLAG_DEFERRED = BIT(0),
MSM_VIDC_FLAG_RBR_PENDING = BIT(1),
MSM_VIDC_FLAG_QUEUED = BIT(2),
};
struct msm_vidc_buffer {
struct list_head list;
struct kref kref;
struct msm_smem smem[VIDEO_MAX_PLANES];
struct vb2_v4l2_buffer vvb;
enum msm_vidc_flags flags;
};
struct msm_vidc_cvp_buffer {
struct list_head list;
struct msm_smem smem;
struct msm_cvp_buffer buf;
};
void msm_comm_handle_thermal_event(void);
int msm_smem_alloc(size_t size, u32 align, u32 flags,
enum hal_buffer buffer_type, int map_kernel,
void *res, u32 session_type, struct msm_smem *smem);
int msm_smem_free(struct msm_smem *smem);
struct context_bank_info *msm_smem_get_context_bank(u32 session_type,
bool is_secure, struct msm_vidc_platform_resources *res,
enum hal_buffer buffer_type);
int msm_smem_map_dma_buf(struct msm_vidc_inst *inst, struct msm_smem *smem);
int msm_smem_unmap_dma_buf(struct msm_vidc_inst *inst, struct msm_smem *smem);
struct dma_buf *msm_smem_get_dma_buf(int fd);
void msm_smem_put_dma_buf(void *dma_buf);
int msm_smem_cache_operations(struct dma_buf *dbuf,
enum smem_cache_ops cache_op, unsigned long offset, unsigned long size);
void msm_vidc_fw_unload_handler(struct work_struct *work);
void msm_vidc_ssr_handler(struct work_struct *work);
/*
* XXX: normally should be in msm_vidc.h, but that's meant for public APIs,
* whereas this is private
*/
int msm_vidc_destroy(struct msm_vidc_inst *inst);
void *vidc_get_drv_data(struct device *dev);
#endif

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*/
#include <linux/debugfs.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/ioctl.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/version.h>
#include <linux/io.h>
#include "msm_vidc_internal.h"
#include "msm_vidc_debug.h"
#define CODEC_ENTRY(n, p, vsp, vpp, lp) \
{ \
.fourcc = n, \
.session_type = p, \
.vsp_cycles = vsp, \
.vpp_cycles = vpp, \
.low_power_cycles = lp \
}
#define EFUSE_ENTRY(sa, s, m, sh, p) \
{ \
.start_address = sa, \
.size = s, \
.mask = m, \
.shift = sh, \
.purpose = p \
}
#define GCC_VIDEO_AXI_REG_START_ADDR 0x10B024
#define GCC_VIDEO_AXI_REG_SIZE 0xC
static struct msm_vidc_codec_data default_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 125, 675, 320),
};
/* Update with SM6150 data */
static struct msm_vidc_codec_data sm6150_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),
CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 50, 200, 200),
};
/* Update with 855 data */
static struct msm_vidc_codec_data sm8150_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 10, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 10, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 10, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),
CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 10, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 10, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 10, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_DECODER, 10, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 10, 200, 200),
};
static struct msm_vidc_codec_data sdm845_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),
CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 50, 200, 200),
};
static struct msm_vidc_codec_data sdm670_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),
CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 50, 200, 200),
};
/*
* Custom conversion coefficients for resolution: 176x144 negative
* coeffs are converted to s4.9 format
* (e.g. -22 converted to ((1 << 13) - 22)
* 3x3 transformation matrix coefficients in s4.9 fixed point format
*/
static u32 vpe_csc_custom_matrix_coeff[HAL_MAX_MATRIX_COEFFS] = {
470, 8170, 8148, 0, 490, 50, 0, 34, 483
};
/* offset coefficients in s9 fixed point format */
static u32 vpe_csc_custom_bias_coeff[HAL_MAX_BIAS_COEFFS] = {
34, 0, 4
};
/* clamping value for Y/U/V([min,max] for Y/U/V) */
static u32 vpe_csc_custom_limit_coeff[HAL_MAX_LIMIT_COEFFS] = {
16, 235, 16, 240, 16, 240
};
static struct msm_vidc_common_data default_common_data[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
};
static struct msm_vidc_common_data sm6150_common_data[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 5,
},
{
.key = "qcom,max-hw-load",
.value = 1216800,
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160,
},
{
.key = "qcom,max-hq-frames-per-sec",
.value = 60,
},
{
.key = "qcom,max-b-frame-size",
.value = 8160,
},
{
.key = "qcom,max-b-frames-per-sec",
.value = 60,
},
{
.key = "qcom,power-collapse-delay",
.value = 1500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 1000,
},
{
.key = "qcom,dcvs",
.value = 1,
},
{
.key = "qcom,fw-cycles",
.value = 733003,
},
};
static struct msm_vidc_common_data sm8150_common_data[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 2, /*
* As per design driver allows 3rd
* instance as well since the secure
* flags were updated later for the
* current instance. Hence total
* secure sessions would be
* max-secure-instances + 1.
*/
},
{
.key = "qcom,max-hw-load",
.value = 3916800, /*
* 1920x1088/256 MBs@480fps. It is less
* any other usecases (ex:
* 3840x2160@120fps, 4096x2160@96ps,
* 7680x4320@30fps)
*/
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160,
},
{
.key = "qcom,max-hq-frames-per-sec",
.value = 60,
},
{
.key = "qcom,max-b-frame-size",
.value = 8160,
},
{
.key = "qcom,max-b-frames-per-sec",
.value = 60,
},
{
.key = "qcom,power-collapse-delay",
.value = 1500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 1000,
},
{
.key = "qcom,debug-timeout",
.value = 0,
},
{
.key = "qcom,domain-cvp",
.value = 1,
},
{
.key = "qcom,decode-batching",
.value = 1,
},
{
.key = "qcom,dcvs",
.value = 1,
},
{
.key = "qcom,fw-cycles",
.value = 760000,
},
};
static struct msm_vidc_common_data sdm845_common_data[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,domain-attr-cache-pagetables",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 5,
},
{
.key = "qcom,max-hw-load",
.value = 3110400, /* 4096x2160@90 */
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160,
},
{
.key = "qcom,max-hq-frames-per-sec",
.value = 60,
},
{
.key = "qcom,max-b-frame-size",
.value = 8160,
},
{
.key = "qcom,max-b-frames-per-sec",
.value = 60,
},
{
.key = "qcom,power-collapse-delay",
.value = 500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 250,
},
{
.key = "qcom,debug-timeout",
.value = 0,
},
{
.key = "qcom,dcvs",
.value = 1,
},
};
static struct msm_vidc_common_data sdm670_common_data_v0[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 5,
},
{
.key = "qcom,max-hw-load",
.value = 1944000,
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160,
},
{
.key = "qcom,max-hq-frames-per-sec",
.value = 60,
},
{
.key = "qcom,max-b-frame-size",
.value = 8160,
},
{
.key = "qcom,max-b-frames-per-sec",
.value = 60,
},
{
.key = "qcom,power-collapse-delay",
.value = 500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 250,
},
{
.key = "qcom,dcvs",
.value = 1,
},
};
static struct msm_vidc_common_data sdm670_common_data_v1[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 5,
},
{
.key = "qcom,max-hw-load",
.value = 1216800,
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160,
},
{
.key = "qcom,max-hq-frames-per-sec",
.value = 60,
},
{
.key = "qcom,max-b-frame-size",
.value = 8160,
},
{
.key = "qcom,max-b-frames-per-sec",
.value = 60,
},
{
.key = "qcom,power-collapse-delay",
.value = 500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 250,
},
{
.key = "qcom,dcvs",
.value = 1,
},
};
static struct msm_vidc_efuse_data sdm670_efuse_data[] = {
EFUSE_ENTRY(0x007801A0, 4, 0x00008000, 0x0f, SKU_VERSION),
};
static struct msm_vidc_platform_data default_data = {
.codec_data = default_codec_data,
.codec_data_length = ARRAY_SIZE(default_codec_data),
.common_data = default_common_data,
.common_data_length = ARRAY_SIZE(default_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,
.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,
.efuse_data = NULL,
.efuse_data_length = 0,
.sku_version = 0,
.gcc_register_base = 0,
.gcc_register_size = 0,
.vpu_ver = VPU_VERSION_5,
};
static struct msm_vidc_platform_data sm6150_data = {
.codec_data = sm6150_codec_data,
.codec_data_length = ARRAY_SIZE(sm6150_codec_data),
.common_data = sm6150_common_data,
.common_data_length = ARRAY_SIZE(sm6150_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,
.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,
.efuse_data = NULL,
.efuse_data_length = 0,
.sku_version = 0,
.gcc_register_base = 0,
.gcc_register_size = 0,
.vpu_ver = VPU_VERSION_4,
};
static struct msm_vidc_platform_data sm8150_data = {
.codec_data = sm8150_codec_data,
.codec_data_length = ARRAY_SIZE(sm8150_codec_data),
.common_data = sm8150_common_data,
.common_data_length = ARRAY_SIZE(sm8150_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,
.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,
.efuse_data = NULL,
.efuse_data_length = 0,
.sku_version = 0,
.gcc_register_base = GCC_VIDEO_AXI_REG_START_ADDR,
.gcc_register_size = GCC_VIDEO_AXI_REG_SIZE,
.vpu_ver = VPU_VERSION_5,
};
static struct msm_vidc_platform_data sdm845_data = {
.codec_data = sdm845_codec_data,
.codec_data_length = ARRAY_SIZE(sdm845_codec_data),
.common_data = sdm845_common_data,
.common_data_length = ARRAY_SIZE(sdm845_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,
.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,
.efuse_data = NULL,
.efuse_data_length = 0,
.sku_version = 0,
.gcc_register_base = 0,
.gcc_register_size = 0,
.vpu_ver = VPU_VERSION_4,
};
static struct msm_vidc_platform_data sdm670_data = {
.codec_data = sdm670_codec_data,
.codec_data_length = ARRAY_SIZE(sdm670_codec_data),
.common_data = sdm670_common_data_v0,
.common_data_length = ARRAY_SIZE(sdm670_common_data_v0),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,
.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,
.efuse_data = sdm670_efuse_data,
.efuse_data_length = ARRAY_SIZE(sdm670_efuse_data),
.sku_version = 0,
.gcc_register_base = 0,
.gcc_register_size = 0,
.vpu_ver = VPU_VERSION_4,
};
static const struct of_device_id msm_vidc_dt_match[] = {
{
.compatible = "qcom,sm6150-vidc",
.data = &sm6150_data,
},
{
.compatible = "qcom,sm8150-vidc",
.data = &sm8150_data,
},
{
.compatible = "qcom,sdm845-vidc",
.data = &sdm845_data,
},
{
.compatible = "qcom,sdm670-vidc",
.data = &sdm670_data,
},
{},
};
MODULE_DEVICE_TABLE(of, msm_vidc_dt_match);
static int msm_vidc_read_efuse(
struct msm_vidc_platform_data *data, struct device *dev)
{
void __iomem *base;
uint32_t i;
struct msm_vidc_efuse_data *efuse_data = data->efuse_data;
uint32_t efuse_data_count = data->efuse_data_length;
for (i = 0; i < efuse_data_count; i++) {
switch ((efuse_data[i]).purpose) {
case SKU_VERSION:
base = devm_ioremap(dev, (efuse_data[i]).start_address,
(efuse_data[i]).size);
if (!base) {
dprintk(VIDC_ERR,
"failed efuse ioremap: res->start %#x, size %d\n",
(efuse_data[i]).start_address,
(efuse_data[i]).size);
return -EINVAL;
} else {
u32 efuse = 0;
efuse = readl_relaxed(base);
data->sku_version =
(efuse & (efuse_data[i]).mask) >>
(efuse_data[i]).shift;
dprintk(VIDC_DBG,
"efuse 0x%x, platform version 0x%x\n",
efuse, data->sku_version);
devm_iounmap(dev, base);
}
break;
default:
break;
}
}
return 0;
}
void *vidc_get_drv_data(struct device *dev)
{
struct msm_vidc_platform_data *driver_data = NULL;
const struct of_device_id *match;
int rc = 0;
if (!IS_ENABLED(CONFIG_OF) || !dev->of_node) {
driver_data = &default_data;
goto exit;
}
match = of_match_node(msm_vidc_dt_match, dev->of_node);
if (match)
driver_data = (struct msm_vidc_platform_data *)match->data;
if (!of_find_property(dev->of_node, "sku-index", NULL) ||
!driver_data) {
goto exit;
} else if (!strcmp(match->compatible, "qcom,sdm670-vidc")) {
rc = msm_vidc_read_efuse(driver_data, dev);
if (rc)
goto exit;
if (driver_data->sku_version == SKU_VERSION_1) {
driver_data->common_data = sdm670_common_data_v1;
driver_data->common_data_length =
ARRAY_SIZE(sdm670_common_data_v1);
}
}
exit:
return driver_data;
}

1311
drivers/media/platform/msm/vidc/msm_vidc_res_parse.c Normal file
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30
drivers/media/platform/msm/vidc/msm_vidc_res_parse.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef DT_PARSE
#define DT_PARSE
#include <linux/of.h>
#include "msm_vidc_resources.h"
#include "msm_vidc_common.h"
void msm_vidc_free_platform_resources(
struct msm_vidc_platform_resources *res);
int read_hfi_type(struct platform_device *pdev);
int read_platform_resources_from_drv_data(
struct msm_vidc_core *core);
int read_platform_resources_from_dt(
struct msm_vidc_platform_resources *res);
int read_context_bank_resources_from_dt(struct platform_device *pdev);
int read_bus_resources_from_dt(struct platform_device *pdev);
int read_mem_cdsp_resources_from_dt(struct platform_device *pdev);
int msm_vidc_load_u32_table(struct platform_device *pdev,
struct device_node *of_node, char *table_name, int struct_size,
u32 **table, u32 *num_elements);
#endif

203
drivers/media/platform/msm/vidc/msm_vidc_resources.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __MSM_VIDC_RESOURCES_H__
#define __MSM_VIDC_RESOURCES_H__
#include <linux/devfreq.h>
#include <linux/platform_device.h>
#include "msm_vidc.h"
#include <linux/soc/qcom/llcc-qcom.h>
#define MAX_BUFFER_TYPES 32
struct dcvs_table {
u32 load;
u32 load_low;
u32 load_high;
u32 supported_codecs;
};
struct dcvs_limit {
u32 min_mbpf;
u32 fps;
};
struct reg_value_pair {
u32 reg;
u32 value;
};
struct reg_set {
struct reg_value_pair *reg_tbl;
int count;
};
struct addr_range {
u32 start;
u32 size;
};
struct addr_set {
struct addr_range *addr_tbl;
int count;
};
struct context_bank_info {
struct list_head list;
const char *name;
u32 buffer_type;
bool is_secure;
struct addr_range addr_range;
struct device *dev;
struct dma_iommu_mapping *mapping;
};
struct buffer_usage_table {
u32 buffer_type;
u32 tz_usage;
};
struct buffer_usage_set {
struct buffer_usage_table *buffer_usage_tbl;
u32 count;
};
struct regulator_info {
struct regulator *regulator;
bool has_hw_power_collapse;
char *name;
};
struct regulator_set {
struct regulator_info *regulator_tbl;
u32 count;
};
struct clock_info {
const char *name;
struct clk *clk;
u32 count;
bool has_scaling;
bool has_mem_retention;
};
struct clock_set {
struct clock_info *clock_tbl;
u32 count;
};
struct bus_info {
char *name;
int master;
int slave;
unsigned int range[2];
const char *governor;
struct device *dev;
struct devfreq_dev_profile devfreq_prof;
struct devfreq *devfreq;
struct msm_bus_client_handle *client;
bool is_prfm_gov_used;
};
struct bus_set {
struct bus_info *bus_tbl;
u32 count;
};
struct allowed_clock_rates_table {
u32 clock_rate;
};
struct clock_profile_entry {
u32 codec_mask;
u32 vpp_cycles;
u32 vsp_cycles;
u32 low_power_cycles;
};
struct clock_freq_table {
struct clock_profile_entry *clk_prof_entries;
u32 count;
};
struct subcache_info {
const char *name;
bool isactive;
bool isset;
struct llcc_slice_desc *subcache;
};
struct subcache_set {
struct subcache_info *subcache_tbl;
u32 count;
};
struct msm_vidc_mem_cdsp {
struct device *dev;
};
struct msm_vidc_platform_resources {
phys_addr_t firmware_base;
phys_addr_t register_base;
phys_addr_t gcc_register_base;
uint32_t register_size;
uint32_t gcc_register_size;
uint32_t irq;
uint32_t sku_version;
struct allowed_clock_rates_table *allowed_clks_tbl;
u32 allowed_clks_tbl_size;
struct clock_freq_table clock_freq_tbl;
struct dcvs_table *dcvs_tbl;
uint32_t dcvs_tbl_size;
struct dcvs_limit *dcvs_limit;
bool sys_cache_present;
bool sys_cache_res_set;
struct subcache_set subcache_set;
struct reg_set reg_set;
struct addr_set qdss_addr_set;
struct buffer_usage_set buffer_usage_set;
uint32_t max_load;
uint32_t max_hq_mbs_per_frame;
uint32_t max_hq_fps;
struct platform_device *pdev;
struct regulator_set regulator_set;
struct clock_set clock_set;
struct bus_set bus_set;
bool use_non_secure_pil;
bool sw_power_collapsible;
bool slave_side_cp;
struct list_head context_banks;
bool thermal_mitigable;
const char *fw_name;
const char *hfi_version;
bool never_unload_fw;
bool debug_timeout;
uint32_t pm_qos_latency_us;
uint32_t max_inst_count;
uint32_t max_secure_inst_count;
int msm_vidc_hw_rsp_timeout;
int msm_vidc_firmware_unload_delay;
uint32_t msm_vidc_pwr_collapse_delay;
bool domain_cvp;
bool non_fatal_pagefaults;
bool cache_pagetables;
bool decode_batching;
bool dcvs;
struct msm_vidc_codec_data *codec_data;
int codec_data_count;
struct msm_vidc_csc_coeff *csc_coeff_data;
struct msm_vidc_mem_cdsp mem_cdsp;
uint32_t vpu_ver;
uint32_t fw_cycles;
};
static inline bool is_iommu_present(struct msm_vidc_platform_resources *res)
{
return !list_empty(&res->context_banks);
}
#endif

476
drivers/media/platform/msm/vidc/venus_boot.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
*/
#define VIDC_DBG_LABEL "venus_boot"
#include <asm/dma-iommu.h>
#include <asm/page.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iommu.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/sizes.h>
#include <linux/slab.h>
#include <soc/qcom/subsystem_notif.h>
#include <soc/qcom/subsystem_restart.h>
#include "msm_vidc_debug.h"
#include "vidc_hfi_io.h"
#include "venus_boot.h"
/* VENUS WRAPPER registers */
#define VENUS_WRAPPER_SEC_CPA_START_ADDR \
(VIDC_WRAPPER_BASE_OFFS + 0x1020)
#define VENUS_WRAPPER_SEC_CPA_END_ADDR \
(VIDC_WRAPPER_BASE_OFFS + 0x1024)
#define VENUS_WRAPPER_SEC_FW_START_ADDR \
(VIDC_WRAPPER_BASE_OFFS + 0x1028)
#define VENUS_WRAPPER_SEC_FW_END_ADDR \
(VIDC_WRAPPER_BASE_OFFS + 0x102C)
#define VENUS_WRAPPER_A9SS_SW_RESET (VIDC_WRAPPER_BASE_OFFS + 0x3000)
/* VENUS VBIF registers */
#define VENUS_VBIF_CLKON_FORCE_ON BIT(0)
#define VENUS_VBIF_ADDR_TRANS_EN (VIDC_VBIF_BASE_OFFS + 0x1000)
#define VENUS_VBIF_AT_OLD_BASE (VIDC_VBIF_BASE_OFFS + 0x1004)
#define VENUS_VBIF_AT_OLD_HIGH (VIDC_VBIF_BASE_OFFS + 0x1008)
#define VENUS_VBIF_AT_NEW_BASE (VIDC_VBIF_BASE_OFFS + 0x1010)
#define VENUS_VBIF_AT_NEW_HIGH (VIDC_VBIF_BASE_OFFS + 0x1018)
/* Poll interval in uS */
#define POLL_INTERVAL_US 50
#define VENUS_REGION_SIZE 0x00500000
static struct {
struct msm_vidc_platform_resources *resources;
struct regulator *gdsc;
const char *reg_name;
void __iomem *reg_base;
void __iomem *gcc_base;
struct device *iommu_ctx_bank_dev;
struct dma_iommu_mapping *mapping;
dma_addr_t fw_iova;
bool is_booted;
bool hw_ver_checked;
u32 fw_sz;
u32 hw_ver_major;
u32 hw_ver_minor;
void *venus_notif_hdle;
} *venus_data = NULL;
/* Get venus clocks and set rates for rate-settable clocks */
static int venus_clock_setup(void)
{
int i, rc = 0;
unsigned long rate;
struct msm_vidc_platform_resources *res = venus_data->resources;
struct clock_info *cl;
for (i = 0; i < res->clock_set.count; i++) {
cl = &res->clock_set.clock_tbl[i];
/* Make sure rate-settable clocks' rates are set */
if (!clk_get_rate(cl->clk) && cl->count) {
rate = clk_round_rate(cl->clk, 0);
rc = clk_set_rate(cl->clk, rate);
if (rc) {
dprintk(VIDC_ERR,
"Failed to set clock rate %lu %s: %d\n",
rate, cl->name, rc);
break;
}
}
}
return rc;
}
static int venus_clock_prepare_enable(void)
{
int i, rc = 0;
struct msm_vidc_platform_resources *res = venus_data->resources;
struct clock_info *cl;
for (i = 0; i < res->clock_set.count; i++) {
cl = &res->clock_set.clock_tbl[i];
rc = clk_prepare_enable(cl->clk);
if (rc) {
dprintk(VIDC_ERR, "failed to enable %s\n", cl->name);
for (i--; i >= 0; i--) {
cl = &res->clock_set.clock_tbl[i];
clk_disable_unprepare(cl->clk);
}
return rc;
}
}
return rc;
}
static void venus_clock_disable_unprepare(void)
{
struct msm_vidc_platform_resources *res = venus_data->resources;
struct clock_info *cl;
int i = res->clock_set.count;
for (i--; i >= 0; i--) {
cl = &res->clock_set.clock_tbl[i];
clk_disable_unprepare(cl->clk);
}
}
static int venus_setup_cb(struct device *dev,
u32 size)
{
dma_addr_t va_start = 0x0;
size_t va_size = size;
venus_data->mapping = arm_iommu_create_mapping(
dev->bus, va_start, va_size);
if (IS_ERR_OR_NULL(venus_data->mapping)) {
dprintk(VIDC_ERR, "%s: failed to create mapping for %s\n",
__func__, dev_name(dev));
return -ENODEV;
}
dprintk(VIDC_DBG,
"%s Attached device %pK and created mapping %pK for %s\n",
__func__, dev, venus_data->mapping, dev_name(dev));
return 0;
}
static int pil_venus_mem_setup(size_t size)
{
int rc = 0;
if (!venus_data->mapping) {
size = round_up(size, SZ_4K);
rc = venus_setup_cb(venus_data->iommu_ctx_bank_dev, size);
if (rc) {
dprintk(VIDC_ERR,
"%s: Failed to setup context bank for venus : %s\n",
__func__,
dev_name(venus_data->iommu_ctx_bank_dev));
return rc;
}
venus_data->fw_sz = size;
}
return rc;
}
static int pil_venus_auth_and_reset(void)
{
int rc;
phys_addr_t fw_bias = venus_data->resources->firmware_base;
void __iomem *reg_base = venus_data->reg_base;
u32 ver;
bool iommu_present = is_iommu_present(venus_data->resources);
struct device *dev = venus_data->iommu_ctx_bank_dev;
if (!fw_bias) {
dprintk(VIDC_ERR, "FW bias is not valid\n");
return -EINVAL;
}
venus_data->fw_iova = (dma_addr_t)NULL;
/* Get Venus version number */
if (!venus_data->hw_ver_checked) {
ver = readl_relaxed(reg_base + VIDC_WRAPPER_HW_VERSION);
venus_data->hw_ver_minor = (ver & 0x0FFF0000) >> 16;
venus_data->hw_ver_major = (ver & 0xF0000000) >> 28;
venus_data->hw_ver_checked = true;
}
if (iommu_present) {
u32 cpa_start_addr, cpa_end_addr, fw_start_addr, fw_end_addr;
/* Get the cpa and fw start/end addr */
cpa_start_addr =
VENUS_WRAPPER_SEC_CPA_START_ADDR;
cpa_end_addr =
VENUS_WRAPPER_SEC_CPA_END_ADDR;
fw_start_addr =
VENUS_WRAPPER_SEC_FW_START_ADDR;
fw_end_addr =
VENUS_WRAPPER_SEC_FW_END_ADDR;
/* Program CPA start and end address */
writel_relaxed(0, reg_base + cpa_start_addr);
writel_relaxed(venus_data->fw_sz, reg_base + cpa_end_addr);
/* Program FW start and end address */
writel_relaxed(0, reg_base + fw_start_addr);
writel_relaxed(venus_data->fw_sz, reg_base + fw_end_addr);
} else {
rc = regulator_enable(venus_data->gdsc);
if (rc) {
dprintk(VIDC_ERR, "GDSC enable failed\n");
goto err;
}
rc = venus_clock_prepare_enable();
if (rc) {
dprintk(VIDC_ERR, "Clock prepare and enable failed\n");
regulator_disable(venus_data->gdsc);
goto err;
}
writel_relaxed(0, reg_base + VENUS_VBIF_AT_OLD_BASE);
writel_relaxed(VENUS_REGION_SIZE,
reg_base + VENUS_VBIF_AT_OLD_HIGH);
writel_relaxed(fw_bias, reg_base + VENUS_VBIF_AT_NEW_BASE);
writel_relaxed(fw_bias + VENUS_REGION_SIZE,
reg_base + VENUS_VBIF_AT_NEW_HIGH);
writel_relaxed(0x7F007F, reg_base + VENUS_VBIF_ADDR_TRANS_EN);
venus_clock_disable_unprepare();
regulator_disable(venus_data->gdsc);
}
/* Make sure all register writes are committed. */
mb();
/*
* Need to wait 10 cycles of internal clocks before bringing ARM9
* out of reset.
*/
udelay(1);
if (iommu_present) {
phys_addr_t pa = fw_bias;
rc = arm_iommu_attach_device(dev, venus_data->mapping);
if (rc) {
dprintk(VIDC_ERR,
"Failed to attach iommu for %s : %d\n",
dev_name(dev), rc);
goto release_mapping;
}
dprintk(VIDC_DBG, "Attached and created mapping for %s\n",
dev_name(dev));
/* Map virtual addr space 0 - fw_sz to fw phys addr space */
rc = iommu_map(venus_data->mapping->domain,
venus_data->fw_iova, pa, venus_data->fw_sz,
IOMMU_READ|IOMMU_WRITE|IOMMU_PRIV);
if (!rc) {
dprintk(VIDC_DBG,
"%s - Successfully mapped and performed test translation!\n",
dev_name(dev));
}
if (rc || (venus_data->fw_iova != 0)) {
dprintk(VIDC_ERR, "%s - Failed to setup IOMMU\n",
dev_name(dev));
goto err_iommu_map;
}
}
/* Bring Arm9 out of reset */
writel_relaxed(0, reg_base + VENUS_WRAPPER_A9SS_SW_RESET);
venus_data->is_booted = true;
return 0;
err_iommu_map:
if (iommu_present)
arm_iommu_detach_device(dev);
release_mapping:
if (iommu_present)
arm_iommu_release_mapping(venus_data->mapping);
err:
return rc;
}
static int pil_venus_shutdown(void)
{
void __iomem *reg_base = venus_data->reg_base;
u32 reg;
int rc;
if (!venus_data->is_booted)
return 0;
/* Assert the reset to ARM9 */
reg = readl_relaxed(reg_base + VENUS_WRAPPER_A9SS_SW_RESET);
reg |= BIT(4);
writel_relaxed(reg, reg_base + VENUS_WRAPPER_A9SS_SW_RESET);
/* Make sure reset is asserted before the mapping is removed */
mb();
if (is_iommu_present(venus_data->resources)) {
iommu_unmap(venus_data->mapping->domain, venus_data->fw_iova,
venus_data->fw_sz);
arm_iommu_detach_device(venus_data->iommu_ctx_bank_dev);
}
/*
* Force the VBIF clk to be on to avoid AXI bridge halt ack failure
* for certain Venus version.
*/
if (venus_data->hw_ver_major == 0x1 &&
(venus_data->hw_ver_minor == 0x2 ||
venus_data->hw_ver_minor == 0x3)) {
reg = readl_relaxed(reg_base + VIDC_VENUS_VBIF_CLK_ON);
reg |= VENUS_VBIF_CLKON_FORCE_ON;
writel_relaxed(reg, reg_base + VIDC_VENUS_VBIF_CLK_ON);
}
/* Halt AXI and AXI OCMEM VBIF Access */
reg = readl_relaxed(reg_base + VENUS_VBIF_AXI_HALT_CTRL0);
reg |= VENUS_VBIF_AXI_HALT_CTRL0_HALT_REQ;
writel_relaxed(reg, reg_base + VENUS_VBIF_AXI_HALT_CTRL0);
/* Request for AXI bus port halt */
rc = readl_poll_timeout(reg_base + VENUS_VBIF_AXI_HALT_CTRL1,
reg, reg & VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK,
POLL_INTERVAL_US,
VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US);
if (rc)
dprintk(VIDC_ERR, "Port halt timeout\n");
venus_data->is_booted = false;
return 0;
}
static int venus_notifier_cb(struct notifier_block *this, unsigned long code,
void *ss_handle)
{
struct notif_data *data = (struct notif_data *)ss_handle;
static bool venus_data_set;
int ret;
if (!data->no_auth)
return NOTIFY_DONE;
if (!venus_data_set) {
ret = venus_clock_setup();
if (ret)
return ret;
ret = of_property_read_string(data->pdev->dev.of_node,
"qcom,proxy-reg-names", &venus_data->reg_name);
if (ret)
return ret;
venus_data->gdsc = devm_regulator_get(
&data->pdev->dev, venus_data->reg_name);
if (IS_ERR(venus_data->gdsc)) {
dprintk(VIDC_ERR, "Failed to get Venus GDSC\n");
return -ENODEV;
}
venus_data_set = true;
}
if (code != SUBSYS_AFTER_POWERUP && code != SUBSYS_AFTER_SHUTDOWN)
return NOTIFY_DONE;
ret = regulator_enable(venus_data->gdsc);
if (ret) {
dprintk(VIDC_ERR, "GDSC enable failed\n");
return ret;
}
ret = venus_clock_prepare_enable();
if (ret) {
dprintk(VIDC_ERR, "Clock prepare and enable failed\n");
goto err_clks;
}
if (code == SUBSYS_AFTER_POWERUP) {
if (is_iommu_present(venus_data->resources))
pil_venus_mem_setup(VENUS_REGION_SIZE);
pil_venus_auth_and_reset();
} else if (code == SUBSYS_AFTER_SHUTDOWN)
pil_venus_shutdown();
venus_clock_disable_unprepare();
regulator_disable(venus_data->gdsc);
return NOTIFY_DONE;
err_clks:
regulator_disable(venus_data->gdsc);
return ret;
}
static struct notifier_block venus_notifier = {
.notifier_call = venus_notifier_cb,
};
int venus_boot_init(struct msm_vidc_platform_resources *res,
struct context_bank_info *cb)
{
int rc = 0;
if (!res || !cb) {
dprintk(VIDC_ERR, "Invalid platform resource handle\n");
return -EINVAL;
}
venus_data = kzalloc(sizeof(*venus_data), GFP_KERNEL);
if (!venus_data)
return -ENOMEM;
venus_data->resources = res;
venus_data->iommu_ctx_bank_dev = cb->dev;
if (!venus_data->iommu_ctx_bank_dev) {
dprintk(VIDC_ERR, "Invalid venus context bank device\n");
return -ENODEV;
}
venus_data->reg_base = ioremap_nocache(res->register_base,
(unsigned long)res->register_size);
dprintk(VIDC_DBG, "venus reg: base %x size %x\n",
res->register_base, res->register_size);
if (!venus_data->reg_base) {
dprintk(VIDC_ERR,
"could not map reg addr %pa of size %d\n",
&res->register_base, res->register_size);
rc = -ENOMEM;
goto err_ioremap_fail;
}
venus_data->gcc_base = ioremap_nocache(res->gcc_register_base,
(unsigned long)res->gcc_register_size);
dprintk(VIDC_DBG, "gcc reg: base %x size %x\n",
res->gcc_register_base, res->gcc_register_size);
if (!venus_data->gcc_base) {
dprintk(VIDC_ERR,
"could not map reg addr %pa of size %d\n",
&res->gcc_register_base,
res->gcc_register_size);
rc = -ENOMEM;
goto err_ioremap_fail;
}
venus_data->venus_notif_hdle = subsys_notif_register_notifier("venus",
&venus_notifier);
if (IS_ERR(venus_data->venus_notif_hdle)) {
dprintk(VIDC_ERR, "register event notification failed\n");
rc = PTR_ERR(venus_data->venus_notif_hdle);
goto err_subsys_notif;
}
return rc;
err_subsys_notif:
err_ioremap_fail:
kfree(venus_data);
return rc;
}
void venus_boot_deinit(void)
{
venus_data->resources = NULL;
subsys_notif_unregister_notifier(venus_data->venus_notif_hdle,
&venus_notifier);
kfree(venus_data);
}

14
drivers/media/platform/msm/vidc/venus_boot.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __VENUS_BOOT_H__
#define __VENUS_BOOT_H__
#include "msm_vidc_resources.h"
int venus_boot_init(struct msm_vidc_platform_resources *res,
struct context_bank_info *cb);
void venus_boot_deinit(void);
#endif /* __VENUS_BOOT_H__ */

5240
drivers/media/platform/msm/vidc/venus_hfi.c Normal file
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284
drivers/media/platform/msm/vidc/venus_hfi.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __H_VENUS_HFI_H__
#define __H_VENUS_HFI_H__
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/pm_qos.h>
#include <linux/spinlock.h>
#include "vidc_hfi_api.h"
#include "vidc_hfi_helper.h"
#include "vidc_hfi_api.h"
#include "vidc_hfi.h"
#include "msm_vidc_resources.h"
#include "hfi_packetization.h"
#define HFI_MASK_QHDR_TX_TYPE 0xFF000000
#define HFI_MASK_QHDR_RX_TYPE 0x00FF0000
#define HFI_MASK_QHDR_PRI_TYPE 0x0000FF00
#define HFI_MASK_QHDR_Q_ID_TYPE 0x000000FF
#define HFI_Q_ID_HOST_TO_CTRL_CMD_Q 0x00
#define HFI_Q_ID_CTRL_TO_HOST_MSG_Q 0x01
#define HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q 0x02
#define HFI_MASK_QHDR_STATUS 0x000000FF
#define VIDC_MAX_UNCOMPRESSED_FMT_PLANES 3
#define VIDC_IFACEQ_NUMQ 3
#define VIDC_IFACEQ_CMDQ_IDX 0
#define VIDC_IFACEQ_MSGQ_IDX 1
#define VIDC_IFACEQ_DBGQ_IDX 2
#define VIDC_IFACEQ_MAX_BUF_COUNT 50
#define VIDC_IFACE_MAX_PARALLEL_CLNTS 16
#define VIDC_IFACEQ_DFLT_QHDR 0x01010000
#define VIDC_MAX_NAME_LENGTH 64
#define VIDC_MAX_PC_SKIP_COUNT 10
#define VIDC_MAX_SUBCACHES 4
#define VIDC_MAX_SUBCACHE_SIZE 52
struct hfi_queue_table_header {
u32 qtbl_version;
u32 qtbl_size;
u32 qtbl_qhdr0_offset;
u32 qtbl_qhdr_size;
u32 qtbl_num_q;
u32 qtbl_num_active_q;
void *device_addr;
char name[256];
};
struct hfi_queue_header {
u32 qhdr_status;
u32 qhdr_start_addr;
u32 qhdr_type;
u32 qhdr_q_size;
u32 qhdr_pkt_size;
u32 qhdr_pkt_drop_cnt;
u32 qhdr_rx_wm;
u32 qhdr_tx_wm;
u32 qhdr_rx_req;
u32 qhdr_tx_req;
u32 qhdr_rx_irq_status;
u32 qhdr_tx_irq_status;
u32 qhdr_read_idx;
u32 qhdr_write_idx;
};
struct hfi_mem_map_table {
u32 mem_map_num_entries;
u32 mem_map_table_base_addr;
};
struct hfi_mem_map {
u32 virtual_addr;
u32 physical_addr;
u32 size;
u32 attr;
};
#define VIDC_IFACEQ_TABLE_SIZE (sizeof(struct hfi_queue_table_header) \
+ sizeof(struct hfi_queue_header) * VIDC_IFACEQ_NUMQ)
#define VIDC_IFACEQ_QUEUE_SIZE (VIDC_IFACEQ_MAX_PKT_SIZE * \
VIDC_IFACEQ_MAX_BUF_COUNT * VIDC_IFACE_MAX_PARALLEL_CLNTS)
#define VIDC_IFACEQ_GET_QHDR_START_ADDR(ptr, i) \
(void *)((ptr + sizeof(struct hfi_queue_table_header)) + \
(i * sizeof(struct hfi_queue_header)))
#define QDSS_SIZE 4096
#define SFR_SIZE 4096
#define QUEUE_SIZE (VIDC_IFACEQ_TABLE_SIZE + \
(VIDC_IFACEQ_QUEUE_SIZE * VIDC_IFACEQ_NUMQ))
#define ALIGNED_QDSS_SIZE ALIGN(QDSS_SIZE, SZ_4K)
#define ALIGNED_SFR_SIZE ALIGN(SFR_SIZE, SZ_4K)
#define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K)
#define SHARED_QSIZE ALIGN(ALIGNED_SFR_SIZE + ALIGNED_QUEUE_SIZE + \
ALIGNED_QDSS_SIZE, SZ_1M)
enum vidc_hw_reg {
VIDC_HWREG_CTRL_STATUS = 0x1,
VIDC_HWREG_QTBL_INFO = 0x2,
VIDC_HWREG_QTBL_ADDR = 0x3,
VIDC_HWREG_CTRLR_RESET = 0x4,
VIDC_HWREG_IFACEQ_FWRXREQ = 0x5,
VIDC_HWREG_IFACEQ_FWTXREQ = 0x6,
VIDC_HWREG_VHI_SOFTINTEN = 0x7,
VIDC_HWREG_VHI_SOFTINTSTATUS = 0x8,
VIDC_HWREG_VHI_SOFTINTCLR = 0x9,
VIDC_HWREG_HVI_SOFTINTEN = 0xA,
};
struct vidc_mem_addr {
u32 align_device_addr;
u8 *align_virtual_addr;
u32 mem_size;
struct msm_smem mem_data;
};
struct vidc_iface_q_info {
void *q_hdr;
struct vidc_mem_addr q_array;
};
/*
* These are helper macros to iterate over various lists within
* venus_hfi_device->res. The intention is to cut down on a lot of boiler-plate
* code
*/
/* Read as "for each 'thing' in a set of 'thingies'" */
#define venus_hfi_for_each_thing(__device, __thing, __thingy) \
venus_hfi_for_each_thing_continue(__device, __thing, __thingy, 0)
#define venus_hfi_for_each_thing_reverse(__device, __thing, __thingy) \
venus_hfi_for_each_thing_reverse_continue(__device, __thing, __thingy, \
(__device)->res->__thingy##_set.count - 1)
/* TODO: the __from parameter technically not required since we can figure it
* out with some pointer magic (i.e. __thing - __thing##_tbl[0]). If this macro
* sees extensive use, probably worth cleaning it up but for now omitting it
* since it introduces unnecessary complexity.
*/
#define venus_hfi_for_each_thing_continue(__device, __thing, __thingy, __from) \
for (__thing = &(__device)->res->\
__thingy##_set.__thingy##_tbl[__from]; \
__thing < &(__device)->res->__thingy##_set.__thingy##_tbl[0] + \
((__device)->res->__thingy##_set.count - __from); \
++__thing)
#define venus_hfi_for_each_thing_reverse_continue(__device, __thing, __thingy, \
__from) \
for (__thing = &(__device)->res->\
__thingy##_set.__thingy##_tbl[__from]; \
__thing >= &(__device)->res->__thingy##_set.__thingy##_tbl[0]; \
--__thing)
/* Regular set helpers */
#define venus_hfi_for_each_regulator(__device, __rinfo) \
venus_hfi_for_each_thing(__device, __rinfo, regulator)
#define venus_hfi_for_each_regulator_reverse(__device, __rinfo) \
venus_hfi_for_each_thing_reverse(__device, __rinfo, regulator)
#define venus_hfi_for_each_regulator_reverse_continue(__device, __rinfo, \
__from) \
venus_hfi_for_each_thing_reverse_continue(__device, __rinfo, \
regulator, __from)
/* Clock set helpers */
#define venus_hfi_for_each_clock(__device, __cinfo) \
venus_hfi_for_each_thing(__device, __cinfo, clock)
#define venus_hfi_for_each_clock_reverse(__device, __cinfo) \
venus_hfi_for_each_thing_reverse(__device, __cinfo, clock)
#define venus_hfi_for_each_clock_reverse_continue(__device, __rinfo, \
__from) \
venus_hfi_for_each_thing_reverse_continue(__device, __rinfo, \
clock, __from)
/* Bus set helpers */
#define venus_hfi_for_each_bus(__device, __binfo) \
venus_hfi_for_each_thing(__device, __binfo, bus)
#define venus_hfi_for_each_bus_reverse(__device, __binfo) \
venus_hfi_for_each_thing_reverse(__device, __binfo, bus)
/* Subcache set helpers */
#define venus_hfi_for_each_subcache(__device, __sinfo) \
venus_hfi_for_each_thing(__device, __sinfo, subcache)
#define venus_hfi_for_each_subcache_reverse(__device, __sinfo) \
venus_hfi_for_each_thing_reverse(__device, __sinfo, subcache)
#define call_venus_op(d, op, ...) \
(((d) && (d)->vpu_ops && (d)->vpu_ops->op) ? \
((d)->vpu_ops->op(__VA_ARGS__)):0)
/* Internal data used in vidc_hal not exposed to msm_vidc*/
struct hal_data {
u32 irq;
phys_addr_t firmware_base;
u8 __iomem *register_base;
u8 __iomem *gcc_reg_base;
u32 register_size;
u32 gcc_reg_size;
};
struct venus_resources {
struct msm_vidc_fw fw;
};
enum dsp_flag {
DSP_INIT = BIT(0),
DSP_SUSPEND = BIT(1),
};
enum venus_hfi_state {
VENUS_STATE_DEINIT = 1,
VENUS_STATE_INIT,
};
struct venus_hfi_device;
struct venus_hfi_vpu_ops {
void (*interrupt_init)(struct venus_hfi_device *ptr);
void (*setup_dsp_uc_memmap)(struct venus_hfi_device *device);
void (*clock_config_on_enable)(struct venus_hfi_device *device);
};
struct venus_hfi_device {
struct list_head list;
struct list_head sess_head;
u32 intr_status;
u32 device_id;
u32 clk_freq;
u32 last_packet_type;
unsigned long clk_bitrate;
unsigned long scaled_rate;
struct msm_vidc_gov_data bus_vote;
bool power_enabled;
struct mutex lock;
msm_vidc_callback callback;
struct vidc_mem_addr iface_q_table;
struct vidc_mem_addr dsp_iface_q_table;
struct vidc_mem_addr qdss;
struct vidc_mem_addr sfr;
struct vidc_mem_addr mem_addr;
struct vidc_iface_q_info iface_queues[VIDC_IFACEQ_NUMQ];
struct vidc_iface_q_info dsp_iface_queues[VIDC_IFACEQ_NUMQ];
u32 dsp_flags;
struct hal_data *hal_data;
struct workqueue_struct *vidc_workq;
struct workqueue_struct *venus_pm_workq;
int spur_count;
int reg_count;
struct venus_resources resources;
struct msm_vidc_platform_resources *res;
enum venus_hfi_state state;
struct hfi_packetization_ops *pkt_ops;
enum hfi_packetization_type packetization_type;
struct msm_vidc_cb_info *response_pkt;
u8 *raw_packet;
struct pm_qos_request qos;
unsigned int skip_pc_count;
struct msm_vidc_capability *sys_init_capabilities;
struct venus_hfi_vpu_ops *vpu_ops;
};
void venus_hfi_delete_device(void *device);
int venus_hfi_initialize(struct hfi_device *hdev, u32 device_id,
struct msm_vidc_platform_resources *res,
hfi_cmd_response_callback callback);
bool venus_hfi_is_session_supported(unsigned long sessions_supported,
enum vidc_vote_data_session session_type);
#endif

64
drivers/media/platform/msm/vidc/vidc_hfi.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#include <linux/slab.h>
#include "msm_vidc_debug.h"
#include "vidc_hfi_api.h"
#include "venus_hfi.h"
struct hfi_device *vidc_hfi_initialize(enum msm_vidc_hfi_type hfi_type,
u32 device_id, struct msm_vidc_platform_resources *res,
hfi_cmd_response_callback callback)
{
struct hfi_device *hdev = NULL;
int rc = 0;
hdev = kzalloc(sizeof(struct hfi_device), GFP_KERNEL);
if (!hdev) {
dprintk(VIDC_ERR, "%s: failed to allocate hdev\n", __func__);
return NULL;
}
switch (hfi_type) {
case VIDC_HFI_VENUS:
rc = venus_hfi_initialize(hdev, device_id, res, callback);
break;
default:
dprintk(VIDC_ERR, "Unsupported host-firmware interface\n");
goto err_hfi_init;
}
if (rc) {
if (rc != -EPROBE_DEFER)
dprintk(VIDC_ERR, "%s device init failed rc = %d",
__func__, rc);
goto err_hfi_init;
}
return hdev;
err_hfi_init:
kfree(hdev);
return ERR_PTR(rc);
}
void vidc_hfi_deinitialize(enum msm_vidc_hfi_type hfi_type,
struct hfi_device *hdev)
{
if (!hdev) {
dprintk(VIDC_ERR, "%s invalid device %pK", __func__, hdev);
return;
}
switch (hfi_type) {
case VIDC_HFI_VENUS:
venus_hfi_delete_device(hdev->hfi_device_data);
break;
default:
dprintk(VIDC_ERR, "Unsupported host-firmware interface\n");
}
kfree(hdev);
}

859
drivers/media/platform/msm/vidc/vidc_hfi.h Normal file
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@ -0,0 +1,859 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __H_VIDC_HFI_H__
#define __H_VIDC_HFI_H__
#include <media/msm_media_info.h>
#include "vidc_hfi_helper.h"
#include "vidc_hfi_api.h"
#define HFI_EVENT_SESSION_SEQUENCE_CHANGED (HFI_OX_BASE + 0x3)
#define HFI_EVENT_SESSION_PROPERTY_CHANGED (HFI_OX_BASE + 0x4)
#define HFI_EVENT_SESSION_LTRUSE_FAILED (HFI_OX_BASE + 0x5)
#define HFI_EVENT_RELEASE_BUFFER_REFERENCE (HFI_OX_BASE + 0x6)
#define HFI_EVENT_DATA_SEQUENCE_CHANGED_SUFFICIENT_BUFFER_RESOURCES \
(HFI_OX_BASE + 0x1)
#define HFI_EVENT_DATA_SEQUENCE_CHANGED_INSUFFICIENT_BUFFER_RESOURCES \
(HFI_OX_BASE + 0x2)
#define HFI_BUFFERFLAG_EOS 0x00000001
#define HFI_BUFFERFLAG_STARTTIME 0x00000002
#define HFI_BUFFERFLAG_DECODEONLY 0x00000004
#define HFI_BUFFERFLAG_DATACORRUPT 0x00000008
#define HFI_BUFFERFLAG_ENDOFFRAME 0x00000010
#define HFI_BUFFERFLAG_SYNCFRAME 0x00000020
#define HFI_BUFFERFLAG_EXTRADATA 0x00000040
#define HFI_BUFFERFLAG_CODECCONFIG 0x00000080
#define HFI_BUFFERFLAG_TIMESTAMPINVALID 0x00000100
#define HFI_BUFFERFLAG_READONLY 0x00000200
#define HFI_BUFFERFLAG_ENDOFSUBFRAME 0x00000400
#define HFI_BUFFERFLAG_EOSEQ 0x00200000
#define HFI_BUFFER_FLAG_MBAFF 0x08000000
#define HFI_BUFFERFLAG_VPE_YUV_601_709_CSC_CLAMP \
0x10000000
#define HFI_BUFFERFLAG_DROP_FRAME 0x20000000
#define HFI_BUFFERFLAG_TEI 0x40000000
#define HFI_BUFFERFLAG_DISCONTINUITY 0x80000000
#define HFI_ERR_SESSION_EMPTY_BUFFER_DONE_OUTPUT_PENDING \
(HFI_OX_BASE + 0x1001)
#define HFI_ERR_SESSION_SAME_STATE_OPERATION \
(HFI_OX_BASE + 0x1002)
#define HFI_ERR_SESSION_SYNC_FRAME_NOT_DETECTED \
(HFI_OX_BASE + 0x1003)
#define HFI_ERR_SESSION_START_CODE_NOT_FOUND \
(HFI_OX_BASE + 0x1004)
#define HFI_BUFFER_MODE_DYNAMIC (HFI_OX_BASE + 0x3)
#define HFI_FLUSH_INPUT (HFI_OX_BASE + 0x1)
#define HFI_FLUSH_OUTPUT (HFI_OX_BASE + 0x2)
#define HFI_FLUSH_ALL (HFI_OX_BASE + 0x4)
#define HFI_EXTRADATA_NONE 0x00000000
#define HFI_EXTRADATA_MB_QUANTIZATION 0x00000001
#define HFI_EXTRADATA_INTERLACE_VIDEO 0x00000002
#define HFI_EXTRADATA_TIMESTAMP 0x00000005
#define HFI_EXTRADATA_S3D_FRAME_PACKING 0x00000006
#define HFI_EXTRADATA_FRAME_RATE 0x00000007
#define HFI_EXTRADATA_PANSCAN_WINDOW 0x00000008
#define HFI_EXTRADATA_RECOVERY_POINT_SEI 0x00000009
#define HFI_EXTRADATA_MPEG2_SEQDISP 0x0000000D
#define HFI_EXTRADATA_STREAM_USERDATA 0x0000000E
#define HFI_EXTRADATA_FRAME_QP 0x0000000F
#define HFI_EXTRADATA_FRAME_BITS_INFO 0x00000010
#define HFI_EXTRADATA_VPX_COLORSPACE 0x00000014
#define HFI_EXTRADATA_UBWC_CR_STAT_INFO 0x00000019
#define HFI_EXTRADATA_MULTISLICE_INFO 0x7F100000
#define HFI_EXTRADATA_NUM_CONCEALED_MB 0x7F100001
#define HFI_EXTRADATA_INDEX 0x7F100002
#define HFI_EXTRADATA_METADATA_LTR 0x7F100004
#define HFI_EXTRADATA_METADATA_FILLER 0x7FE00002
#define HFI_INDEX_EXTRADATA_INPUT_CROP 0x0700000E
#define HFI_INDEX_EXTRADATA_OUTPUT_CROP 0x0700000F
#define HFI_INDEX_EXTRADATA_ASPECT_RATIO 0x7F100003
struct hfi_buffer_alloc_mode {
u32 buffer_type;
u32 buffer_mode;
};
struct hfi_index_extradata_config {
int enable;
u32 index_extra_data_id;
};
struct hfi_extradata_header {
u32 size;
u32 version;
u32 port_index;
u32 type;
u32 data_size;
u8 rg_data[1];
};
#define HFI_INTERLACE_FRAME_PROGRESSIVE 0x01
#define HFI_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST 0x02
#define HFI_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST 0x04
#define HFI_INTERLACE_FRAME_TOPFIELDFIRST 0x08
#define HFI_INTERLACE_FRAME_BOTTOMFIELDFIRST 0x10
#define HFI_INTERLACE_FRAME_MBAFF 0x20
#define HFI_PROPERTY_SYS_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x0000)
#define HFI_PROPERTY_PARAM_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x1000)
#define HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL \
(HFI_PROPERTY_PARAM_OX_START + 0x001)
#define HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO \
(HFI_PROPERTY_PARAM_OX_START + 0x002)
#define HFI_PROPERTY_PARAM_INDEX_EXTRADATA \
(HFI_PROPERTY_PARAM_OX_START + 0x006)
#define HFI_PROPERTY_PARAM_S3D_FRAME_PACKING_EXTRADATA \
(HFI_PROPERTY_PARAM_OX_START + 0x009)
#define HFI_PROPERTY_PARAM_BUFFER_SIZE_MINIMUM \
(HFI_PROPERTY_PARAM_OX_START + 0x00C)
#define HFI_PROPERTY_PARAM_SYNC_BASED_INTERRUPT \
(HFI_PROPERTY_PARAM_OX_START + 0x00E)
#define HFI_PROPERTY_CONFIG_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x02000)
#define HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS \
(HFI_PROPERTY_CONFIG_OX_START + 0x001)
#define HFI_PROPERTY_CONFIG_REALTIME \
(HFI_PROPERTY_CONFIG_OX_START + 0x002)
#define HFI_PROPERTY_CONFIG_PRIORITY \
(HFI_PROPERTY_CONFIG_OX_START + 0x003)
#define HFI_PROPERTY_PARAM_VDEC_OX_START \
(HFI_DOMAIN_BASE_VDEC + HFI_ARCH_OX_OFFSET + 0x3000)
#define HFI_PROPERTY_PARAM_VDEC_CONTINUE_DATA_TRANSFER \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x001)
#define HFI_PROPERTY_PARAM_VDEC_MULTI_VIEW_SELECT \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x003)
#define HFI_PROPERTY_PARAM_VDEC_PICTURE_TYPE_DECODE \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x004)
#define HFI_PROPERTY_PARAM_VDEC_OUTPUT_ORDER \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x005)
#define HFI_PROPERTY_PARAM_VDEC_MB_QUANTIZATION \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x006)
#define HFI_PROPERTY_PARAM_VDEC_NUM_CONCEALED_MB \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x007)
#define HFI_PROPERTY_PARAM_VDEC_OUTPUT2_KEEP_ASPECT_RATIO\
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x009)
#define HFI_PROPERTY_PARAM_VDEC_FRAME_RATE_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x00A)
#define HFI_PROPERTY_PARAM_VDEC_PANSCAN_WNDW_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x00B)
#define HFI_PROPERTY_PARAM_VDEC_RECOVERY_POINT_SEI_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x00C)
#define HFI_PROPERTY_PARAM_VDEC_THUMBNAIL_MODE \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x00D)
#define HFI_PROPERTY_PARAM_VDEC_TIMESTAMP_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x013)
#define HFI_PROPERTY_PARAM_VDEC_INTERLACE_VIDEO_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x014)
#define HFI_PROPERTY_PARAM_VDEC_AVC_SESSION_SELECT \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x015)
#define HFI_PROPERTY_PARAM_VDEC_MPEG2_SEQDISP_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x016)
#define HFI_PROPERTY_PARAM_VDEC_STREAM_USERDATA_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x017)
#define HFI_PROPERTY_PARAM_VDEC_FRAME_QP_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x018)
#define HFI_PROPERTY_PARAM_VDEC_FRAME_BITS_INFO_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x019)
#define HFI_PROPERTY_PARAM_VUI_DISPLAY_INFO_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x01B)
#define HFI_PROPERTY_PARAM_VDEC_VQZIP_SEI_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x001C)
#define HFI_PROPERTY_PARAM_VDEC_VPX_COLORSPACE_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x001D)
#define HFI_PROPERTY_PARAM_VDEC_MASTERING_DISPLAY_COLOUR_SEI_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x001E)
#define HFI_PROPERTY_PARAM_VDEC_CONTENT_LIGHT_LEVEL_SEI_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x001F)
#define HFI_PROPERTY_PARAM_VDEC_COLOUR_REMAPPING_INFO_SEI_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x0020)
#define HFI_PROPERTY_PARAM_VDEC_DOWN_SCALAR \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x0021)
#define HFI_PROPERTY_PARAM_VDEC_UBWC_CR_STAT_INFO_EXTRADATA \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x0022)
#define HFI_PROPERTY_CONFIG_VDEC_OX_START \
(HFI_DOMAIN_BASE_VDEC + HFI_ARCH_OX_OFFSET + 0x4000)
#define HFI_PROPERTY_CONFIG_VDEC_MB_ERROR_MAP_REPORTING \
(HFI_PROPERTY_CONFIG_VDEC_OX_START + 0x002)
#define HFI_PROPERTY_CONFIG_VDEC_MB_ERROR_MAP \
(HFI_PROPERTY_CONFIG_VDEC_OX_START + 0x003)
#define HFI_PROPERTY_CONFIG_VDEC_ENTROPY \
(HFI_PROPERTY_CONFIG_VDEC_OX_START + 0x004)
#define HFI_PROPERTY_PARAM_VENC_OX_START \
(HFI_DOMAIN_BASE_VENC + HFI_ARCH_OX_OFFSET + 0x5000)
#define HFI_PROPERTY_PARAM_VENC_MULTI_SLICE_INFO \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x001)
#define HFI_PROPERTY_PARAM_VENC_H264_IDR_S3D_FRAME_PACKING_NAL \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x002)
#define HFI_PROPERTY_PARAM_VENC_LTR_INFO \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x003)
#define HFI_PROPERTY_PARAM_VENC_MBI_DUMPING \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x005)
#define HFI_PROPERTY_PARAM_VENC_FRAME_QP_EXTRADATA \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x006)
#define HFI_PROPERTY_PARAM_VENC_ROI_QP_EXTRADATA \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x008)
#define HFI_PROPERTY_PARAM_VENC_HDR10PLUS_METADATA_EXTRADATA \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x00A)
#define HFI_PROPERTY_CONFIG_VENC_OX_START \
(HFI_DOMAIN_BASE_VENC + HFI_ARCH_OX_OFFSET + 0x6000)
#define HFI_PROPERTY_PARAM_VPE_OX_START \
(HFI_DOMAIN_BASE_VPE + HFI_ARCH_OX_OFFSET + 0x7000)
#define HFI_PROPERTY_CONFIG_VPE_OX_START \
(HFI_DOMAIN_BASE_VPE + HFI_ARCH_OX_OFFSET + 0x8000)
struct hfi_batch_info {
u32 input_batch_count;
u32 output_batch_count;
};
struct hfi_buffer_count_actual {
u32 buffer_type;
u32 buffer_count_actual;
u32 buffer_count_min_host;
};
struct hfi_buffer_size_minimum {
u32 buffer_type;
u32 buffer_size;
};
struct hfi_buffer_requirements {
u32 buffer_type;
u32 buffer_size;
u32 buffer_region_size;
u32 buffer_count_min;
u32 buffer_count_min_host;
u32 buffer_count_actual;
u32 contiguous;
u32 buffer_alignment;
};
struct hfi_data_payload {
u32 size;
u8 rg_data[1];
};
struct hfi_enable_picture {
u32 picture_type;
};
struct hfi_mb_error_map {
u32 error_map_size;
u8 rg_error_map[1];
};
struct hfi_metadata_pass_through {
int enable;
u32 size;
};
struct hfi_multi_view_select {
u32 view_index;
};
struct hfi_hybrid_hierp {
u32 layers;
};
#define HFI_PRIORITY_LOW 10
#define HFI_PRIOIRTY_MEDIUM 20
#define HFI_PRIORITY_HIGH 30
#define HFI_OUTPUT_ORDER_DISPLAY (HFI_OX_BASE + 0x1)
#define HFI_OUTPUT_ORDER_DECODE (HFI_OX_BASE + 0x2)
#define HFI_RATE_CONTROL_OFF (HFI_OX_BASE + 0x1)
#define HFI_RATE_CONTROL_VBR_VFR (HFI_OX_BASE + 0x2)
#define HFI_RATE_CONTROL_VBR_CFR (HFI_OX_BASE + 0x3)
#define HFI_RATE_CONTROL_CBR_VFR (HFI_OX_BASE + 0x4)
#define HFI_RATE_CONTROL_CBR_CFR (HFI_OX_BASE + 0x5)
#define HFI_RATE_CONTROL_MBR_CFR (HFI_OX_BASE + 0x6)
#define HFI_RATE_CONTROL_MBR_VFR (HFI_OX_BASE + 0x7)
#define HFI_RATE_CONTROL_CQ (HFI_OX_BASE + 0x8)
struct hfi_uncompressed_plane_actual_constraints_info {
u32 buffer_type;
u32 num_planes;
struct hfi_uncompressed_plane_constraints rg_plane_format[1];
};
#define HFI_CMD_SYS_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_CMD_START_OFFSET + 0x0000)
#define HFI_CMD_SYS_SESSION_ABORT (HFI_CMD_SYS_OX_START + 0x001)
#define HFI_CMD_SYS_PING (HFI_CMD_SYS_OX_START + 0x002)
#define HFI_CMD_SESSION_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_CMD_START_OFFSET + 0x1000)
#define HFI_CMD_SESSION_LOAD_RESOURCES (HFI_CMD_SESSION_OX_START + 0x001)
#define HFI_CMD_SESSION_START (HFI_CMD_SESSION_OX_START + 0x002)
#define HFI_CMD_SESSION_STOP (HFI_CMD_SESSION_OX_START + 0x003)
#define HFI_CMD_SESSION_EMPTY_BUFFER (HFI_CMD_SESSION_OX_START + 0x004)
#define HFI_CMD_SESSION_FILL_BUFFER (HFI_CMD_SESSION_OX_START + 0x005)
#define HFI_CMD_SESSION_SUSPEND (HFI_CMD_SESSION_OX_START + 0x006)
#define HFI_CMD_SESSION_RESUME (HFI_CMD_SESSION_OX_START + 0x007)
#define HFI_CMD_SESSION_FLUSH (HFI_CMD_SESSION_OX_START + 0x008)
#define HFI_CMD_SESSION_GET_PROPERTY (HFI_CMD_SESSION_OX_START + 0x009)
#define HFI_CMD_SESSION_PARSE_SEQUENCE_HEADER \
(HFI_CMD_SESSION_OX_START + 0x00A)
#define HFI_CMD_SESSION_RELEASE_BUFFERS \
(HFI_CMD_SESSION_OX_START + 0x00B)
#define HFI_CMD_SESSION_RELEASE_RESOURCES \
(HFI_CMD_SESSION_OX_START + 0x00C)
#define HFI_CMD_SESSION_CONTINUE (HFI_CMD_SESSION_OX_START + 0x00D)
#define HFI_CMD_SESSION_SYNC (HFI_CMD_SESSION_OX_START + 0x00E)
#define HFI_CMD_SESSION_CVP_START \
(HFI_DOMAIN_BASE_CVP + HFI_ARCH_COMMON_OFFSET + \
HFI_CMD_START_OFFSET + 0x1000)
#define HFI_CMD_SESSION_REGISTER_BUFFERS \
(HFI_CMD_SESSION_CVP_START + 0x0A0)
#define HFI_CMD_SESSION_UNREGISTER_BUFFERS \
(HFI_CMD_SESSION_CVP_START + 0x0A1)
#define HFI_MSG_SYS_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_MSG_START_OFFSET + 0x0000)
#define HFI_MSG_SYS_PING_ACK (HFI_MSG_SYS_OX_START + 0x2)
#define HFI_MSG_SYS_SESSION_ABORT_DONE (HFI_MSG_SYS_OX_START + 0x4)
#define HFI_MSG_SESSION_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_MSG_START_OFFSET + 0x1000)
#define HFI_MSG_SESSION_LOAD_RESOURCES_DONE (HFI_MSG_SESSION_OX_START + 0x1)
#define HFI_MSG_SESSION_START_DONE (HFI_MSG_SESSION_OX_START + 0x2)
#define HFI_MSG_SESSION_STOP_DONE (HFI_MSG_SESSION_OX_START + 0x3)
#define HFI_MSG_SESSION_SUSPEND_DONE (HFI_MSG_SESSION_OX_START + 0x4)
#define HFI_MSG_SESSION_RESUME_DONE (HFI_MSG_SESSION_OX_START + 0x5)
#define HFI_MSG_SESSION_FLUSH_DONE (HFI_MSG_SESSION_OX_START + 0x6)
#define HFI_MSG_SESSION_EMPTY_BUFFER_DONE (HFI_MSG_SESSION_OX_START + 0x7)
#define HFI_MSG_SESSION_FILL_BUFFER_DONE (HFI_MSG_SESSION_OX_START + 0x8)
#define HFI_MSG_SESSION_PROPERTY_INFO (HFI_MSG_SESSION_OX_START + 0x9)
#define HFI_MSG_SESSION_RELEASE_RESOURCES_DONE \
(HFI_MSG_SESSION_OX_START + 0xA)
#define HFI_MSG_SESSION_RELEASE_BUFFERS_DONE \
(HFI_MSG_SESSION_OX_START + 0xC)
#define HFI_MSG_SESSION_CVP_START \
(HFI_DOMAIN_BASE_CVP + HFI_ARCH_COMMON_OFFSET + \
HFI_MSG_START_OFFSET + 0x1000)
#define HFI_MSG_SESSION_REGISTER_BUFFERS_DONE \
(HFI_MSG_SESSION_CVP_START + 0x0A0)
#define HFI_MSG_SESSION_UNREGISTER_BUFFERS_DONE \
(HFI_MSG_SESSION_CVP_START + 0x0A1)
#define VIDC_IFACEQ_MAX_PKT_SIZE 1024
#define VIDC_IFACEQ_MED_PKT_SIZE 768
#define VIDC_IFACEQ_MIN_PKT_SIZE 8
#define VIDC_IFACEQ_VAR_SMALL_PKT_SIZE 100
#define VIDC_IFACEQ_VAR_LARGE_PKT_SIZE 512
#define VIDC_IFACEQ_VAR_HUGE_PKT_SIZE (1024*12)
struct hfi_cmd_sys_session_abort_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
struct hfi_cmd_sys_ping_packet {
u32 size;
u32 packet_type;
u32 client_data;
};
struct hfi_cmd_session_load_resources_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
struct hfi_cmd_session_start_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
struct hfi_cmd_session_stop_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
struct hfi_cmd_session_empty_buffer_compressed_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 time_stamp_hi;
u32 time_stamp_lo;
u32 flags;
u32 mark_target;
u32 mark_data;
u32 offset;
u32 alloc_len;
u32 filled_len;
u32 input_tag;
u32 packet_buffer;
u32 extra_data_buffer;
u32 rgData[1];
};
struct hfi_cmd_session_empty_buffer_uncompressed_plane0_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 view_id;
u32 time_stamp_hi;
u32 time_stamp_lo;
u32 flags;
u32 mark_target;
u32 mark_data;
u32 alloc_len;
u32 filled_len;
u32 offset;
u32 input_tag;
u32 packet_buffer;
u32 extra_data_buffer;
u32 rgData[1];
};
struct hfi_cmd_session_empty_buffer_uncompressed_plane1_packet {
u32 flags;
u32 alloc_len;
u32 filled_len;
u32 offset;
u32 packet_buffer2;
u32 rgData[1];
};
struct hfi_cmd_session_empty_buffer_uncompressed_plane2_packet {
u32 flags;
u32 alloc_len;
u32 filled_len;
u32 offset;
u32 packet_buffer3;
u32 rgData[1];
};
struct hfi_cmd_session_fill_buffer_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 stream_id;
u32 offset;
u32 alloc_len;
u32 filled_len;
u32 output_tag;
u32 packet_buffer;
u32 extra_data_buffer;
u32 rgData[1];
};
struct hfi_cmd_session_flush_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 flush_type;
};
struct hfi_cmd_session_suspend_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
struct hfi_cmd_session_resume_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
struct hfi_cmd_session_get_property_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 num_properties;
u32 rg_property_data[1];
};
struct hfi_cmd_session_release_buffer_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 buffer_type;
u32 buffer_size;
u32 extra_data_size;
int response_req;
u32 num_buffers;
u32 rg_buffer_info[1];
};
struct hfi_cmd_session_release_resources_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
struct hfi_msg_sys_session_abort_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
};
struct hfi_msg_sys_ping_ack_packet {
u32 size;
u32 packet_type;
u32 client_data;
};
struct hfi_msg_sys_property_info_packet {
u32 size;
u32 packet_type;
u32 num_properties;
u32 rg_property_data[1];
};
struct hfi_msg_session_load_resources_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
};
struct hfi_msg_session_start_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
};
struct hfi_msg_session_stop_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
};
struct hfi_msg_session_suspend_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
};
struct hfi_msg_session_resume_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
};
struct hfi_msg_session_flush_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
u32 flush_type;
};
struct hfi_ubwc_cr_stats_info_type {
u32 cr_stats_info0;
u32 cr_stats_info1;
u32 cr_stats_info2;
u32 cr_stats_info3;
u32 cr_stats_info4;
u32 cr_stats_info5;
u32 cr_stats_info6;
};
struct hfi_frame_cr_stats_type {
u32 frame_index;
struct hfi_ubwc_cr_stats_info_type ubwc_stats_info;
u32 complexity_number;
};
struct hfi_msg_session_empty_buffer_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
u32 offset;
u32 filled_len;
u32 input_tag;
u32 packet_buffer;
u32 extra_data_buffer;
u32 flags;
struct hfi_frame_cr_stats_type ubwc_cr_stats;
u32 rgData[0];
};
struct hfi_msg_session_fill_buffer_done_compressed_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 time_stamp_hi;
u32 time_stamp_lo;
u32 error_type;
u32 flags;
u32 mark_target;
u32 mark_data;
u32 stats;
u32 offset;
u32 alloc_len;
u32 filled_len;
u32 input_tag;
u32 output_tag;
u32 picture_type;
u32 packet_buffer;
u32 extra_data_buffer;
u32 rgData[0];
};
struct hfi_msg_session_fbd_uncompressed_plane0_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 stream_id;
u32 view_id;
u32 error_type;
u32 time_stamp_hi;
u32 time_stamp_lo;
u32 flags;
u32 mark_target;
u32 mark_data;
u32 stats;
u32 alloc_len;
u32 filled_len;
u32 offset;
u32 frame_width;
u32 frame_height;
u32 start_x_coord;
u32 start_y_coord;
u32 input_tag;
u32 input_tag2;
u32 output_tag;
u32 picture_type;
u32 packet_buffer;
u32 extra_data_buffer;
u32 rgData[0];
};
struct hfi_msg_session_fill_buffer_done_uncompressed_plane1_packet {
u32 flags;
u32 alloc_len;
u32 filled_len;
u32 offset;
u32 packet_buffer2;
u32 rgData[0];
};
struct hfi_msg_session_fill_buffer_done_uncompressed_plane2_packet {
u32 flags;
u32 alloc_len;
u32 filled_len;
u32 offset;
u32 packet_buffer3;
u32 rgData[0];
};
struct hfi_msg_session_property_info_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 num_properties;
u32 rg_property_data[1];
};
struct hfi_msg_session_release_resources_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
};
struct hfi_msg_session_release_buffers_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 error_type;
u32 num_buffers;
u32 rg_buffer_info[1];
};
struct hfi_msg_session_register_buffers_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 client_data;
u32 error_type;
};
struct hfi_msg_session_unregister_buffers_done_packet {
u32 size;
u32 packet_type;
u32 session_id;
u32 client_data;
u32 error_type;
};
struct hfi_extradata_mb_quantization_payload {
u8 rg_mb_qp[1];
};
struct hfi_extradata_timestamp_payload {
u32 time_stamp_low;
u32 time_stamp_high;
};
struct hfi_extradata_s3d_frame_packing_payload {
u32 fpa_id;
int cancel_flag;
u32 fpa_type;
int quin_cunx_flag;
u32 content_interprtation_type;
int spatial_flipping_flag;
int frame0_flipped_flag;
int field_views_flag;
int current_frame_isFrame0_flag;
int frame0_self_contained_flag;
int frame1_self_contained_flag;
u32 frame0_graid_pos_x;
u32 frame0_graid_pos_y;
u32 frame1_graid_pos_x;
u32 frame1_graid_pos_y;
u32 fpa_reserved_byte;
u32 fpa_repetition_period;
int fpa_extension_flag;
};
struct hfi_extradata_interlace_video_payload {
u32 format;
};
struct hfi_conceal_color_type {
u32 value_8bit;
u32 value_10bit;
};
struct hfi_extradata_num_concealed_mb_payload {
u32 num_mb_concealed;
};
struct hfi_extradata_sliceinfo {
u32 offset_in_stream;
u32 slice_length;
};
struct hfi_extradata_multislice_info_payload {
u32 num_slices;
struct hfi_extradata_sliceinfo rg_slice_info[1];
};
struct hfi_index_extradata_input_crop_payload {
u32 size;
u32 version;
u32 port_index;
u32 left;
u32 top;
u32 width;
u32 height;
};
struct hfi_index_extradata_output_crop_payload {
u32 size;
u32 version;
u32 port_index;
u32 left;
u32 top;
u32 display_width;
u32 display_height;
u32 width;
u32 height;
};
struct hfi_index_extradata_digital_zoom_payload {
u32 size;
u32 version;
u32 port_index;
int width;
int height;
};
struct hfi_index_extradata_aspect_ratio_payload {
u32 size;
u32 version;
u32 port_index;
u32 aspect_width;
u32 aspect_height;
};
struct hfi_extradata_frame_type_payload {
u32 frame_rate;
};
struct hfi_extradata_recovery_point_sei_payload {
u32 flag;
};
struct hfi_cmd_session_continue_packet {
u32 size;
u32 packet_type;
u32 session_id;
};
enum session_flags {
SESSION_PAUSE = BIT(1),
};
struct hal_session {
struct list_head list;
void *session_id;
bool is_decoder;
enum hal_video_codec codec;
enum hal_domain domain;
u32 flags;
void *device;
};
struct hal_device_data {
struct list_head dev_head;
int dev_count;
};
struct msm_vidc_fw {
void *cookie;
};
int hfi_process_msg_packet(u32 device_id, struct vidc_hal_msg_pkt_hdr *msg_hdr,
struct msm_vidc_cb_info *info);
enum vidc_status hfi_process_sys_init_done_prop_read(
struct hfi_msg_sys_init_done_packet *pkt,
struct vidc_hal_sys_init_done *sys_init_done);
enum vidc_status hfi_process_session_init_done_prop_read(
struct hfi_msg_sys_session_init_done_packet *pkt,
struct vidc_hal_session_init_done *session_init_done);
#endif

1474
drivers/media/platform/msm/vidc/vidc_hfi_api.h Normal file
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File diff suppressed because it is too large Load diff

1144
drivers/media/platform/msm/vidc/vidc_hfi_helper.h Normal file
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File diff suppressed because it is too large Load diff

198
drivers/media/platform/msm/vidc/vidc_hfi_io.h Normal file
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@ -0,0 +1,198 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __VIDC_HFI_IO_H__
#define __VIDC_HFI_IO_H__
#include <linux/io.h>
#define VIDC_VBIF_BASE_OFFS 0x00080000
#define VIDC_CPU_BASE_OFFS 0x000C0000
#define VIDEO_GCC_BASE_OFFS 0x00000000
#define VIDEO_CC_BASE_OFFS 0x00100000
#define VIDC_CPU_CS_BASE_OFFS (VIDC_CPU_BASE_OFFS + 0x00012000)
#define VIDC_CPU_IC_BASE_OFFS (VIDC_CPU_BASE_OFFS + 0x0001F000)
#define VIDC_CPU_CS_REMAP_OFFS (VIDC_CPU_CS_BASE_OFFS + 0x00)
#define VIDC_CPU_CS_TIMER_CONTROL (VIDC_CPU_CS_BASE_OFFS + 0x04)
#define VIDC_CPU_CS_A2HSOFTINTEN (VIDC_CPU_CS_BASE_OFFS + 0x10)
#define VIDC_CPU_CS_A2HSOFTINTENCLR (VIDC_CPU_CS_BASE_OFFS + 0x14)
#define VIDC_CPU_CS_A2HSOFTINT (VIDC_CPU_CS_BASE_OFFS + 0x18)
#define VIDC_CPU_CS_A2HSOFTINTCLR (VIDC_CPU_CS_BASE_OFFS + 0x1C)
#define VIDC_CPU_CS_VMIMSG (VIDC_CPU_CS_BASE_OFFS + 0x34)
#define VIDC_CPU_CS_VMIMSGAG0 (VIDC_CPU_CS_BASE_OFFS + 0x38)
#define VIDC_CPU_CS_VMIMSGAG1 (VIDC_CPU_CS_BASE_OFFS + 0x3C)
#define VIDC_CPU_CS_VMIMSGAG2 (VIDC_CPU_CS_BASE_OFFS + 0x40)
#define VIDC_CPU_CS_VMIMSGAG3 (VIDC_CPU_CS_BASE_OFFS + 0x44)
#define VIDC_CPU_CS_SCIACMD (VIDC_CPU_CS_BASE_OFFS + 0x48)
/* HFI_CTRL_STATUS */
#define VIDC_CPU_CS_SCIACMDARG0 (VIDC_CPU_CS_BASE_OFFS + 0x4C)
#define VIDC_CPU_CS_SCIACMDARG0_BMSK 0xff
#define VIDC_CPU_CS_SCIACMDARG0_SHFT 0x0
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK 0xfe
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_SHFT 0x1
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_BMSK 0x1
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_SHFT 0x0
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY 0x100
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK 0x40000000
/* HFI_QTBL_INFO */
#define VIDC_CPU_CS_SCIACMDARG1 (VIDC_CPU_CS_BASE_OFFS + 0x50)
/* HFI_QTBL_ADDR */
#define VIDC_CPU_CS_SCIACMDARG2 (VIDC_CPU_CS_BASE_OFFS + 0x54)
/* HFI_VERSION_INFO */
#define VIDC_CPU_CS_SCIACMDARG3 (VIDC_CPU_CS_BASE_OFFS + 0x58)
/* VIDC_SFR_ADDR */
#define VIDC_CPU_CS_SCIBCMD (VIDC_CPU_CS_BASE_OFFS + 0x5C)
/* VIDC_MMAP_ADDR */
#define VIDC_CPU_CS_SCIBCMDARG0 (VIDC_CPU_CS_BASE_OFFS + 0x60)
/* VIDC_UC_REGION_ADDR */
#define VIDC_CPU_CS_SCIBARG1 (VIDC_CPU_CS_BASE_OFFS + 0x64)
/* VIDC_UC_REGION_ADDR */
#define VIDC_CPU_CS_SCIBARG2 (VIDC_CPU_CS_BASE_OFFS + 0x68)
#define VIDC_CPU_CS_SCIBARG3 (VIDC_CPU_CS_BASE_OFFS + 0x6C)
#define VIDC_CPU_IC_IRQSTATUS (VIDC_CPU_IC_BASE_OFFS + 0x00)
#define VIDC_CPU_IC_FIQSTATUS (VIDC_CPU_IC_BASE_OFFS + 0x04)
#define VIDC_CPU_IC_RAWINTR (VIDC_CPU_IC_BASE_OFFS + 0x08)
#define VIDC_CPU_IC_INTSELECT (VIDC_CPU_IC_BASE_OFFS + 0x0C)
#define VIDC_CPU_IC_INTENABLE (VIDC_CPU_IC_BASE_OFFS + 0x10)
#define VIDC_CPU_IC_INTENACLEAR (VIDC_CPU_IC_BASE_OFFS + 0x14)
#define VIDC_CPU_IC_SOFTINT (VIDC_CPU_IC_BASE_OFFS + 0x18)
#define VIDC_CPU_IC_SOFTINT_H2A_BMSK 0x8000
#define VIDC_CPU_IC_SOFTINT_H2A_SHFT 0xF
#define VIDC_CPU_IC_SOFTINTCLEAR (VIDC_CPU_IC_BASE_OFFS + 0x1C)
/*
* --------------------------------------------------------------------------
* MODULE: vidc_wrapper
* --------------------------------------------------------------------------
*/
#define VIDC_WRAPPER_BASE_OFFS 0x000E0000
#define VIDC_WRAPPER_HW_VERSION (VIDC_WRAPPER_BASE_OFFS + 0x00)
#define VIDC_WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x78000000
#define VIDC_WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 28
#define VIDC_WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xFFF0000
#define VIDC_WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 16
#define VIDC_WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xFFFF
#define VIDC_WRAPPER_CLOCK_CONFIG (VIDC_WRAPPER_BASE_OFFS + 0x04)
#define VIDC_WRAPPER_INTR_STATUS (VIDC_WRAPPER_BASE_OFFS + 0x0C)
#define VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10
#define VIDC_WRAPPER_INTR_STATUS_A2HWD_SHFT 0x4
#define VIDC_WRAPPER_INTR_STATUS_A2H_BMSK 0x4
#define VIDC_WRAPPER_INTR_STATUS_A2H_SHFT 0x2
#define VIDC_WRAPPER_INTR_MASK (VIDC_WRAPPER_BASE_OFFS + 0x10)
#define VIDC_WRAPPER_INTR_MASK_A2HWD_BMSK 0x10
#define VIDC_WRAPPER_INTR_MASK_A2HWD_SHFT 0x4
#define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK 0x8
#define VIDC_WRAPPER_INTR_MASK_A2HCPU_BMSK 0x4
#define VIDC_WRAPPER_INTR_MASK_A2HCPU_SHFT 0x2
#define VIDC_WRAPPER_INTR_CLEAR (VIDC_WRAPPER_BASE_OFFS + 0x14)
#define VIDC_WRAPPER_INTR_CLEAR_A2HWD_BMSK 0x10
#define VIDC_WRAPPER_INTR_CLEAR_A2HWD_SHFT 0x4
#define VIDC_WRAPPER_INTR_CLEAR_A2H_BMSK 0x4
#define VIDC_WRAPPER_INTR_CLEAR_A2H_SHFT 0x2
#define VIDC_WRAPPER_CPU_CLOCK_CONFIG (VIDC_WRAPPER_BASE_OFFS + 0x2000)
#define VIDC_WRAPPER_CPU_CGC_DIS (VIDC_WRAPPER_BASE_OFFS + 0x2010)
#define VIDC_WRAPPER_CPU_STATUS (VIDC_WRAPPER_BASE_OFFS + 0x2014)
#define VIDC_VENUS_VBIF_CLK_ON (VIDC_VBIF_BASE_OFFS + 0x4)
#define VENUS_VBIF_AXI_HALT_CTRL0 (VIDC_VBIF_BASE_OFFS + 0x208)
#define VENUS_VBIF_AXI_HALT_CTRL1 (VIDC_VBIF_BASE_OFFS + 0x20C)
#define VENUS_VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
#define VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
#define VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US 500000
#define VIDC_CTRL_INIT VIDC_CPU_CS_SCIACMD
#define VIDC_CTRL_STATUS VIDC_CPU_CS_SCIACMDARG0
#define VIDC_CTRL_ERROR_STATUS__M \
VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK
#define VIDC_CTRL_INIT_IDLE_MSG_BMSK \
VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK
#define VIDC_CTRL_STATUS_PC_READY \
VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY
#define VIDC_QTBL_INFO VIDC_CPU_CS_SCIACMDARG1
#define VIDC_QTBL_ADDR VIDC_CPU_CS_SCIACMDARG2
#define VIDC_VERSION_INFO VIDC_CPU_CS_SCIACMDARG3
#define VIDC_SFR_ADDR VIDC_CPU_CS_SCIBCMD
#define VIDC_MMAP_ADDR VIDC_CPU_CS_SCIBCMDARG0
#define VIDC_UC_REGION_ADDR VIDC_CPU_CS_SCIBARG1
#define VIDC_UC_REGION_SIZE VIDC_CPU_CS_SCIBARG2
/* HFI_DSP_QTBL_ADDR
* 31:3 - HFI_DSP_QTBL_ADDR
* 4-byte aligned Address
*/
#define HFI_DSP_QTBL_ADDR VIDC_CPU_CS_VMIMSG
/* HFI_DSP_UC_REGION_ADDR
* 31:20 - HFI_DSP_UC_REGION_ADDR
* 1MB aligned address.
* Uncached Region start Address. This region covers
* HFI DSP QTable,
* HFI DSP Queue Headers,
* HFI DSP Queues,
*/
#define HFI_DSP_UC_REGION_ADDR VIDC_CPU_CS_VMIMSGAG0
/* HFI_DSP_UC_REGION_SIZE
* 31:20 - HFI_DSP_UC_REGION_SIZE
* Multiples of 1MB.
* Size of the DSP_UC_REGION Uncached Region
*/
#define HFI_DSP_UC_REGION_SIZE VIDC_CPU_CS_VMIMSGAG1
/*
* --------------------------------------------------------------------------
* MODULE: vcodec noc error log registers
* --------------------------------------------------------------------------
*/
#define VCODEC_CORE0_VIDEO_NOC_BASE_OFFS 0x00004000
#define VCODEC_CORE1_VIDEO_NOC_BASE_OFFS 0x0000C000
#define VCODEC_COREX_VIDEO_NOC_ERR_SWID_LOW_OFFS 0x0500
#define VCODEC_COREX_VIDEO_NOC_ERR_SWID_HIGH_OFFS 0x0504
#define VCODEC_COREX_VIDEO_NOC_ERR_MAINCTL_LOW_OFFS 0x0508
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRVLD_LOW_OFFS 0x0510
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRCLR_LOW_OFFS 0x0518
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG0_LOW_OFFS 0x0520
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG0_HIGH_OFFS 0x0524
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG1_LOW_OFFS 0x0528
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG1_HIGH_OFFS 0x052C
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG2_LOW_OFFS 0x0530
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG2_HIGH_OFFS 0x0534
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG3_LOW_OFFS 0x0538
#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG3_HIGH_OFFS 0x053C
#define VIDEO_GCC_AXIC_CBCR (VIDEO_GCC_BASE_OFFS + 0x8)
#define VIDEO_GCC_AXIC_CBCR_CLK_OFF_BMSK 0x80000000
#define VIDEO_GCC_AXIC_CBCR_CLK_ARES_BMSK 0x4
#define VIDEO_GCC_AXIC_CBCR_CLK_ENABLE_BMSK 0x1
#define VIDEO_CC_MVSC_CORE_CBCR (VIDEO_CC_BASE_OFFS + 0x850)
#define VIDEO_CC_MVSC_CORE_CBCR_CLK_OFF_BMSK 0x80000000
#define VIDEO_CC_MVSC_CORE_CBCR_CLK_ARES_BMSK 0x4
#define VIDEO_CC_MVSC_CORE_CBCR_CLK_ENABLE_BMSK 0x1
#endif

6
drivers/media/v4l2-core/v4l2-ctrls.c
View file

@ -338,6 +338,11 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
"4.2",
"5",
"5.1",
"5.2",
"6",
"6.1",
"6.2",
"Unknown",
NULL,
};
static const char * const h264_loop_filter[] = {
@ -514,6 +519,7 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
"6",
"6.1",
"6.2",
"Unknown",
NULL,
};
static const char * const hevc_hierarchial_coding_type[] = {

80
include/linux/fastcvpd.h Normal file
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@ -0,0 +1,80 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef FASTCVPD_H
#define FASTCVPD_H
#include <linux/types.h>
#define FASTCVPD_GLINK_GUID "fastcvpd-glink-apps-dsp"
#define FASTCVPD_SMD_GUID "fastcvpd-smd-apps-dsp"
#define FASTCVPD_DEVICE_NAME "fastcvpd-smd"
#ifdef CONFIG_MSM_FASTCVPD
/*
* API for Video driver to send physical address to FastCVP driver
* @param phys_addr
* Physical address of command message queue
* that needs to be mapped to CDSP.
* It should be allocated from CMA adsp_mem region.
*
* @param size_in_bytes
* Size in bytes of command message queue
*/
int fastcvpd_video_send_cmd_hfi_queue(phys_addr_t *phys_addr,
uint32_t size_in_bytes);
/*
* API for Video driver to suspend CVP session during
* power collapse
*
* @param session_flag
* Flag to share details of session.
*/
int fastcvpd_video_suspend(uint32_t session_flag);
/*
* API for Video driver to resume CVP session during
* power collapse
*
* @param session_flag
* Flag to share details of session.
*/
int fastcvpd_video_resume(uint32_t session_flag);
/*
* API for Video driver to shutdown CVP session during
* video subsystem error.
*
* @param session_flag
* Flag to share details of session.
*/
int fastcvpd_video_shutdown(uint32_t session_flag);
#else
static inline int fastcvpd_video_send_cmd_hfi_queue(
phys_addr_t *phys_addr,
uint32_t size_in_bytes)
{
return -ENODEV;
}
static inline int fastcvpd_video_shutdown(uint32_t session_flag)
{
return -ENODEV;
}
static inline int fastcvpd_video_suspend(uint32_t session_flag)
{
return -ENODEV;
}
static inline int fastcvpd_video_resume(uint32_t session_flag)
{
return -ENODEV;
}
#endif // CONFIG_FASTCVPD
#endif // FASTCVPD_H

2
include/media/videobuf2-core.h
View file

@ -18,7 +18,7 @@
#include <linux/dma-buf.h>
#include <linux/bitops.h>
#define VB2_MAX_FRAME (32)
#define VB2_MAX_FRAME (64)
#define VB2_MAX_PLANES (8)
/**

340
include/trace/events/msm_vidc_events.h Normal file
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@ -0,0 +1,340 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM msm_vidc_events
#if !defined(_TRACE_MSM_VIDC_H_) || defined(TRACE_HEADER_MULTI_READ)
#define _TRACE_MSM_VIDC_H
#include <linux/types.h>
#include <linux/tracepoint.h>
DECLARE_EVENT_CLASS(msm_v4l2_vidc,
TP_PROTO(char *dummy),
TP_ARGS(dummy),
TP_STRUCT__entry(
__field(char *, dummy)
),
TP_fast_assign(
__entry->dummy = dummy;
),
TP_printk("%s", __entry->dummy)
);
DEFINE_EVENT(msm_v4l2_vidc, msm_v4l2_vidc_open_start,
TP_PROTO(char *dummy),
TP_ARGS(dummy)
);
DEFINE_EVENT(msm_v4l2_vidc, msm_v4l2_vidc_open_end,
TP_PROTO(char *dummy),
TP_ARGS(dummy)
);
DEFINE_EVENT(msm_v4l2_vidc, msm_v4l2_vidc_close_start,
TP_PROTO(char *dummy),
TP_ARGS(dummy)
);
DEFINE_EVENT(msm_v4l2_vidc, msm_v4l2_vidc_close_end,
TP_PROTO(char *dummy),
TP_ARGS(dummy)
);
DEFINE_EVENT(msm_v4l2_vidc, msm_v4l2_vidc_fw_load_start,
TP_PROTO(char *dummy),
TP_ARGS(dummy)
);
DEFINE_EVENT(msm_v4l2_vidc, msm_v4l2_vidc_fw_load_end,
TP_PROTO(char *dummy),
TP_ARGS(dummy)
);
DECLARE_EVENT_CLASS(msm_vidc_common,
TP_PROTO(void *instp, int old_state, int new_state),
TP_ARGS(instp, old_state, new_state),
TP_STRUCT__entry(
__field(void *, instp)
__field(int, old_state)
__field(int, new_state)
),
TP_fast_assign(
__entry->instp = instp;
__entry->old_state = old_state;
__entry->new_state = new_state;
),
TP_printk("Moved inst: %p from 0x%x to 0x%x",
__entry->instp,
__entry->old_state,
__entry->new_state)
);
DEFINE_EVENT(msm_vidc_common, msm_vidc_common_state_change,
TP_PROTO(void *instp, int old_state, int new_state),
TP_ARGS(instp, old_state, new_state)
);
DECLARE_EVENT_CLASS(venus_hfi_var,
TP_PROTO(u32 cp_start, u32 cp_size,
u32 cp_nonpixel_start, u32 cp_nonpixel_size),
TP_ARGS(cp_start, cp_size, cp_nonpixel_start, cp_nonpixel_size),
TP_STRUCT__entry(
__field(u32, cp_start)
__field(u32, cp_size)
__field(u32, cp_nonpixel_start)
__field(u32, cp_nonpixel_size)
),
TP_fast_assign(
__entry->cp_start = cp_start;
__entry->cp_size = cp_size;
__entry->cp_nonpixel_start = cp_nonpixel_start;
__entry->cp_nonpixel_size = cp_nonpixel_size;
),
TP_printk(
"TZBSP_MEM_PROTECT_VIDEO_VAR done, cp_start : 0x%x, cp_size : 0x%x, cp_nonpixel_start : 0x%x, cp_nonpixel_size : 0x%x",
__entry->cp_start,
__entry->cp_size,
__entry->cp_nonpixel_start,
__entry->cp_nonpixel_size)
);
DEFINE_EVENT(venus_hfi_var, venus_hfi_var_done,
TP_PROTO(u32 cp_start, u32 cp_size,
u32 cp_nonpixel_start, u32 cp_nonpixel_size),
TP_ARGS(cp_start, cp_size, cp_nonpixel_start, cp_nonpixel_size)
);
DECLARE_EVENT_CLASS(msm_v4l2_vidc_buffer_events,
TP_PROTO(char *event_type, u32 device_addr, int64_t timestamp,
u32 alloc_len, u32 filled_len, u32 offset),
TP_ARGS(event_type, device_addr, timestamp, alloc_len,
filled_len, offset),
TP_STRUCT__entry(
__field(char *, event_type)
__field(u32, device_addr)
__field(int64_t, timestamp)
__field(u32, alloc_len)
__field(u32, filled_len)
__field(u32, offset)
),
TP_fast_assign(
__entry->event_type = event_type;
__entry->device_addr = device_addr;
__entry->timestamp = timestamp;
__entry->alloc_len = alloc_len;
__entry->filled_len = filled_len;
__entry->offset = offset;
),
TP_printk(
"%s, device_addr : 0x%x, timestamp : %lld, alloc_len : 0x%x, filled_len : 0x%x, offset : 0x%x",
__entry->event_type,
__entry->device_addr,
__entry->timestamp,
__entry->alloc_len,
__entry->filled_len,
__entry->offset)
);
DEFINE_EVENT(msm_v4l2_vidc_buffer_events, msm_v4l2_vidc_buffer_event_start,
TP_PROTO(char *event_type, u32 device_addr, int64_t timestamp,
u32 alloc_len, u32 filled_len, u32 offset),
TP_ARGS(event_type, device_addr, timestamp, alloc_len,
filled_len, offset)
);
DEFINE_EVENT(msm_v4l2_vidc_buffer_events, msm_v4l2_vidc_buffer_event_end,
TP_PROTO(char *event_type, u32 device_addr, int64_t timestamp,
u32 alloc_len, u32 filled_len, u32 offset),
TP_ARGS(event_type, device_addr, timestamp, alloc_len,
filled_len, offset)
);
DECLARE_EVENT_CLASS(msm_smem_buffer_dma_ops,
TP_PROTO(char *buffer_op, u32 buffer_type, u32 heap_mask,
size_t size, u32 align, u32 flags, int map_kernel),
TP_ARGS(buffer_op, buffer_type, heap_mask, size, align,
flags, map_kernel),
TP_STRUCT__entry(
__field(char *, buffer_op)
__field(u32, buffer_type)
__field(u32, heap_mask)
__field(u32, size)
__field(u32, align)
__field(u32, flags)
__field(int, map_kernel)
),
TP_fast_assign(
__entry->buffer_op = buffer_op;
__entry->buffer_type = buffer_type;
__entry->heap_mask = heap_mask;
__entry->size = size;
__entry->align = align;
__entry->flags = flags;
__entry->map_kernel = map_kernel;
),
TP_printk(
"%s, buffer_type : 0x%x, heap_mask : 0x%x, size : 0x%x, align : 0x%x, flags : 0x%x, map_kernel : %d",
__entry->buffer_op,
__entry->buffer_type,
__entry->heap_mask,
__entry->size,
__entry->align,
__entry->flags,
__entry->map_kernel)
);
DEFINE_EVENT(msm_smem_buffer_dma_ops, msm_smem_buffer_dma_op_start,
TP_PROTO(char *buffer_op, u32 buffer_type, u32 heap_mask,
size_t size, u32 align, u32 flags, int map_kernel),
TP_ARGS(buffer_op, buffer_type, heap_mask, size, align,
flags, map_kernel)
);
DEFINE_EVENT(msm_smem_buffer_dma_ops, msm_smem_buffer_dma_op_end,
TP_PROTO(char *buffer_op, u32 buffer_type, u32 heap_mask,
size_t size, u32 align, u32 flags, int map_kernel),
TP_ARGS(buffer_op, buffer_type, heap_mask, size, align,
flags, map_kernel)
);
DECLARE_EVENT_CLASS(msm_smem_buffer_iommu_ops,
TP_PROTO(char *buffer_op, int domain_num, int partition_num,
unsigned long align, unsigned long iova,
unsigned long buffer_size),
TP_ARGS(buffer_op, domain_num, partition_num, align, iova, buffer_size),
TP_STRUCT__entry(
__field(char *, buffer_op)
__field(int, domain_num)
__field(int, partition_num)
__field(unsigned long, align)
__field(unsigned long, iova)
__field(unsigned long, buffer_size)
),
TP_fast_assign(
__entry->buffer_op = buffer_op;
__entry->domain_num = domain_num;
__entry->partition_num = partition_num;
__entry->align = align;
__entry->iova = iova;
__entry->buffer_size = buffer_size;
),
TP_printk(
"%s, domain : %d, partition : %d, align : %lx, iova : 0x%lx, buffer_size=%lx",
__entry->buffer_op,
__entry->domain_num,
__entry->partition_num,
__entry->align,
__entry->iova,
__entry->buffer_size)
);
DEFINE_EVENT(msm_smem_buffer_iommu_ops, msm_smem_buffer_iommu_op_start,
TP_PROTO(char *buffer_op, int domain_num, int partition_num,
unsigned long align, unsigned long iova,
unsigned long buffer_size),
TP_ARGS(buffer_op, domain_num, partition_num, align, iova, buffer_size)
);
DEFINE_EVENT(msm_smem_buffer_iommu_ops, msm_smem_buffer_iommu_op_end,
TP_PROTO(char *buffer_op, int domain_num, int partition_num,
unsigned long align, unsigned long iova,
unsigned long buffer_size),
TP_ARGS(buffer_op, domain_num, partition_num, align, iova, buffer_size)
);
DECLARE_EVENT_CLASS(msm_vidc_perf,
TP_PROTO(const char *name, unsigned long value),
TP_ARGS(name, value),
TP_STRUCT__entry(
__field(const char *, name)
__field(unsigned long, value)
),
TP_fast_assign(
__entry->name = name;
__entry->value = value;
),
TP_printk("%s %lu", __entry->name, __entry->value)
);
DEFINE_EVENT(msm_vidc_perf, msm_vidc_perf_clock_scale,
TP_PROTO(const char *clock_name, unsigned long frequency),
TP_ARGS(clock_name, frequency)
);
DEFINE_EVENT(msm_vidc_perf, msm_vidc_perf_bus_vote,
TP_PROTO(const char *governor_mode, unsigned long ab),
TP_ARGS(governor_mode, ab)
);
#endif
#include <trace/define_trace.h>

165
include/uapi/linux/v4l2-controls.h
View file

@ -365,8 +365,14 @@ enum v4l2_mpeg_video_aspect {
#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205)
#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206)
enum v4l2_mpeg_video_bitrate_mode {
/* CFR Modes */
V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0,
V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1,
V4L2_MPEG_VIDEO_BITRATE_MODE_MBR = 2,
/* VFR Modes */
V4L2_MPEG_VIDEO_BITRATE_MODE_CBR_VFR = 3,
V4L2_MPEG_VIDEO_BITRATE_MODE_MBR_VFR = 4,
V4L2_MPEG_VIDEO_BITRATE_MODE_CQ = 5,
};
#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207)
#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208)
@ -438,6 +444,11 @@ enum v4l2_mpeg_video_h264_level {
V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13,
V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14,
V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15,
V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16,
V4L2_MPEG_VIDEO_H264_LEVEL_6_0 = 17,
V4L2_MPEG_VIDEO_H264_LEVEL_6_1 = 18,
V4L2_MPEG_VIDEO_H264_LEVEL_6_2 = 19,
V4L2_MPEG_VIDEO_H264_LEVEL_UNKNOWN = 20,
};
#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360)
#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361)
@ -466,6 +477,7 @@ enum v4l2_mpeg_video_h264_profile {
V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14,
V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15,
V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16,
V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17,
};
#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364)
#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365)
@ -633,6 +645,7 @@ enum v4l2_mpeg_video_hevc_profile {
V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10 = 2,
};
#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL (V4L2_CID_MPEG_BASE + 616)
enum v4l2_mpeg_video_hevc_level {
V4L2_MPEG_VIDEO_HEVC_LEVEL_1 = 0,
V4L2_MPEG_VIDEO_HEVC_LEVEL_2 = 1,
@ -647,7 +660,9 @@ enum v4l2_mpeg_video_hevc_level {
V4L2_MPEG_VIDEO_HEVC_LEVEL_6 = 10,
V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1 = 11,
V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2 = 12,
V4L2_MPEG_VIDEO_HEVC_LEVEL_UNKNOWN = 13,
};
#define V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION (V4L2_CID_MPEG_BASE + 617)
#define V4L2_CID_MPEG_VIDEO_HEVC_TIER (V4L2_CID_MPEG_BASE + 618)
enum v4l2_mpeg_video_hevc_tier {
@ -765,6 +780,156 @@ enum v4l2_mpeg_mfc51_video_force_frame_type {
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53)
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54)
/* MPEG-class control IDs specific to the msm_vidc driver */
#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000)
#define V4L2_MPEG_MSM_VIDC_DISABLE 0
#define V4L2_MPEG_MSM_VIDC_ENABLE 1
#define V4L2_CID_MPEG_VIDC_VIDEO_PICTYPE_DEC_MODE \
(V4L2_CID_MPEG_MSM_VIDC_BASE+0)
enum v4l2_mpeg_vidc_video_pictype_dec_mode {
V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_I = 1,
V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_P = 2,
V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_B = 4,
};
#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+2)
enum v4l2_mpeg_vidc_video_stream_format {
V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0,
V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4,
};
#define V4L2_CID_MPEG_VIDC_VIDEO_DECODE_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+3)
#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM \
(V4L2_CID_MPEG_MSM_VIDC_BASE+13)
#define V4L2_CID_MPEG_VIDC_VIDEO_AU_DELIMITER \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 14)
#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 15)
#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+16)
#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 17)
enum v4l2_mpeg_vidc_extradata {
EXTRADATA_DEFAULT = 1,
EXTRADATA_ADVANCED = 2,
EXTRADATA_ENC_INPUT_ROI = 4,
EXTRADATA_ENC_INPUT_HDR10PLUS = 8,
};
#define V4L2_CID_MPEG_VIDC_VIDEO_VUI_TIMING_INFO \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 19)
#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 20)
enum v4l2_mpeg_vidc_video_vp8_profile_level {
V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED,
V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0,
V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1,
V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2,
V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3,
};
#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+23)
enum v4l2_mpeg_vidc_video_mpeg2_level {
V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_0 = 0,
V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_1 = 1,
V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_2 = 2,
V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_3 = 3,
};
#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+24)
enum v4l2_mpeg_vidc_video_mpeg2_profile {
V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SIMPLE = 0,
V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_MAIN = 1,
V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_HIGH = 2,
};
#define V4L2_CID_MPEG_VIDC_VIDEO_LTRCOUNT \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 27)
#define V4L2_CID_MPEG_VIDC_VIDEO_USELTRFRAME \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 28)
#define V4L2_CID_MPEG_VIDC_VIDEO_MARKLTRFRAME \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 29)
#define V4L2_CID_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 38)
#define V4L2_CID_MPEG_VIDC_VIDEO_BUFFER_SIZE_LIMIT \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 39)
#define V4L2_CID_MPEG_VIDC_VIDEO_BASELAYER_ID \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 47)
#define V4L2_CID_MPEG_VIDC_VIDEO_PRIORITY \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 52)
#define V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 53)
#define V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 55)
#define V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_MODE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 56)
#define V4L2_CID_MPEG_VIDC_VIDEO_BLUR_DIMENSIONS \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 57)
#define V4L2_CID_MPEG_VIDC_VIDEO_COLOR_SPACE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 60)
#define V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 61)
#define V4L2_CID_MPEG_VIDC_VIDEO_TRANSFER_CHARS \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 62)
#define V4L2_CID_MPEG_VIDC_VIDEO_MATRIX_COEFFS \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 63)
#define V4L2_CID_MPEG_VIDC_VIDEO_VP9_LEVEL \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 67)
enum v4l2_mpeg_vidc_video_vp9_level {
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_UNUSED = 0,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_1 = 1,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_11 = 2,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_2 = 3,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_21 = 4,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_3 = 5,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_31 = 6,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_4 = 7,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_41 = 8,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_5 = 9,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_51 = 10,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_6 = 11,
V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_61 = 12,
};
#define V4L2_CID_MPEG_VIDC_VIDEO_DYN_QP \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 108)
#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR_8BIT \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 109)
#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR_10BIT \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 110)
#define V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_CUSTOM_MATRIX \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 114)
#define V4L2_CID_MPEG_VIDC_VENC_HDR_INFO \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 116)
#define V4L2_CID_MPEG_VIDC_IMG_GRID_SIZE \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 117)
#define V4L2_CID_MPEG_VIDC_COMPRESSION_QUALITY \
(V4L2_CID_MPEG_MSM_VIDC_BASE + 118)
/* Camera class control IDs */
#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)

55
include/uapi/linux/videodev2.h
View file

@ -70,7 +70,7 @@
* Common stuff for both V4L1 and V4L2
* Moved from videodev.h
*/
#define VIDEO_MAX_FRAME 32
#define VIDEO_MAX_FRAME 64
#define VIDEO_MAX_PLANES 8
/*
@ -510,6 +510,7 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */
#define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') /* 32 ARGB-8-8-8-8 */
#define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */
#define V4L2_PIX_FMT_RGBA8888_UBWC v4l2_fourcc('Q', 'R', 'G', 'B')
/* Grey formats */
#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */
@ -553,6 +554,15 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
/* NV12_512 8-bit Y/CbCr 4:2:0 */
#define V4L2_PIX_FMT_NV12_512 v4l2_fourcc('Q', '5', '1', '2')
/* UBWC 8-bit Y/CbCr 4:2:0 */
#define V4L2_PIX_FMT_NV12_UBWC v4l2_fourcc('Q', '1', '2', '8')
/* UBWC 10-bit Y/CbCr 4:2:0 */
#define V4L2_PIX_FMT_NV12_TP10_UBWC v4l2_fourcc('Q', '1', '2', 'A')
#define V4L2_PIX_FMT_NV12_P010_UBWC v4l2_fourcc('Q', '1', '2', 'B')
/* two non contiguous planes - one Y, one Cr + Cb interleaved */
#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */
@ -643,6 +653,8 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */
#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */
#define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */
#define V4L2_PIX_FMT_TME v4l2_fourcc('T', 'M', 'E', '0') /* TME stream */
#define V4L2_PIX_FMT_CVP v4l2_fourcc('C', 'V', 'P', '0') /* CVP stream */
/* Vendor-specific formats */
#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */
@ -682,6 +694,8 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_IPU3_SGBRG10 v4l2_fourcc('i', 'p', '3', 'g') /* IPU3 packed 10-bit GBRG bayer */
#define V4L2_PIX_FMT_IPU3_SGRBG10 v4l2_fourcc('i', 'p', '3', 'G') /* IPU3 packed 10-bit GRBG bayer */
#define V4L2_PIX_FMT_IPU3_SRGGB10 v4l2_fourcc('i', 'p', '3', 'r') /* IPU3 packed 10-bit RGGB bayer */
#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS \
v4l2_fourcc('Q', 'P', '1', '0') /* Y/CbCr 4:2:0 P10 Venus*/
/* SDR formats - used only for Software Defined Radio devices */
#define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') /* IQ u8 */
@ -977,6 +991,13 @@ struct v4l2_buffer {
#define V4L2_BUF_FLAG_TSTAMP_SRC_SOE 0x00010000
/* mem2mem encoder/decoder */
#define V4L2_BUF_FLAG_LAST 0x00100000
/* Vendor extensions */
#define V4L2_BUF_FLAG_CODECCONFIG 0x00020000
#define V4L2_BUF_FLAG_DATA_CORRUPT 0x00400000
#define V4L2_BUF_INPUT_UNSUPPORTED 0x01000000
#define V4L2_BUF_FLAG_EOS 0x02000000
#define V4L2_BUF_FLAG_READONLY 0x04000000
#define V4L2_BUF_FLAG_PERF_MODE 0x20000000
/**
* struct v4l2_exportbuffer - export of video buffer as DMABUF file descriptor
@ -1838,7 +1859,6 @@ struct v4l2_audioout {
/*
* M P E G S E R V I C E S
*/
#if 1
#define V4L2_ENC_IDX_FRAME_I (0)
#define V4L2_ENC_IDX_FRAME_P (1)
#define V4L2_ENC_IDX_FRAME_B (2)
@ -1884,7 +1904,8 @@ struct v4l2_encoder_cmd {
#define V4L2_DEC_CMD_STOP (1)
#define V4L2_DEC_CMD_PAUSE (2)
#define V4L2_DEC_CMD_RESUME (3)
#define V4L2_CMD_FLUSH (4)
#define V4L2_CMD_SESSION_CONTINUE (5)
/* Flags for V4L2_DEC_CMD_START */
#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0)
@ -1895,6 +1916,10 @@ struct v4l2_encoder_cmd {
#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0)
#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1)
/* Flags for V4L2_CMD_FLUSH */
#define V4L2_CMD_FLUSH_OUTPUT (1 << 0)
#define V4L2_CMD_FLUSH_CAPTURE (1 << 1)
/* Play format requirements (returned by the driver): */
/* The decoder has no special format requirements */
@ -1927,7 +1952,6 @@ struct v4l2_decoder_cmd {
} raw;
};
};
#endif
/*
@ -2174,6 +2198,26 @@ struct v4l2_streamparm {
#define V4L2_EVENT_MOTION_DET 6
#define V4L2_EVENT_PRIVATE_START 0x08000000
#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000)
#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1)
#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT \
(V4L2_EVENT_MSM_VIDC_START + 2)
#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT \
(V4L2_EVENT_MSM_VIDC_START + 3)
#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5)
#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE \
(V4L2_EVENT_MSM_VIDC_START + 6)
#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER \
(V4L2_EVENT_MSM_VIDC_START + 7)
#define V4L2_EVENT_MSM_VIDC_HW_OVERLOAD (V4L2_EVENT_MSM_VIDC_START + 8)
#define V4L2_EVENT_MSM_VIDC_MAX_CLIENTS (V4L2_EVENT_MSM_VIDC_START + 9)
#define V4L2_EVENT_MSM_VIDC_HW_UNSUPPORTED (V4L2_EVENT_MSM_VIDC_START + 10)
#define V4L2_EVENT_MSM_VIDC_REGISTER_BUFFER_DONE \
(V4L2_EVENT_MSM_VIDC_START + 11)
#define V4L2_EVENT_MSM_VIDC_UNREGISTER_BUFFER_DONE \
(V4L2_EVENT_MSM_VIDC_START + 12)
/* Payload for V4L2_EVENT_VSYNC */
struct v4l2_event_vsync {
/* Can be V4L2_FIELD_ANY, _NONE, _TOP or _BOTTOM */
@ -2417,4 +2461,7 @@ struct v4l2_create_buffers {
#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */
/* (BASE_VIDIOC_PRIVATE + 0) is private ioctl code for video module */
#define BASE_VIDIOC_PRIVATE_VIDEO (BASE_VIDIOC_PRIVATE + 0)
#endif /* _UAPI__LINUX_VIDEODEV2_H */

123
include/uapi/media/msm_vidc_private.h Normal file
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@ -0,0 +1,123 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __MSM_VIDC_PRIVATE_H__
#define __MSM_VIDC_PRIVATE_H__
#include <linux/videodev2.h>
/* VIDIOC private video command */
#define VIDIOC_VIDEO_CMD \
_IOWR('V', BASE_VIDIOC_PRIVATE_VIDEO, struct msm_vidc_arg)
/* Commands type */
#define MSM_VIDC_CMD_START 0x10000000
#define MSM_CVP_START (MSM_VIDC_CMD_START + 0x1000)
/*
* userspace clients pass one of the below arguments type
* in struct msm_vidc_arg (@type field).
*/
/*
* MSM_CVP_GET_SESSION_INFO - this argument type is used to
* get the session information from driver. it passes
* struct msm_cvp_session_info {}
*/
#define MSM_CVP_GET_SESSION_INFO (MSM_CVP_START + 1)
/*
* MSM_CVP_REQUEST_POWER - this argument type is used to
* set the power required to driver. it passes
* struct msm_cvp_request_power {}
*/
#define MSM_CVP_REQUEST_POWER (MSM_CVP_START + 2)
/*
* MSM_CVP_REGISTER_BUFFER - this argument type is used to
* register the buffer to driver. it passes
* struct msm_cvp_buffer {}
*/
#define MSM_CVP_REGISTER_BUFFER (MSM_CVP_START + 3)
/*
* MSM_CVP_REGISTER_BUFFER - this argument type is used to
* unregister the buffer to driver. it passes
* struct msm_cvp_buffer {}
*/
#define MSM_CVP_UNREGISTER_BUFFER (MSM_CVP_START + 4)
/* flags */
#define MSM_CVP_FLAG_UNSECURE 0x00000000
#define MSM_CVP_FLAG_SECURE 0x00000001
/* buffer type */
#define MSM_CVP_BUFTYPE_INPUT 0x00000001
#define MSM_CVP_BUFTYPE_OUTPUT 0x00000002
#define MSM_CVP_BUFTYPE_INTERNAL_1 0x00000003
#define MSM_CVP_BUFTYPE_INTERNAL_2 0x00000004
/**
* struct msm_cvp_session_info - session information
* @session_id: current session id
*/
struct msm_cvp_session_info {
unsigned int session_id;
unsigned int reserved[10];
};
/**
* struct msm_cvp_request_power - power / clock data information
* @clock_cycles_a: clock cycles per second required for hardware_a
* @clock_cycles_b: clock cycles per second required for hardware_b
* @ddr_bw: bandwidth required for ddr in bps
* @sys_cache_bw: bandwidth required for system cache in bps
*/
struct msm_cvp_request_power {
unsigned int clock_cycles_a;
unsigned int clock_cycles_b;
unsigned int ddr_bw;
unsigned int sys_cache_bw;
unsigned int reserved[8];
};
/**
* struct msm_cvp_buffer - buffer information to be registered
* @index: index of buffer
* @type: buffer type
* @fd: file descriptor of buffer
* @size: allocated size of buffer
* @offset: offset in fd from where usable data starts
* @pixelformat: fourcc format
* @flags: buffer flags
*/
struct msm_cvp_buffer {
unsigned int index;
unsigned int type;
unsigned int fd;
unsigned int size;
unsigned int offset;
unsigned int pixelformat;
unsigned int flags;
unsigned int reserved[5];
};
/**
* struct msm_vidc_arg - argument passed with VIDIOC_VIDEO_CMD
* @type: command type
* @session: session information
* @req_power: power information
* @regbuf: buffer to be registered
* @unregbuf: buffer to be unregistered
*/
struct msm_vidc_arg {
unsigned int type;
union data_t {
struct msm_cvp_session_info session;
struct msm_cvp_request_power req_power;
struct msm_cvp_buffer regbuf;
struct msm_cvp_buffer unregbuf;
} data;
unsigned int reserved[12];
};
#endif

336
include/uapi/media/msm_vidc_utils.h Normal file
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@ -0,0 +1,336 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __MSM_VIDC_UTILS_H__
#define __MSM_VIDC_UTILS_H__
#include <linux/types.h>
#define MSM_VIDC_EXTRADATA_NONE 0x00000000
struct msm_vidc_extradata_header {
__u32 size;
__u32 version; /** Keeping binary compatibility */
__u32 port_index; /* with firmware and OpenMAX IL **/
__u32 type; /* msm_vidc_extradata_type */
__u32 data_size;
__u32 data[1];
};
/* msm_vidc_interlace_type */
#define MSM_VIDC_INTERLACE_FRAME_PROGRESSIVE 0x01
#define MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST 0x02
#define MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST 0x04
#define MSM_VIDC_INTERLACE_FRAME_TOPFIELDFIRST 0x08
#define MSM_VIDC_INTERLACE_FRAME_BOTTOMFIELDFIRST 0x10
#define MSM_VIDC_INTERLACE_FRAME_MBAFF 0x20
/* Color formats */
#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12 0x2
#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12_UBWC 0x8002
#define MSM_VIDC_EXTRADATA_INTERLACE_VIDEO 0x00000002
struct msm_vidc_interlace_payload {
__u32 format; /* Interlace format */
__u32 color_format;
};
#define MSM_VIDC_EXTRADATA_FRAME_RATE 0x00000007
struct msm_vidc_framerate_payload {
__u32 frame_rate; /*In Q16 format */
};
#define MSM_VIDC_EXTRADATA_TIMESTAMP 0x00000005
struct msm_vidc_ts_payload {
__u32 timestamp_lo;
__u32 timestamp_hi;
};
#define MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB 0x7F100001
struct msm_vidc_concealmb_payload {
__u32 num_mbs;
};
#define MSM_VIDC_FRAME_RECONSTRUCTION_INCORRECT 0x0
#define MSM_VIDC_FRAME_RECONSTRUCTION_CORRECT 0x01
#define MSM_VIDC_FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT 0x02
#define MSM_VIDC_EXTRADATA_RECOVERY_POINT_SEI 0x00000009
struct msm_vidc_recoverysei_payload {
__u32 flags;
};
#define MSM_VIDC_EXTRADATA_ASPECT_RATIO 0x7F100003
struct msm_vidc_aspect_ratio_payload {
__u32 size;
__u32 version;
__u32 port_index;
__u32 aspect_width;
__u32 aspect_height;
};
struct msm_vidc_misr_info {
__u32 misr_set;
__u32 misr_dpb_luma[8];
__u32 misr_dpb_chroma[8];
__u32 misr_opb_luma[8];
__u32 misr_opb_chroma[8];
};
#define MSM_VIDC_EXTRADATA_OUTPUT_CROP 0x0700000F
struct msm_vidc_output_crop_payload {
__u32 size;
__u32 version;
__u32 port_index;
__u32 left;
__u32 top;
__u32 display_width;
__u32 display_height;
__u32 width;
__u32 height;
__u32 frame_num;
__u32 bit_depth_y;
__u32 bit_depth_c;
struct msm_vidc_misr_info misr_info[2];
};
#define MSM_VIDC_EXTRADATA_INDEX 0x7F100002
struct msm_vidc_extradata_index {
__u32 type;
union {
struct msm_vidc_aspect_ratio_payload aspect_ratio;
};
};
#define MSM_VIDC_EXTRADATA_PANSCAN_WINDOW 0x00000008
struct msm_vidc_panscan_window {
__u32 panscan_height_offset;
__u32 panscan_width_offset;
__u32 panscan_window_width;
__u32 panscan_window_height;
};
struct msm_vidc_panscan_window_payload {
__u32 num_panscan_windows;
struct msm_vidc_panscan_window wnd[1];
};
#define MSM_VIDC_USERDATA_TYPE_FRAME 0x1
#define MSM_VIDC_USERDATA_TYPE_TOP_FIELD 0x2
#define MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD 0x3
#define MSM_VIDC_EXTRADATA_STREAM_USERDATA 0x0000000E
struct msm_vidc_stream_userdata_payload {
__u32 type;
__u32 data[1];
};
#define MSM_VIDC_EXTRADATA_FRAME_QP 0x0000000F
struct msm_vidc_frame_qp_payload {
__u32 frame_qp;
__u32 qp_sum;
__u32 skip_qp_sum;
__u32 skip_num_blocks;
__u32 total_num_blocks;
};
#define MSM_VIDC_EXTRADATA_FRAME_BITS_INFO 0x00000010
struct msm_vidc_frame_bits_info_payload {
__u32 frame_bits;
__u32 header_bits;
};
#define MSM_VIDC_EXTRADATA_S3D_FRAME_PACKING 0x00000006
struct msm_vidc_s3d_frame_packing_payload {
__u32 fpa_id;
__u32 cancel_flag;
__u32 fpa_type;
__u32 quin_cunx_flag;
__u32 content_interprtation_type;
__u32 spatial_flipping_flag;
__u32 frame0_flipped_flag;
__u32 field_views_flag;
__u32 current_frame_is_frame0_flag;
__u32 frame0_self_contained_flag;
__u32 frame1_self_contained_flag;
__u32 frame0_graid_pos_x;
__u32 frame0_graid_pos_y;
__u32 frame1_graid_pos_x;
__u32 frame1_graid_pos_y;
__u32 fpa_reserved_byte;
__u32 fpa_repetition_period;
__u32 fpa_extension_flag;
};
#define MSM_VIDC_EXTRADATA_ROI_QP 0x00000013
struct msm_vidc_roi_deltaqp_payload {
__u32 b_roi_info; /*Enable/Disable*/
__u32 mbi_info_size; /*Size of QP data*/
__u32 data[1];
};
#define MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI 0x00000015
struct msm_vidc_mastering_display_colour_sei_payload {
__u32 nDisplayPrimariesX[3];
__u32 nDisplayPrimariesY[3];
__u32 nWhitePointX;
__u32 nWhitePointY;
__u32 nMaxDisplayMasteringLuminance;
__u32 nMinDisplayMasteringLuminance;
};
#define MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI 0x00000016
struct msm_vidc_content_light_level_sei_payload {
__u32 nMaxContentLight;
__u32 nMaxPicAverageLight;
};
#define MSM_VIDC_EXTRADATA_HDR10PLUS_METADATA 0x0000001A
struct msm_vidc_hdr10plus_metadata_payload {
__u32 size;
__u32 data[1];
};
/* video_format */
#define MSM_VIDC_COMPONENT 0
#define MSM_VIDC_PAL 1
#define MSM_VIDC_NTSC 2
#define MSM_VIDC_SECAM 3
#define MSM_VIDC_MAC 4
#define MSM_VIDC_UNSPECIFIED_FORMAT 5
#define MSM_VIDC_RESERVED_1_FORMAT 6
#define MSM_VIDC_RESERVED_2_FORMAT 7
/* See colour_primaries of ISO/IEC 14496 for significance */
/* color_primaries values */
#define MSM_VIDC_RESERVED_1 0
#define MSM_VIDC_BT709_5 1
#define MSM_VIDC_UNSPECIFIED 2
#define MSM_VIDC_RESERVED_2 3
#define MSM_VIDC_BT470_6_M 4
#define MSM_VIDC_BT601_6_625 5
#define MSM_VIDC_BT470_6_BG MSM_VIDC_BT601_6_625
#define MSM_VIDC_BT601_6_525 6
#define MSM_VIDC_SMPTE_240M 7
#define MSM_VIDC_GENERIC_FILM 8
#define MSM_VIDC_BT2020 9
/* matrix_coeffs values */
#define MSM_VIDC_MATRIX_RGB 0
#define MSM_VIDC_MATRIX_BT_709_5 1
#define MSM_VIDC_MATRIX_UNSPECIFIED 2
#define MSM_VIDC_MATRIX_RESERVED 3
#define MSM_VIDC_MATRIX_FCC_47 4
#define MSM_VIDC_MATRIX_601_6_625 5
#define MSM_VIDC_MATRIX_BT470_BG MSM_VIDC_MATRIX_601_6_625
#define MSM_VIDC_MATRIX_601_6_525 6
#define MSM_VIDC_MATRIX_SMPTE_170M MSM_VIDC_MATRIX_601_6_525
#define MSM_VIDC_MATRIX_SMPTE_240M 7
#define MSM_VIDC_MATRIX_Y_CG_CO 8
#define MSM_VIDC_MATRIX_BT_2020 9
#define MSM_VIDC_MATRIX_BT_2020_CONST 10
/* transfer_char values */
#define MSM_VIDC_TRANSFER_RESERVED_1 0
#define MSM_VIDC_TRANSFER_BT709_5 1
#define MSM_VIDC_TRANSFER_UNSPECIFIED 2
#define MSM_VIDC_TRANSFER_RESERVED_2 3
#define MSM_VIDC_TRANSFER_BT_470_6_M 4
#define MSM_VIDC_TRANSFER_BT_470_6_BG 5
#define MSM_VIDC_TRANSFER_601_6_625 6
#define MSM_VIDC_TRANSFER_601_6_525 MSM_VIDC_TRANSFER_601_6_625
#define MSM_VIDC_TRANSFER_SMPTE_240M 7
#define MSM_VIDC_TRANSFER_LINEAR 8
#define MSM_VIDC_TRANSFER_LOG_100_1 9
#define MSM_VIDC_TRANSFER_LOG_100_SQRT10_1 10
#define MSM_VIDC_TRANSFER_IEC_61966 11
#define MSM_VIDC_TRANSFER_BT_1361 12
#define MSM_VIDC_TRANSFER_SRGB 13
#define MSM_VIDC_TRANSFER_BT_2020_10 14
#define MSM_VIDC_TRANSFER_BT_2020_12 15
#define MSM_VIDC_TRANSFER_SMPTE_ST2084 16
#define MSM_VIDC_TRANSFER_SMPTE_ST428_1 17
#define MSM_VIDC_TRANSFER_HLG 18
#define MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO 0x7F100006
struct msm_vidc_vui_display_info_payload {
__u32 video_signal_present_flag;
__u32 video_format;
__u32 bit_depth_y;
__u32 bit_depth_c;
__u32 video_full_range_flag;
__u32 color_description_present_flag;
__u32 color_primaries;
__u32 transfer_char;
__u32 matrix_coeffs;
__u32 chroma_location_info_present_flag;
__u32 chroma_format_idc;
__u32 separate_color_plane_flag;
__u32 chroma_sample_loc_type_top_field;
__u32 chroma_sample_loc_type_bottom_field;
};
#define MSM_VIDC_EXTRADATA_MPEG2_SEQDISP 0x0000000D
struct msm_vidc_mpeg2_seqdisp_payload {
__u32 video_format;
__u32 color_descp;
__u32 color_primaries;
__u32 transfer_char;
__u32 matrix_coeffs;
__u32 disp_width;
__u32 disp_height;
};
/* VPx color_space values */
#define MSM_VIDC_CS_UNKNOWN 0
#define MSM_VIDC_CS_BT_601 1
#define MSM_VIDC_CS_BT_709 2
#define MSM_VIDC_CS_SMPTE_170 3
#define MSM_VIDC_CS_SMPTE_240 4
#define MSM_VIDC_CS_BT_2020 5
#define MSM_VIDC_CS_RESERVED 6
#define MSM_VIDC_CS_RGB 7
#define MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO 0x00000014
struct msm_vidc_vpx_colorspace_payload {
__u32 color_space;
__u32 yuv_range_flag;
__u32 sumsampling_x;
__u32 sumsampling_y;
};
#define MSM_VIDC_EXTRADATA_METADATA_LTRINFO 0x7F100004
/* ptr[2]: event_notify: pixel_depth */
#define MSM_VIDC_BIT_DEPTH_8 0
#define MSM_VIDC_BIT_DEPTH_10 1
#define MSM_VIDC_BIT_DEPTH_UNSUPPORTED 0XFFFFFFFF
/* ptr[3]: event_notify: pic_struct */
#define MSM_VIDC_PIC_STRUCT_MAYBE_INTERLACED 0x0
#define MSM_VIDC_PIC_STRUCT_PROGRESSIVE 0x1
/*default when layer ID isn't specified*/
#define MSM_VIDC_ALL_LAYER_ID 0xFF
static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height)
{
(void)height;
(void)width;
/*
* In the future, calculate the size based on the w/h but just
* hardcode it for now since 16K satisfies all current usecases.
*/
return 16 * 1024;
}
/* V4L2_CID_MPEG_VIDC_VENC_HDR_INFO payload index */
enum msm_vidc_hdr_info_types {
MSM_VIDC_RGB_PRIMARY_00,
MSM_VIDC_RGB_PRIMARY_01,
MSM_VIDC_RGB_PRIMARY_10,
MSM_VIDC_RGB_PRIMARY_11,
MSM_VIDC_RGB_PRIMARY_20,
MSM_VIDC_RGB_PRIMARY_21,
MSM_VIDC_WHITEPOINT_X,
MSM_VIDC_WHITEPOINT_Y,
MSM_VIDC_MAX_DISP_LUM,
MSM_VIDC_MIN_DISP_LUM,
MSM_VIDC_RGB_MAX_CLL,
MSM_VIDC_RGB_MAX_FLL,
};
#endif