ARC fixes for 4.5
- Corner case of returning to delay slot from interrupt - Changing default interrupt prioiry level - Kconfig'ize support for super pages - Other minor fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWvxdUAAoJEGnX8d3iisJeRkYP/2HZAt4J6c5MPk/NSy8rabVX 2bB1m5jYXlBmJAIsmWm+WcDL72MdrB1Owtc5tEN+hIoQQa2QQpxolp32IslHg0o8 C9CCzmF+iR8wz3caVk3javpsbze23XbHho/kdx/l2Ed3Fi+syI/9jF1GiboydRtR X22an1lslA6Y44pYxFmSFcMCv7XclFkJNe1ltxsgN9/QapnNrE/HWqUIy+SMr2Oo Tpo3m/Dc+IfMMejYyupc3keyAhyeux69lJXPuOzYiurgGUIyXz15Un2mQ9gZWf0u W56L/55VpQVuah46qrp5CBTLmdJA5cBqr0F8RqmZAqrEYLgn5SD4IhDjamo1qsP/ FfFh0cG955SoEyCsUOPILWUFR5TeS4rJK+ZJjErUb+dwEC1BWZR0/Dn1s9KJN8b7 GgGV8yXruDACFlFnCqnlxVs1TKOPOUqD2NZRAdsKunp+ywNrvGdD43xWONcriyvr 2KW0nb+mH3RRk8HQzKjfqsVhLMoR7n1MD/+tg8ME8usLn1ik0hBerT56CX0Wh/yQ VnOUX6xqlaRydeJJgCUyByz3+jJVvj8sk/VZbr19F0p9id6wpiPQeNus2AcoHFKW OyvWcfxzqKegXrYtMsy8IoFzx73zJaXV3ht0I09rhAj3JkdF7vFEIUpKIhsWqxAK yWKKqLcVKga/2Yc8jduI =FNDd -----END PGP SIGNATURE----- Merge tag 'arc-4.5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: "I've been sitting on some of these fixes for a while. - Corner case of returning to delay slot from interrupt - Changing default interrupt prioiry level - Kconfig'ize support for super pages - Other minor fixes" * tag 'arc-4.5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: mm: Introduce explicit super page size support ARCv2: intc: Allow interruption by lowest priority interrupt ARCv2: Check for LL-SC livelock only if LLSC is enabled ARC: shrink cpuinfo by not saving full timer BCR ARCv2: clocksource: Rename GRTC -> GFRC ... ARCv2: STAR 9000950267: Handle return from intr to Delay Slot #2
This commit is contained in:
Linus Torvalds
commit
e835a65f7a
11 changed files with 119 additions and 61 deletions
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@ -338,6 +338,19 @@ config ARC_PAGE_SIZE_4K
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endchoice
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choice
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prompt "MMU Super Page Size"
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depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
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default ARC_HUGEPAGE_2M
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config ARC_HUGEPAGE_2M
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bool "2MB"
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config ARC_HUGEPAGE_16M
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bool "16MB"
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endchoice
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if ISA_ARCOMPACT
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config ARC_COMPACT_IRQ_LEVELS
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@ -410,7 +423,7 @@ config ARC_HAS_RTC
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default n
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depends on !SMP
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config ARC_HAS_GRTC
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config ARC_HAS_GFRC
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bool "SMP synchronized 64-bit cycle counter"
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default y
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depends on SMP
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@ -566,6 +579,12 @@ endmenu
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endmenu # "ARC Architecture Configuration"
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source "mm/Kconfig"
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config FORCE_MAX_ZONEORDER
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int "Maximum zone order"
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default "12" if ARC_HUGEPAGE_16M
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default "11"
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source "net/Kconfig"
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source "drivers/Kconfig"
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source "fs/Kconfig"
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@ -16,7 +16,7 @@ CONFIG_ARC_PLAT_AXS10X=y
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CONFIG_AXS103=y
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CONFIG_ISA_ARCV2=y
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CONFIG_SMP=y
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# CONFIG_ARC_HAS_GRTC is not set
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# CONFIG_ARC_HAS_GFRC is not set
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CONFIG_ARC_UBOOT_SUPPORT=y
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CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
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CONFIG_PREEMPT=y
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@ -349,14 +349,13 @@ struct cpuinfo_arc {
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struct cpuinfo_arc_bpu bpu;
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struct bcr_identity core;
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struct bcr_isa isa;
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struct bcr_timer timers;
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unsigned int vec_base;
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struct cpuinfo_arc_ccm iccm, dccm;
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struct {
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unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
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fpu_sp:1, fpu_dp:1, pad2:6,
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debug:1, ap:1, smart:1, rtt:1, pad3:4,
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pad4:8;
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timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
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} extn;
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struct bcr_mpy extn_mpy;
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struct bcr_extn_xymem extn_xymem;
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@ -30,8 +30,11 @@
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/* Was Intr taken in User Mode */
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#define AUX_IRQ_ACT_BIT_U 31
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/* 0 is highest level, but taken by FIRQs, if present in design */
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#define ARCV2_IRQ_DEF_PRIO 0
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/*
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* User space should be interruptable even by lowest prio interrupt
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* Safe even if actual interrupt priorities is fewer or even one
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*/
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#define ARCV2_IRQ_DEF_PRIO 15
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/* seed value for status register */
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#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
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@ -39,8 +39,8 @@ struct mcip_cmd {
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#define CMD_DEBUG_SET_MASK 0x34
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#define CMD_DEBUG_SET_SELECT 0x36
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#define CMD_GRTC_READ_LO 0x42
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#define CMD_GRTC_READ_HI 0x43
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#define CMD_GFRC_READ_LO 0x42
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#define CMD_GFRC_READ_HI 0x43
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#define CMD_IDU_ENABLE 0x71
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#define CMD_IDU_DISABLE 0x72
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@ -179,37 +179,44 @@
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#define __S111 PAGE_U_X_W_R
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/****************************************************************
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* Page Table Lookup split
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* 2 tier (PGD:PTE) software page walker
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*
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* We implement 2 tier paging and since this is all software, we are free
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* to customize the span of a PGD / PTE entry to suit us
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*
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* 32 bit virtual address
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* [31] 32 bit virtual address [0]
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* -------------------------------------------------------
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* | BITS_FOR_PGD | BITS_FOR_PTE | BITS_IN_PAGE |
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* | | <------------ PGDIR_SHIFT ----------> |
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* | | |
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* | BITS_FOR_PGD | BITS_FOR_PTE | <-- PAGE_SHIFT --> |
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* -------------------------------------------------------
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* | | |
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* | | --> off in page frame
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* | |
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* | ---> index into Page Table
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* |
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* ----> index into Page Directory
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*
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* In a single page size configuration, only PAGE_SHIFT is fixed
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* So both PGD and PTE sizing can be tweaked
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* e.g. 8K page (PAGE_SHIFT 13) can have
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* - PGDIR_SHIFT 21 -> 11:8:13 address split
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* - PGDIR_SHIFT 24 -> 8:11:13 address split
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*
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* If Super Page is configured, PGDIR_SHIFT becomes fixed too,
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* so the sizing flexibility is gone.
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*/
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#define BITS_IN_PAGE PAGE_SHIFT
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/* Optimal Sizing of Pg Tbl - based on MMU page size */
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#if defined(CONFIG_ARC_PAGE_SIZE_8K)
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#define BITS_FOR_PTE 8 /* 11:8:13 */
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#elif defined(CONFIG_ARC_PAGE_SIZE_16K)
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#define BITS_FOR_PTE 8 /* 10:8:14 */
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#elif defined(CONFIG_ARC_PAGE_SIZE_4K)
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#define BITS_FOR_PTE 9 /* 11:9:12 */
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#if defined(CONFIG_ARC_HUGEPAGE_16M)
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#define PGDIR_SHIFT 24
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#elif defined(CONFIG_ARC_HUGEPAGE_2M)
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#define PGDIR_SHIFT 21
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#else
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/*
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* Only Normal page support so "hackable" (see comment above)
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* Default value provides 11:8:13 (8K), 11:9:12 (4K)
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*/
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#define PGDIR_SHIFT 21
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#endif
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#define BITS_FOR_PGD (32 - BITS_FOR_PTE - BITS_IN_PAGE)
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#define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT)
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#define BITS_FOR_PGD (32 - PGDIR_SHIFT)
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#define PGDIR_SHIFT (32 - BITS_FOR_PGD)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT) /* vaddr span, not PDG sz */
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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@ -211,7 +211,11 @@ debug_marker_syscall:
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; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
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; entry was via Exception in DS which got preempted in kernel).
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;
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; IRQ RTIE won't reliably restore DE bit and/or BTA, needs handling
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; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
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;
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; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
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; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
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.Lintr_ret_to_delay_slot:
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debug_marker_ds:
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@ -222,18 +226,23 @@ debug_marker_ds:
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ld r2, [sp, PT_ret]
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ld r3, [sp, PT_status32]
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; STAT32 for Int return created from scratch
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; (No delay dlot, disable Further intr in trampoline)
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bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
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st r0, [sp, PT_status32]
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mov r1, .Lintr_ret_to_delay_slot_2
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st r1, [sp, PT_ret]
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; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
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st r2, [sp, 0]
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st r3, [sp, 4]
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b .Lisr_ret_fast_path
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.Lintr_ret_to_delay_slot_2:
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; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
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sub sp, sp, SZ_PT_REGS
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st r9, [sp, -4]
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@ -243,11 +252,19 @@ debug_marker_ds:
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ld r9, [sp, 4]
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sr r9, [erstatus]
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; restore AUX_USER_SP if returning to U mode
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bbit0 r9, STATUS_U_BIT, 1f
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ld r9, [sp, PT_sp]
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sr r9, [AUX_USER_SP]
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1:
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ld r9, [sp, 8]
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sr r9, [erbta]
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ld r9, [sp, -4]
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add sp, sp, SZ_PT_REGS
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; return from pure kernel mode to delay slot
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rtie
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END(ret_from_exception)
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@ -14,6 +14,8 @@
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#include <linux/irqchip.h>
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#include <asm/irq.h>
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static int irq_prio;
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/*
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* Early Hardware specific Interrupt setup
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* -Called very early (start_kernel -> setup_arch -> setup_processor)
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@ -24,6 +26,14 @@ void arc_init_IRQ(void)
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{
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unsigned int tmp;
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struct irq_build {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
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#else
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unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
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#endif
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} irq_bcr;
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struct aux_irq_ctrl {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res3:18, save_idx_regs:1, res2:1,
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@ -46,28 +56,25 @@ void arc_init_IRQ(void)
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WRITE_AUX(AUX_IRQ_CTRL, ictrl);
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/* setup status32, don't enable intr yet as kernel doesn't want */
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tmp = read_aux_reg(0xa);
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tmp |= ISA_INIT_STATUS_BITS;
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tmp &= ~STATUS_IE_MASK;
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asm volatile("flag %0 \n"::"r"(tmp));
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/*
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* ARCv2 core intc provides multiple interrupt priorities (upto 16).
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* Typical builds though have only two levels (0-high, 1-low)
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* Linux by default uses lower prio 1 for most irqs, reserving 0 for
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* NMI style interrupts in future (say perf)
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*
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* Read the intc BCR to confirm that Linux default priority is avail
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* in h/w
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*
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* Note:
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* IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level
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* is 0 based.
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*/
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tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF;
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if (ARCV2_IRQ_DEF_PRIO > tmp)
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panic("Linux default irq prio incorrect\n");
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READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
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irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
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pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
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irq_prio + 1, irq_prio,
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irq_bcr.firq ? " FIRQ (not used)":"");
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/* setup status32, don't enable intr yet as kernel doesn't want */
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tmp = read_aux_reg(0xa);
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tmp |= STATUS_AD_MASK | (irq_prio << 1);
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tmp &= ~STATUS_IE_MASK;
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asm volatile("flag %0 \n"::"r"(tmp));
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}
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static void arcv2_irq_mask(struct irq_data *data)
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@ -86,7 +93,7 @@ void arcv2_irq_enable(struct irq_data *data)
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{
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/* set default priority */
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write_aux_reg(AUX_IRQ_SELECT, data->irq);
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write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
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write_aux_reg(AUX_IRQ_PRIORITY, irq_prio);
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/*
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* hw auto enables (linux unmask) all by default
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@ -96,13 +96,13 @@ static void mcip_probe_n_setup(void)
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:8,
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idu:1, llm:1, num_cores:6,
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iocoh:1, grtc:1, dbg:1, pad2:1,
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iocoh:1, gfrc:1, dbg:1, pad2:1,
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msg:1, sem:1, ipi:1, pad:1,
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ver:8;
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#else
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unsigned int ver:8,
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pad:1, ipi:1, sem:1, msg:1,
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pad2:1, dbg:1, grtc:1, iocoh:1,
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pad2:1, dbg:1, gfrc:1, iocoh:1,
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num_cores:6, llm:1, idu:1,
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pad3:8;
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#endif
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@ -116,7 +116,7 @@ static void mcip_probe_n_setup(void)
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IS_AVAIL1(mp.ipi, "IPI "),
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IS_AVAIL1(mp.idu, "IDU "),
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IS_AVAIL1(mp.dbg, "DEBUG "),
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IS_AVAIL1(mp.grtc, "GRTC"));
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IS_AVAIL1(mp.gfrc, "GFRC"));
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idu_detected = mp.idu;
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@ -125,8 +125,8 @@ static void mcip_probe_n_setup(void)
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__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
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}
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if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
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panic("kernel trying to use non-existent GRTC\n");
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if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
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panic("kernel trying to use non-existent GFRC\n");
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}
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struct plat_smp_ops plat_smp_ops = {
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@ -45,6 +45,7 @@ struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
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static void read_arc_build_cfg_regs(void)
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{
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struct bcr_perip uncached_space;
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struct bcr_timer timer;
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struct bcr_generic bcr;
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struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
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unsigned long perip_space;
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@ -53,7 +54,11 @@ static void read_arc_build_cfg_regs(void)
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READ_BCR(AUX_IDENTITY, cpu->core);
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READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
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READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
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READ_BCR(ARC_REG_TIMERS_BCR, timer);
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cpu->extn.timer0 = timer.t0;
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cpu->extn.timer1 = timer.t1;
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cpu->extn.rtc = timer.rtc;
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cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
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READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
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@ -208,9 +213,9 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
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(unsigned int)(arc_get_core_freq() / 10000) % 100);
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n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
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IS_AVAIL1(cpu->timers.t0, "Timer0 "),
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IS_AVAIL1(cpu->timers.t1, "Timer1 "),
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IS_AVAIL2(cpu->timers.rtc, "64-bit RTC ",
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IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
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IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
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IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
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CONFIG_ARC_HAS_RTC));
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n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
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@ -293,13 +298,13 @@ static void arc_chk_core_config(void)
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struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
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int fpu_enabled;
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if (!cpu->timers.t0)
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if (!cpu->extn.timer0)
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panic("Timer0 is not present!\n");
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if (!cpu->timers.t1)
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if (!cpu->extn.timer1)
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panic("Timer1 is not present!\n");
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->timers.rtc)
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->extn.rtc)
|
||||
panic("RTC is not present\n");
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_DCCM
|
||||
|
|
@ -334,6 +339,7 @@ static void arc_chk_core_config(void)
|
|||
panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
|
||||
|
||||
if (is_isa_arcv2() && IS_ENABLED(CONFIG_SMP) && cpu->isa.atomic &&
|
||||
IS_ENABLED(CONFIG_ARC_HAS_LLSC) &&
|
||||
!IS_ENABLED(CONFIG_ARC_STAR_9000923308))
|
||||
panic("llock/scond livelock workaround missing\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@
|
|||
|
||||
/********** Clock Source Device *********/
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_GRTC
|
||||
#ifdef CONFIG_ARC_HAS_GFRC
|
||||
|
||||
static int arc_counter_setup(void)
|
||||
{
|
||||
|
|
@ -83,10 +83,10 @@ static cycle_t arc_counter_read(struct clocksource *cs)
|
|||
|
||||
local_irq_save(flags);
|
||||
|
||||
__mcip_cmd(CMD_GRTC_READ_LO, 0);
|
||||
__mcip_cmd(CMD_GFRC_READ_LO, 0);
|
||||
stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
|
||||
__mcip_cmd(CMD_GRTC_READ_HI, 0);
|
||||
__mcip_cmd(CMD_GFRC_READ_HI, 0);
|
||||
stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
|
@ -95,7 +95,7 @@ static cycle_t arc_counter_read(struct clocksource *cs)
|
|||
}
|
||||
|
||||
static struct clocksource arc_counter = {
|
||||
.name = "ARConnect GRTC",
|
||||
.name = "ARConnect GFRC",
|
||||
.rating = 400,
|
||||
.read = arc_counter_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
|
|
|
|||
Loading…
Reference in a new issue