OMAP: add TI OMAP1 external LCD controller support - SoSSI
- Adds support for Texas Instruments OMAP1 processors boards connected with external LCD controller through "Special OptimiSed Screen Interface" Signed-off-by: Trilok Soni <soni.trilok@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Imre Deak
Linus Torvalds
parent
7a055fc222
commit
e6b4573c56
3 changed files with 695 additions and 0 deletions
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@ -36,3 +36,10 @@ config FB_OMAP_DMA_TUNE
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answer yes. Answer no if you have a dedicated video
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memory, or don't use any of the accelerated features.
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config FB_OMAP_LCDC_EXTERNAL
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bool "External LCD controller support"
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depends on FB_OMAP
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help
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Say Y here, if you want to have support for boards with an
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external LCD controller connected to the SoSSI/RFBI interface.
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@ -9,5 +9,7 @@ objs-yy := omapfb_main.o
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objs-y$(CONFIG_ARCH_OMAP1) += lcdc.o
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objs-y$(CONFIG_ARCH_OMAP2) += dispc.o
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objs-$(CONFIG_ARCH_OMAP1)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o
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omapfb-objs := $(objs-yy)
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686
drivers/video/omap/sossi.c
Normal file
686
drivers/video/omap/sossi.c
Normal file
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@ -0,0 +1,686 @@
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/*
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* OMAP1 Special OptimiSed Screen Interface support
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*
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* Copyright (C) 2004-2005 Nokia Corporation
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/omapfb.h>
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#include "lcdc.h"
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#define MODULE_NAME "omapfb-sossi"
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#define OMAP_SOSSI_BASE 0xfffbac00
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#define SOSSI_ID_REG 0x00
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#define SOSSI_INIT1_REG 0x04
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#define SOSSI_INIT2_REG 0x08
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#define SOSSI_INIT3_REG 0x0c
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#define SOSSI_FIFO_REG 0x10
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#define SOSSI_REOTABLE_REG 0x14
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#define SOSSI_TEARING_REG 0x18
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#define SOSSI_INIT1B_REG 0x1c
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#define SOSSI_FIFOB_REG 0x20
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#define DMA_GSCR 0xfffedc04
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#define DMA_LCD_CCR 0xfffee3c2
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#define DMA_LCD_CTRL 0xfffee3c4
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#define DMA_LCD_LCH_CTRL 0xfffee3ea
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#define CONF_SOSSI_RESET_R (1 << 23)
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#define RD_ACCESS 0
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#define WR_ACCESS 1
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#define SOSSI_MAX_XMIT_BYTES (512 * 1024)
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static struct {
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void __iomem *base;
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struct clk *fck;
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unsigned long fck_hz;
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spinlock_t lock;
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int bus_pick_count;
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int bus_pick_width;
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int tearsync_mode;
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int tearsync_line;
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void (*lcdc_callback)(void *data);
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void *lcdc_callback_data;
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int vsync_dma_pending;
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/* timing for read and write access */
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int clk_div;
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u8 clk_tw0[2];
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u8 clk_tw1[2];
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/*
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* if last_access is the same as current we don't have to change
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* the timings
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*/
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int last_access;
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struct omapfb_device *fbdev;
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} sossi;
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static inline u32 sossi_read_reg(int reg)
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{
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return readl(sossi.base + reg);
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}
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static inline u16 sossi_read_reg16(int reg)
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{
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return readw(sossi.base + reg);
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}
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static inline u8 sossi_read_reg8(int reg)
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{
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return readb(sossi.base + reg);
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}
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static inline void sossi_write_reg(int reg, u32 value)
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{
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writel(value, sossi.base + reg);
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}
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static inline void sossi_write_reg16(int reg, u16 value)
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{
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writew(value, sossi.base + reg);
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}
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static inline void sossi_write_reg8(int reg, u8 value)
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{
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writeb(value, sossi.base + reg);
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}
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static void sossi_set_bits(int reg, u32 bits)
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{
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sossi_write_reg(reg, sossi_read_reg(reg) | bits);
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}
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static void sossi_clear_bits(int reg, u32 bits)
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{
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sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
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}
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#define HZ_TO_PS(x) (1000000000 / (x / 1000))
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static u32 ps_to_sossi_ticks(u32 ps, int div)
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{
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u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div;
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return (clk_period + ps - 1) / clk_period;
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}
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static int calc_rd_timings(struct extif_timings *t)
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{
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u32 tw0, tw1;
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int reon, reoff, recyc, actim;
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int div = t->clk_div;
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/*
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* Make sure that after conversion it still holds that:
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* reoff > reon, recyc >= reoff, actim > reon
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*/
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reon = ps_to_sossi_ticks(t->re_on_time, div);
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/* reon will be exactly one sossi tick */
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if (reon > 1)
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return -1;
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reoff = ps_to_sossi_ticks(t->re_off_time, div);
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if (reoff <= reon)
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reoff = reon + 1;
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tw0 = reoff - reon;
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if (tw0 > 0x10)
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return -1;
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recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
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if (recyc <= reoff)
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recyc = reoff + 1;
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tw1 = recyc - tw0;
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/* values less then 3 result in the SOSSI block resetting itself */
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if (tw1 < 3)
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tw1 = 3;
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if (tw1 > 0x40)
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return -1;
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actim = ps_to_sossi_ticks(t->access_time, div);
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if (actim < reoff)
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actim++;
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/*
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* access time (data hold time) will be exactly one sossi
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* tick
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*/
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if (actim - reoff > 1)
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return -1;
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t->tim[0] = tw0 - 1;
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t->tim[1] = tw1 - 1;
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return 0;
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}
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static int calc_wr_timings(struct extif_timings *t)
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{
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u32 tw0, tw1;
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int weon, weoff, wecyc;
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int div = t->clk_div;
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/*
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* Make sure that after conversion it still holds that:
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* weoff > weon, wecyc >= weoff
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*/
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weon = ps_to_sossi_ticks(t->we_on_time, div);
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/* weon will be exactly one sossi tick */
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if (weon > 1)
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return -1;
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weoff = ps_to_sossi_ticks(t->we_off_time, div);
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if (weoff <= weon)
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weoff = weon + 1;
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tw0 = weoff - weon;
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if (tw0 > 0x10)
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return -1;
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wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
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if (wecyc <= weoff)
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wecyc = weoff + 1;
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tw1 = wecyc - tw0;
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/* values less then 3 result in the SOSSI block resetting itself */
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if (tw1 < 3)
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tw1 = 3;
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if (tw1 > 0x40)
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return -1;
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t->tim[2] = tw0 - 1;
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t->tim[3] = tw1 - 1;
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return 0;
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}
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static void _set_timing(int div, int tw0, int tw1)
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{
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u32 l;
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#ifdef VERBOSE
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dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n",
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tw0 + 1, tw1 + 1, div);
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#endif
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clk_set_rate(sossi.fck, sossi.fck_hz / div);
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clk_enable(sossi.fck);
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l = sossi_read_reg(SOSSI_INIT1_REG);
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l &= ~((0x0f << 20) | (0x3f << 24));
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l |= (tw0 << 20) | (tw1 << 24);
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sossi_write_reg(SOSSI_INIT1_REG, l);
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clk_disable(sossi.fck);
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}
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static void _set_bits_per_cycle(int bus_pick_count, int bus_pick_width)
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{
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u32 l;
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l = sossi_read_reg(SOSSI_INIT3_REG);
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l &= ~0x3ff;
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l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
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sossi_write_reg(SOSSI_INIT3_REG, l);
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}
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static void _set_tearsync_mode(int mode, unsigned line)
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{
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u32 l;
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l = sossi_read_reg(SOSSI_TEARING_REG);
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l &= ~(((1 << 11) - 1) << 15);
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l |= line << 15;
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l &= ~(0x3 << 26);
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l |= mode << 26;
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sossi_write_reg(SOSSI_TEARING_REG, l);
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if (mode)
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sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */
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else
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sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6);
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}
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static inline void set_timing(int access)
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{
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if (access != sossi.last_access) {
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sossi.last_access = access;
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_set_timing(sossi.clk_div,
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sossi.clk_tw0[access], sossi.clk_tw1[access]);
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}
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}
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static void sossi_start_transfer(void)
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{
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/* WE */
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sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
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/* CS active low */
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sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30);
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}
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static void sossi_stop_transfer(void)
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{
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/* WE */
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sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
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/* CS active low */
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sossi_set_bits(SOSSI_INIT1_REG, 1 << 30);
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}
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static void wait_end_of_write(void)
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{
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/* Before reading we must check if some writings are going on */
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while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
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}
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static void send_data(const void *data, unsigned int len)
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{
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while (len >= 4) {
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sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data);
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len -= 4;
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data += 4;
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}
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while (len >= 2) {
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sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data);
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len -= 2;
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data += 2;
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}
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while (len) {
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sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data);
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len--;
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data++;
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}
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}
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static void set_cycles(unsigned int len)
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{
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unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
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BUG_ON((nr_cycles - 1) & ~0x3ffff);
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sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
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sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
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}
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static int sossi_convert_timings(struct extif_timings *t)
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{
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int r = 0;
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int div = t->clk_div;
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t->converted = 0;
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if (div <= 0 || div > 8)
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return -1;
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/* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
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if ((r = calc_rd_timings(t)) < 0)
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return r;
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if ((r = calc_wr_timings(t)) < 0)
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return r;
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t->tim[4] = div;
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t->converted = 1;
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return 0;
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}
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static void sossi_set_timings(const struct extif_timings *t)
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{
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BUG_ON(!t->converted);
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sossi.clk_tw0[RD_ACCESS] = t->tim[0];
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sossi.clk_tw1[RD_ACCESS] = t->tim[1];
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sossi.clk_tw0[WR_ACCESS] = t->tim[2];
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sossi.clk_tw1[WR_ACCESS] = t->tim[3];
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sossi.clk_div = t->tim[4];
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}
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static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
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{
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*clk_period = HZ_TO_PS(sossi.fck_hz);
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*max_clk_div = 8;
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}
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static void sossi_set_bits_per_cycle(int bpc)
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{
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int bus_pick_count, bus_pick_width;
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/*
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* We set explicitly the the bus_pick_count as well, although
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* with remapping/reordering disabled it will be calculated by HW
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* as (32 / bus_pick_width).
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*/
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switch (bpc) {
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case 8:
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bus_pick_count = 4;
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bus_pick_width = 8;
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break;
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case 16:
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bus_pick_count = 2;
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bus_pick_width = 16;
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break;
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default:
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BUG();
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return;
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}
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sossi.bus_pick_width = bus_pick_width;
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sossi.bus_pick_count = bus_pick_count;
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}
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static int sossi_setup_tearsync(unsigned pin_cnt,
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unsigned hs_pulse_time, unsigned vs_pulse_time,
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int hs_pol_inv, int vs_pol_inv, int div)
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{
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int hs, vs;
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u32 l;
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if (pin_cnt != 1 || div < 1 || div > 8)
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return -EINVAL;
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hs = ps_to_sossi_ticks(hs_pulse_time, div);
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vs = ps_to_sossi_ticks(vs_pulse_time, div);
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if (vs < 8 || vs <= hs || vs >= (1 << 12))
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return -EDOM;
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vs /= 8;
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vs--;
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if (hs > 8)
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hs = 8;
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if (hs)
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hs--;
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dev_dbg(sossi.fbdev->dev,
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"setup_tearsync: hs %d vs %d hs_inv %d vs_inv %d\n",
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hs, vs, hs_pol_inv, vs_pol_inv);
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clk_enable(sossi.fck);
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l = sossi_read_reg(SOSSI_TEARING_REG);
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l &= ~((1 << 15) - 1);
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l |= vs << 3;
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l |= hs;
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if (hs_pol_inv)
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l |= 1 << 29;
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else
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l &= ~(1 << 29);
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if (vs_pol_inv)
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l |= 1 << 28;
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else
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l &= ~(1 << 28);
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sossi_write_reg(SOSSI_TEARING_REG, l);
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clk_disable(sossi.fck);
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return 0;
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}
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static int sossi_enable_tearsync(int enable, unsigned line)
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{
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int mode;
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dev_dbg(sossi.fbdev->dev, "tearsync %d line %d\n", enable, line);
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if (line >= 1 << 11)
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return -EINVAL;
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if (enable) {
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if (line)
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mode = 2; /* HS or VS */
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else
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mode = 3; /* VS only */
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} else
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mode = 0;
|
||||
sossi.tearsync_line = line;
|
||||
sossi.tearsync_mode = mode;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sossi_write_command(const void *data, unsigned int len)
|
||||
{
|
||||
clk_enable(sossi.fck);
|
||||
set_timing(WR_ACCESS);
|
||||
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
|
||||
/* CMD#/DATA */
|
||||
sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
|
||||
set_cycles(len);
|
||||
sossi_start_transfer();
|
||||
send_data(data, len);
|
||||
sossi_stop_transfer();
|
||||
wait_end_of_write();
|
||||
clk_disable(sossi.fck);
|
||||
}
|
||||
|
||||
static void sossi_write_data(const void *data, unsigned int len)
|
||||
{
|
||||
clk_enable(sossi.fck);
|
||||
set_timing(WR_ACCESS);
|
||||
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
|
||||
/* CMD#/DATA */
|
||||
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
|
||||
set_cycles(len);
|
||||
sossi_start_transfer();
|
||||
send_data(data, len);
|
||||
sossi_stop_transfer();
|
||||
wait_end_of_write();
|
||||
clk_disable(sossi.fck);
|
||||
}
|
||||
|
||||
static void sossi_transfer_area(int width, int height,
|
||||
void (callback)(void *data), void *data)
|
||||
{
|
||||
BUG_ON(callback == NULL);
|
||||
|
||||
sossi.lcdc_callback = callback;
|
||||
sossi.lcdc_callback_data = data;
|
||||
|
||||
clk_enable(sossi.fck);
|
||||
set_timing(WR_ACCESS);
|
||||
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
|
||||
_set_tearsync_mode(sossi.tearsync_mode, sossi.tearsync_line);
|
||||
/* CMD#/DATA */
|
||||
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
|
||||
set_cycles(width * height * sossi.bus_pick_width / 8);
|
||||
|
||||
sossi_start_transfer();
|
||||
if (sossi.tearsync_mode) {
|
||||
/*
|
||||
* Wait for the sync signal and start the transfer only
|
||||
* then. We can't seem to be able to use HW sync DMA for
|
||||
* this since LCD DMA shows huge latencies, as if it
|
||||
* would ignore some of the DMA requests from SoSSI.
|
||||
*/
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&sossi.lock, flags);
|
||||
sossi.vsync_dma_pending++;
|
||||
spin_unlock_irqrestore(&sossi.lock, flags);
|
||||
} else
|
||||
/* Just start the transfer right away. */
|
||||
omap_enable_lcd_dma();
|
||||
}
|
||||
|
||||
static void sossi_dma_callback(void *data)
|
||||
{
|
||||
omap_stop_lcd_dma();
|
||||
sossi_stop_transfer();
|
||||
clk_disable(sossi.fck);
|
||||
sossi.lcdc_callback(sossi.lcdc_callback_data);
|
||||
}
|
||||
|
||||
static void sossi_read_data(void *data, unsigned int len)
|
||||
{
|
||||
clk_enable(sossi.fck);
|
||||
set_timing(RD_ACCESS);
|
||||
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
|
||||
/* CMD#/DATA */
|
||||
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
|
||||
set_cycles(len);
|
||||
sossi_start_transfer();
|
||||
while (len >= 4) {
|
||||
*(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
|
||||
len -= 4;
|
||||
data += 4;
|
||||
}
|
||||
while (len >= 2) {
|
||||
*(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG);
|
||||
len -= 2;
|
||||
data += 2;
|
||||
}
|
||||
while (len) {
|
||||
*(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG);
|
||||
len--;
|
||||
data++;
|
||||
}
|
||||
sossi_stop_transfer();
|
||||
clk_disable(sossi.fck);
|
||||
}
|
||||
|
||||
static irqreturn_t sossi_match_irq(int irq, void *data)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&sossi.lock, flags);
|
||||
if (sossi.vsync_dma_pending) {
|
||||
sossi.vsync_dma_pending--;
|
||||
omap_enable_lcd_dma();
|
||||
}
|
||||
spin_unlock_irqrestore(&sossi.lock, flags);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int sossi_init(struct omapfb_device *fbdev)
|
||||
{
|
||||
u32 l, k;
|
||||
struct clk *fck;
|
||||
struct clk *dpll1out_ck;
|
||||
int r;
|
||||
|
||||
sossi.base = (void __iomem *)IO_ADDRESS(OMAP_SOSSI_BASE);
|
||||
sossi.fbdev = fbdev;
|
||||
spin_lock_init(&sossi.lock);
|
||||
|
||||
dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out");
|
||||
if (IS_ERR(dpll1out_ck)) {
|
||||
dev_err(fbdev->dev, "can't get DPLL1OUT clock\n");
|
||||
return PTR_ERR(dpll1out_ck);
|
||||
}
|
||||
/*
|
||||
* We need the parent clock rate, which we might divide further
|
||||
* depending on the timing requirements of the controller. See
|
||||
* _set_timings.
|
||||
*/
|
||||
sossi.fck_hz = clk_get_rate(dpll1out_ck);
|
||||
clk_put(dpll1out_ck);
|
||||
|
||||
fck = clk_get(fbdev->dev, "ck_sossi");
|
||||
if (IS_ERR(fck)) {
|
||||
dev_err(fbdev->dev, "can't get SoSSI functional clock\n");
|
||||
return PTR_ERR(fck);
|
||||
}
|
||||
sossi.fck = fck;
|
||||
|
||||
/* Reset and enable the SoSSI module */
|
||||
l = omap_readl(MOD_CONF_CTRL_1);
|
||||
l |= CONF_SOSSI_RESET_R;
|
||||
omap_writel(l, MOD_CONF_CTRL_1);
|
||||
l &= ~CONF_SOSSI_RESET_R;
|
||||
omap_writel(l, MOD_CONF_CTRL_1);
|
||||
|
||||
clk_enable(sossi.fck);
|
||||
l = omap_readl(ARM_IDLECT2);
|
||||
l &= ~(1 << 8); /* DMACK_REQ */
|
||||
omap_writel(l, ARM_IDLECT2);
|
||||
|
||||
l = sossi_read_reg(SOSSI_INIT2_REG);
|
||||
/* Enable and reset the SoSSI block */
|
||||
l |= (1 << 0) | (1 << 1);
|
||||
sossi_write_reg(SOSSI_INIT2_REG, l);
|
||||
/* Take SoSSI out of reset */
|
||||
l &= ~(1 << 1);
|
||||
sossi_write_reg(SOSSI_INIT2_REG, l);
|
||||
|
||||
sossi_write_reg(SOSSI_ID_REG, 0);
|
||||
l = sossi_read_reg(SOSSI_ID_REG);
|
||||
k = sossi_read_reg(SOSSI_ID_REG);
|
||||
|
||||
if (l != 0x55555555 || k != 0xaaaaaaaa) {
|
||||
dev_err(fbdev->dev,
|
||||
"invalid SoSSI sync pattern: %08x, %08x\n", l, k);
|
||||
r = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
|
||||
dev_err(fbdev->dev, "can't get LCDC IRQ\n");
|
||||
r = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
|
||||
l = sossi_read_reg(SOSSI_ID_REG);
|
||||
dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n",
|
||||
l >> 16, l & 0xffff);
|
||||
|
||||
l = sossi_read_reg(SOSSI_INIT1_REG);
|
||||
l |= (1 << 19); /* DMA_MODE */
|
||||
l &= ~(1 << 31); /* REORDERING */
|
||||
sossi_write_reg(SOSSI_INIT1_REG, l);
|
||||
|
||||
if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq,
|
||||
IRQT_FALLING,
|
||||
"sossi_match", sossi.fbdev->dev)) < 0) {
|
||||
dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
clk_disable(sossi.fck);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
clk_disable(sossi.fck);
|
||||
clk_put(sossi.fck);
|
||||
return r;
|
||||
}
|
||||
|
||||
static void sossi_cleanup(void)
|
||||
{
|
||||
omap_lcdc_free_dma_callback();
|
||||
clk_put(sossi.fck);
|
||||
}
|
||||
|
||||
struct lcd_ctrl_extif omap1_ext_if = {
|
||||
.init = sossi_init,
|
||||
.cleanup = sossi_cleanup,
|
||||
.get_clk_info = sossi_get_clk_info,
|
||||
.convert_timings = sossi_convert_timings,
|
||||
.set_timings = sossi_set_timings,
|
||||
.set_bits_per_cycle = sossi_set_bits_per_cycle,
|
||||
.setup_tearsync = sossi_setup_tearsync,
|
||||
.enable_tearsync = sossi_enable_tearsync,
|
||||
.write_command = sossi_write_command,
|
||||
.read_data = sossi_read_data,
|
||||
.write_data = sossi_write_data,
|
||||
.transfer_area = sossi_transfer_area,
|
||||
|
||||
.max_transmit_size = SOSSI_MAX_XMIT_BYTES,
|
||||
};
|
||||
|
||||
Loading…
Reference in a new issue