dtb: xgene: Add 2nd 10GbE node
Adding the second 10GbE dt node for APM X-Gene SoC device tree Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 28 additions and 0 deletions
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@ -207,6 +207,17 @@
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clock-output-names = "xge0clk";
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};
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xge1clk: xge1clk@1f62c000 {
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compatible = "apm,xgene-device-clock";
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status = "disabled";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f62c000 0x0 0x1000>;
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reg-names = "csr-reg";
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csr-mask = <0x3>;
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clock-output-names = "xge1clk";
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};
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sataphy1clk: sataphy1clk@1f21c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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@ -816,6 +827,23 @@
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phy-connection-type = "xgmii";
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};
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xgenet1: ethernet@1f620000 {
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compatible = "apm,xgene1-xgenet";
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status = "disabled";
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reg = <0x0 0x1f620000 0x0 0xd100>,
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<0x0 0x1f600000 0x0 0Xc300>,
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<0x0 0x18000000 0x0 0X8000>;
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reg-names = "enet_csr", "ring_csr", "ring_cmd";
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interrupts = <0x0 0x6C 0x4>,
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<0x0 0x6D 0x4>;
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port-id = <1>;
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dma-coherent;
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clocks = <&xge1clk 0>;
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/* mac address will be overwritten by the bootloader */
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local-mac-address = [00 00 00 00 00 00];
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phy-connection-type = "xgmii";
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};
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rng: rng@10520000 {
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compatible = "apm,xgene-rng";
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reg = <0x0 0x10520000 0x0 0x100>;
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