[POWERPC] bootwrapper: Add PowerQUICC II (82xx with CPM) cuboot support
This allows booting on legacy, non-device-tree aware versions of U-boot. It also fixes up the hardware to match the PCI and chipselect information in the device tree, as u-boot is inconsistent in setting these up correctly (or at all). Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Scott Wood
Paul Mackerras
parent
0b195812df
commit
e5d8d54db2
5 changed files with 298 additions and 4 deletions
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@ -48,7 +48,7 @@ src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
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cpm-serial.c
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src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
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cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
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ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c
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ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c cuboot-pq2.c
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src-boot := $(src-wlib) $(src-plat) empty.c
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src-boot := $(addprefix $(obj)/, $(src-boot))
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@ -141,6 +141,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImage
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ifneq ($(CONFIG_DEVICE_TREE),"")
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image-$(CONFIG_PPC_8xx) += cuImage.8xx
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image-$(CONFIG_8260) += cuImage.pq2
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image-$(CONFIG_PPC_83xx) += cuImage.83xx
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image-$(CONFIG_PPC_85xx) += cuImage.85xx
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image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
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283
arch/powerpc/boot/cuboot-pq2.c
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283
arch/powerpc/boot/cuboot-pq2.c
Normal file
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@ -0,0 +1,283 @@
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/*
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* Old U-boot compatibility for PowerQUICC II
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* (a.k.a. 82xx with CPM, not the 8240 family of chips)
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*
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include "ops.h"
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#include "stdio.h"
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#include "cuboot.h"
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#include "io.h"
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#define TARGET_CPM2
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#define TARGET_HAS_ETH1
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#include "ppcboot.h"
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static bd_t bd;
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struct cs_range {
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u32 csnum;
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u32 base; /* must be zero */
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u32 addr;
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u32 size;
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};
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struct pci_range {
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u32 flags;
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u32 pci_addr[2];
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u32 phys_addr;
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u32 size[2];
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};
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struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
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struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
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/* Different versions of u-boot put the BCSR in different places, and
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* some don't set up the PCI PIC at all, so we assume the device tree is
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* sane and update the BRx registers appropriately.
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*
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* For any node defined as compatible with fsl,pq2-chipselect,
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* #address/#size must be 2/1 for chipselect bus, 1/1 for parent bus,
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* and ranges must be for whole chip selects.
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*/
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static void update_cs_ranges(void)
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{
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u32 ctrl_ph;
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void *ctrl_node, *bus_node, *parent_node;
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u32 *ctrl_addr;
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unsigned long ctrl_size;
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u32 naddr, nsize;
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int len;
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int i;
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bus_node = finddevice("/chipselect");
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if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-chipselect"))
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return;
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dt_get_reg_format(bus_node, &naddr, &nsize);
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if (naddr != 2 || nsize != 1)
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goto err;
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parent_node = get_parent(bus_node);
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if (!parent_node)
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goto err;
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dt_get_reg_format(parent_node, &naddr, &nsize);
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if (naddr != 1 || nsize != 1)
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goto err;
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len = getprop(bus_node, "fsl,ctrl", &ctrl_ph, 4);
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if (len != 4)
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goto err;
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ctrl_node = find_node_by_prop_value(NULL, "linux,phandle",
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(char *)&ctrl_ph, 4);
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if (!ctrl_node)
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goto err;
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if (!dt_is_compatible(ctrl_node, "fsl,pq2-chipselect-ctrl"))
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goto err;
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if (!dt_xlate_reg(ctrl_node, 0, (unsigned long *)&ctrl_addr,
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&ctrl_size))
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goto err;
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len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
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for (i = 0; i < len / sizeof(struct cs_range); i++) {
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u32 base, option;
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int cs = cs_ranges_buf[i].csnum;
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if (cs >= ctrl_size / 8)
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goto err;
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if (cs_ranges_buf[i].base != 0)
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goto err;
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base = in_be32(&ctrl_addr[cs * 2]);
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/* If CS is already valid, use the existing flags.
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* Otherwise, guess a sane default.
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*/
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if (base & 1) {
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base &= 0x7fff;
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option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
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} else {
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base = 0x1801;
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option = 0x10;
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}
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out_be32(&ctrl_addr[cs * 2], 0);
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out_be32(&ctrl_addr[cs * 2 + 1],
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option | ~(cs_ranges_buf[i].size - 1));
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out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
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}
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return;
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err:
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printf("Bad /chipselect or fsl,pq2-chipselect-ctrl node\r\n");
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}
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/* Older u-boots don't set PCI up properly. Update the hardware to match
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* the device tree. The prefetch mem region and non-prefetch mem region
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* must be contiguous in the host bus. As required by the PCI binding,
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* PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only
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* 32-bit PCI is supported. All three region types (prefetchable mem,
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* non-prefetchable mem, and I/O) must be present.
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*/
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static void fixup_pci(void)
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{
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struct pci_range *mem = NULL, *mmio = NULL,
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*io = NULL, *mem_base = NULL;
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u32 *pci_regs[3];
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u8 *soc_regs;
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int i, len;
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void *ctrl_node, *bus_node, *parent_node, *soc_node;
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u32 naddr, nsize, bus_ph, mem_log2;
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ctrl_node = finddevice("/soc/pci");
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if (!ctrl_node || !dt_is_compatible(ctrl_node, "fsl,pq2-pci"))
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return;
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soc_node = finddevice("/soc");
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if (!soc_node || !dt_is_compatible(soc_node, "fsl,pq2-soc"))
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goto err;
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for (i = 0; i < 3; i++)
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if (!dt_xlate_reg(ctrl_node, i,
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(unsigned long *)&pci_regs[i], NULL))
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goto err;
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if (!dt_xlate_reg(soc_node, 0, (unsigned long *)&soc_regs, NULL))
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goto err;
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len = getprop(ctrl_node, "fsl,bus", &bus_ph, 4);
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if (len != 4)
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goto err;
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bus_node = find_node_by_prop_value(NULL, "linux,phandle",
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(char *)&bus_ph, 4);
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if (!bus_node)
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goto err;
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dt_get_reg_format(bus_node, &naddr, &nsize);
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if (naddr != 3 || nsize != 2)
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goto err;
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parent_node = get_parent(bus_node);
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if (!parent_node)
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goto err;
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dt_get_reg_format(parent_node, &naddr, &nsize);
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if (naddr != 1 || nsize != 1)
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goto err;
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len = getprop(bus_node, "ranges", pci_ranges_buf,
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sizeof(pci_ranges_buf));
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for (i = 0; i < len / sizeof(struct pci_range); i++) {
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u32 flags = pci_ranges_buf[i].flags & 0x43000000;
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if (flags == 0x42000000)
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mem = &pci_ranges_buf[i];
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else if (flags == 0x02000000)
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mmio = &pci_ranges_buf[i];
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else if (flags == 0x01000000)
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io = &pci_ranges_buf[i];
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}
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if (!mem || !mmio || !io)
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goto err;
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if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
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mem_base = mem;
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else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
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mem_base = mmio;
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else
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goto err;
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out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
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out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
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out_be32(&pci_regs[1][1], io->phys_addr | 1);
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out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
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out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
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out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
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out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
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out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
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out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
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out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
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out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
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out_le32(&pci_regs[0][14], io->phys_addr >> 12);
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out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
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/* Inbound translation */
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out_le32(&pci_regs[0][58], 0);
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out_le32(&pci_regs[0][60], 0);
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mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
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out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
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/* If PCI is disabled, drive RST high to enable. */
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if (!(in_le32(&pci_regs[0][32]) & 1)) {
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/* Tpvrh (Power valid to RST# high) 100 ms */
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udelay(100000);
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out_le32(&pci_regs[0][32], 1);
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/* Trhfa (RST# high to first cfg access) 2^25 clocks */
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udelay(1020000);
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}
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/* Enable bus master and memory access */
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out_le32(&pci_regs[0][64], 0x80000004);
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out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
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/* Park the bus on PCI, and elevate PCI's arbitration priority,
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* as required by section 9.6 of the user's manual.
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*/
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out_8(&soc_regs[0x10028], 3);
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out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
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return;
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err:
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printf("Bad PCI node\r\n");
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}
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static void pq2_platform_fixups(void)
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{
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void *node;
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dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
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dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
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dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
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node = finddevice("/soc/cpm");
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if (node) {
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setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
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setprop(node, "fsl,brg-frequency", &bd.bi_brgfreq, 4);
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}
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update_cs_ranges();
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fixup_pci();
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}
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void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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CUBOOT_INIT();
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ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
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serial_console_init();
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platform_ops.fixups = pq2_platform_fixups;
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}
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@ -114,7 +114,7 @@ void __dt_fixup_mac_addresses(u32 startindex, ...)
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#define MAX_ADDR_CELLS 4
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static void get_reg_format(void *node, u32 *naddr, u32 *nsize)
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void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize)
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{
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if (getprop(node, "#address-cells", naddr, 4) != 4)
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*naddr = 2;
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@ -224,7 +224,7 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
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if (!parent)
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return 0;
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get_reg_format(parent, &naddr, &nsize);
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dt_get_reg_format(parent, &naddr, &nsize);
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if (nsize > 2)
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return 0;
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@ -252,7 +252,7 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
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if (!parent)
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break;
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get_reg_format(parent, &naddr, &nsize);
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dt_get_reg_format(parent, &naddr, &nsize);
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buflen = getprop(node, "ranges", prop_buf,
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sizeof(prop_buf));
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@ -89,6 +89,7 @@ extern void flush_cache(void *, unsigned long);
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int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
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int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
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int dt_is_compatible(void *node, const char *compat);
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void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
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static inline void *finddevice(const char *name)
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{
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@ -206,4 +207,12 @@ extern char _initrd_end[];
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extern char _dtb_start[];
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extern char _dtb_end[];
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static inline __attribute__((const))
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int __ilog2_u32(u32 n)
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{
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int bit;
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asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
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return 31 - bit;
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}
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#endif /* _PPC_BOOT_OPS_H_ */
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@ -19,6 +19,7 @@ config EMBEDDED6xx
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config PPC_82xx
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bool "Freescale 82xx"
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depends on 6xx
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select WANT_DEVICE_TREE
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config PPC_83xx
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bool "Freescale 83xx"
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