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blackfin: add spi/sport3/ppi head file for bf60x

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Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
This commit is contained in:
Scott Jiang 2012-05-16 18:08:04 +08:00 committed by Bob Liu
parent 7adede5b9b
commit e578bbdeb8
3 changed files with 493 additions and 0 deletions
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258
arch/blackfin/include/asm/bfin6xx_spi.h Normal file
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@ -0,0 +1,258 @@
/*
* Analog Devices SPI3 controller driver
*
* Copyright (c) 2011 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SPI_CHANNEL_H_
#define _SPI_CHANNEL_H_
#include <linux/types.h>
/* SPI_CONTROL */
#define SPI_CTL_EN 0x00000001 /* Enable */
#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */
#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */
#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */
#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */
#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */
#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */
#define SPI_CTL_LSBF 0x00001000 /* LSB First */
#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */
#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */
#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */
#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */
#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */
#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */
#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */
#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */
#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */
#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */
#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */
/* SPI_RX_CONTROL */
#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */
#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */
#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */
#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */
#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */
#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */
#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */
#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */
#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */
#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */
#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */
#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */
#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */
#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */
#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */
#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */
#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */
#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */
#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */
#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */
#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */
#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */
/* SPI_TX_CONTROL */
#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */
#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */
#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */
#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */
#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */
#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */
#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */
#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */
#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */
#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */
#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */
#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */
#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */
#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */
#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */
#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */
#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */
#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */
#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */
#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */
#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */
#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */
/* SPI_CLOCK */
#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */
/* SPI_DELAY */
#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */
#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */
#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */
/* SPI_SSEL */
#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */
#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */
#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */
#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */
#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */
#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */
#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */
#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */
#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */
#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */
#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */
#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */
#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */
#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */
/* SPI_RWC */
#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */
/* SPI_RWCR */
#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */
/* SPI_TWC */
#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */
/* SPI_TWCR */
#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */
/* SPI_IMASK */
#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */
#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */
#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */
#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
/* SPI_IMASKCL */
#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */
#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */
#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */
#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
/* SPI_IMASKST */
#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */
#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */
#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */
#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
/* SPI_STATUS */
#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */
#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */
#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */
#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */
#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */
#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */
#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */
#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */
#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */
#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */
#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */
#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */
#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */
#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */
#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */
#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */
#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */
#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */
#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */
#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */
#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */
#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */
#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */
#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */
#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */
#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */
/* SPI_ILAT */
#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */
#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */
#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */
#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */
#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */
#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */
#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */
#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */
/* SPI_ILATCL */
#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */
#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */
#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */
#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */
#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */
#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */
#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */
#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
/*
* bfin spi3 registers layout
*/
struct bfin_spi_regs {
u32 revid;
u32 control;
u32 rx_control;
u32 tx_control;
u32 clock;
u32 delay;
u32 ssel;
u32 rwc;
u32 rwcr;
u32 twc;
u32 twcr;
u32 reserved0;
u32 emask;
u32 emaskcl;
u32 emaskst;
u32 reserved1;
u32 status;
u32 elat;
u32 elatcl;
u32 reserved2;
u32 rfifo;
u32 reserved3;
u32 tfifo;
};
#define MAX_CTRL_CS 8 /* cs in spi controller */
/* device.platform_data for SSP controller devices */
struct bfin6xx_spi_master {
u16 num_chipselect;
u16 pin_req[7];
};
/* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning
*/
struct bfin6xx_spi_chip {
u32 control;
u16 cs_chg_udelay; /* Some devices require 16-bit delays */
u32 tx_dummy_val; /* tx value for rx only transfer */
bool enable_dma;
};
#endif /* _SPI_CHANNEL_H_ */

128
arch/blackfin/include/asm/bfin_ppi.h
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@ -10,6 +10,7 @@
#define __ASM_BFIN_PPI_H__
#include <linux/types.h>
#include <asm/blackfin.h>
/*
* All Blackfin system MMRs are padded to 32bits even if the register
@ -48,6 +49,133 @@ struct bfin_eppi_regs {
u32 clip;
};
/*
* bfin eppi3 registers layout
*/
struct bfin_eppi3_regs {
u32 stat;
u32 hcnt;
u32 hdly;
u32 vcnt;
u32 vdly;
u32 frame;
u32 line;
u32 clkdiv;
u32 ctl;
u32 fs1_wlhb;
u32 fs1_paspl;
u32 fs2_wlvb;
u32 fs2_palpf;
u32 imsk;
u32 oddclip;
u32 evenclip;
u32 fs1_dly;
u32 fs2_dly;
u32 ctl2;
};
#undef __BFP
#ifdef EPPI0_CTL2
#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
#endif
#endif

107
arch/blackfin/include/asm/bfin_sport3.h Normal file
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@ -0,0 +1,107 @@
/*
* bfin_sport - Analog Devices BF6XX SPORT registers
*
* Copyright (c) 2012 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _BFIN_SPORT3_H_
#define _BFIN_SPORT3_H_
#include <linux/types.h>
#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrrupt enable select */
#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
struct sport_register {
u32 spctl;
u32 div;
u32 spmctl;
u32 spcs0;
u32 spcs1;
u32 spcs2;
u32 spcs3;
u32 spcnt;
u32 sperrctl;
u32 spmstat;
u32 spctl2;
u32 txa;
u32 rxa;
u32 txb;
u32 rxb;
u32 revid;
};
struct bfin_snd_platform_data {
const unsigned short *pin_req;
};
#endif