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m68knommu: mask off all interrupts in ColdFire intc-simr controller

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The ColdFire intc-simr interrupt controller should mask off all
interrupt sources at init time. Doing it here instead of separately
in each platform setup.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2009-05-06 14:28:25 +10:00
parent 91b1b94f88
commit e47cc3d6ac
2 changed files with 5 additions and 33 deletions
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33
arch/m68k/include/asm/m532xsim.h
View file

@ -56,8 +56,6 @@
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
#define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */
#define MCFINTC0_SIMR 0xFC04801C #define MCFINTC0_SIMR 0xFC04801C
#define MCFINTC0_CIMR 0xFC04801D #define MCFINTC0_CIMR 0xFC04801D
#define MCFINTC0_ICR0 0xFC048040 #define MCFINTC0_ICR0 0xFC048040
@ -69,37 +67,6 @@
#define MCFSIM_ICR_TIMER2 (0xFC048040+33) #define MCFSIM_ICR_TIMER2 (0xFC048040+33)
/*
* Macro to set IMR register. It is 32 bits on the 5307.
*/
#define mcf_getimr() \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
#define mcf_setimr(imr) \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
#define mcf_getipr() \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
#define mcf_getiprl() \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL))
#define mcf_getiprh() \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH))
#define mcf_enable_irq0(irq) \
*((volatile unsigned char *) (MCFINTC0_CIMR)) = (irq);
#define mcf_enable_irq1(irq) \
*((volatile unsigned char *) (MCFINTC1_CIMR)) = (irq);
#define mcf_disable_irq0(irq) \
*((volatile unsigned char *) (MCFINTC0_SIMR)) = (irq);
#define mcf_disable_irq1(irq) \
*((volatile unsigned char *) (MCFINTC1_SIMR)) = (irq);
/* /*
* Define the Cache register flags. * Define the Cache register flags.
*/ */

5
arch/m68knommu/platform/coldfire/intc-simr.c
View file

@ -62,6 +62,11 @@ void __init init_IRQ(void)
init_vectors(); init_vectors();
/* Mask all interrupt sources */
__raw_writeb(0xff, MCFINTC0_SIMR);
if (MCFINTC1_SIMR)
__raw_writeb(0xff, MCFINTC1_SIMR);
for (irq = 0; (irq < NR_IRQS); irq++) { for (irq = 0; (irq < NR_IRQS); irq++) {
irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = NULL; irq_desc[irq].action = NULL;