drm/nouveau: create grctx on the fly on all chipsets
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
eeb9cc015f
commit
e457acaed4
4 changed files with 14 additions and 12 deletions
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@ -121,7 +121,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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uint32_t vram_handle, uint32_t gart_handle)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_channel *chan;
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unsigned long flags;
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@ -202,15 +201,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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/* disable the fifo caches */
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pfifo->reassign(dev, false);
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/* Create a graphics context for new channel */
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if (dev_priv->card_type < NV_50) {
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ret = pgraph->create_context(chan);
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if (ret) {
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nouveau_channel_put(&chan);
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return ret;
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}
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}
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/* Construct inital RAMFC for new channel */
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ret = pfifo->create_context(chan);
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if (ret) {
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@ -651,7 +651,8 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
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}
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break;
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case NVOBJ_ENGINE_GR:
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if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) {
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if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) ||
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(dev_priv->card_type < NV_20 && !chan->pgraph_ctx)) {
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struct nouveau_pgraph_engine *pgraph =
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&dev_priv->engine.graph;
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@ -64,7 +64,6 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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0x30000000 /* no idea.. */);
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nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4);
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nv_wi32(dev, fc + 60, 0x0001FFFF);
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/* enable the fifo dma operation */
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@ -62,6 +62,7 @@ nv40_graph_create_context(struct nouveau_channel *chan)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_grctx ctx = {};
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unsigned long flags;
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int ret;
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ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
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@ -76,6 +77,17 @@ nv40_graph_create_context(struct nouveau_channel *chan)
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nv40_grctx_init(&ctx);
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nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
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/* init grctx pointer in ramfc, and on PFIFO if channel is
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* already active there
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*/
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);
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nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
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if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
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nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);
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nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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return 0;
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}
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