Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Alex writes: "This is the current set of radeon fixes for 3.6. Nothing too major. Highlights: - fix vbios fetch on pure uefi systems - fix vbios fetch on thunderbolt systems - MSAA fixes - lockup timeout fix - modesetting fix" * 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux: drm/radeon/ss: use num_crtc rather than hardcoded 6 Revert "drm/radeon: fix bo creation retry path" drm/radeon: split ATRM support out from the ATPX handler (v3) drm/radeon: convert radeon vfct code to use acpi_get_table_with_size ACPI: export symbol acpi_get_table_with_size drm/radeon: implement ACPI VFCT vbios fetch (v3) drm/radeon/kms: extend the Fujitsu D3003-S2 board connector quirk to cover later silicon stepping drm/radeon: fix checking of MSAA renderbuffers on r600-r700 drm/radeon: allow CMASK and FMASK in the CS checker on r600-r700 drm/radeon: init lockup timeout on ring init drm/radeon: avoid turning off spread spectrum for used pll
This commit is contained in:
Dave Airlie
commit
e2be2cd804
12 changed files with 267 additions and 107 deletions
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@ -387,6 +387,7 @@ acpi_get_table_with_size(char *signature,
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return (AE_NOT_FOUND);
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}
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ACPI_EXPORT_SYMBOL(acpi_get_table_with_size)
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acpi_status
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acpi_get_table(char *signature,
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@ -444,11 +444,28 @@ union atom_enable_ss {
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static void atombios_crtc_program_ss(struct radeon_device *rdev,
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int enable,
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int pll_id,
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int crtc_id,
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struct radeon_atom_ss *ss)
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{
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unsigned i;
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int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
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union atom_enable_ss args;
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if (!enable) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->mode_info.crtcs[i] &&
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rdev->mode_info.crtcs[i]->enabled &&
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i != crtc_id &&
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pll_id == rdev->mode_info.crtcs[i]->pll_id) {
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/* one other crtc is using this pll don't turn
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* off spread spectrum as it might turn off
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* display on active crtc
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*/
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return;
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}
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}
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}
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memset(&args, 0, sizeof(args));
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if (ASIC_IS_DCE5(rdev)) {
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@ -1028,7 +1045,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
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radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
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&ref_div, &post_div);
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atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
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atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
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atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
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encoder_mode, radeon_encoder->encoder_id, mode->clock,
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@ -1051,7 +1068,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
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ss.step = step_size;
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}
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atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
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atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
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}
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}
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@ -1572,11 +1589,11 @@ void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
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ASIC_INTERNAL_SS_ON_DCPLL,
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rdev->clock.default_dispclk);
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if (ss_enabled)
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atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
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atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
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/* XXX: DCE5, make sure voltage, dispclk is high enough */
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atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
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if (ss_enabled)
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atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
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atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
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}
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}
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@ -47,13 +47,17 @@ struct r600_cs_track {
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u32 npipes;
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/* value we track */
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u32 sq_config;
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u32 log_nsamples;
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u32 nsamples;
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u32 cb_color_base_last[8];
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struct radeon_bo *cb_color_bo[8];
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u64 cb_color_bo_mc[8];
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u32 cb_color_bo_offset[8];
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struct radeon_bo *cb_color_frag_bo[8]; /* unused */
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struct radeon_bo *cb_color_tile_bo[8]; /* unused */
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u64 cb_color_bo_offset[8];
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struct radeon_bo *cb_color_frag_bo[8];
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u64 cb_color_frag_offset[8];
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struct radeon_bo *cb_color_tile_bo[8];
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u64 cb_color_tile_offset[8];
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u32 cb_color_mask[8];
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u32 cb_color_info[8];
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u32 cb_color_view[8];
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u32 cb_color_size_idx[8]; /* unused */
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@ -349,10 +353,6 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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unsigned array_mode;
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u32 format;
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if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
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dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
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return -EINVAL;
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}
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size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
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format = G_0280A0_FORMAT(track->cb_color_info[i]);
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if (!r600_fmt_is_valid_color(format)) {
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@ -420,7 +420,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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}
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/* check offset */
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tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
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tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
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r600_fmt_get_blocksize(format) * track->nsamples;
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switch (array_mode) {
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default:
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case V_0280A0_ARRAY_LINEAR_GENERAL:
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@ -441,7 +442,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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* broken userspace.
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*/
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} else {
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dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n",
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dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
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__func__, i, array_mode,
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track->cb_color_bo_offset[i], tmp,
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radeon_bo_size(track->cb_color_bo[i]),
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@ -458,6 +459,51 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
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S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
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ib[track->cb_color_size_idx[i]] = tmp;
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/* FMASK/CMASK */
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switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
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case V_0280A0_TILE_DISABLE:
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break;
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case V_0280A0_FRAG_ENABLE:
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if (track->nsamples > 1) {
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uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
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/* the tile size is 8x8, but the size is in units of bits.
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* for bytes, do just * 8. */
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uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
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if (bytes + track->cb_color_frag_offset[i] >
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radeon_bo_size(track->cb_color_frag_bo[i])) {
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dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
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"(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
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__func__, tile_max, bytes,
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track->cb_color_frag_offset[i],
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radeon_bo_size(track->cb_color_frag_bo[i]));
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return -EINVAL;
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}
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}
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/* fall through */
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case V_0280A0_CLEAR_ENABLE:
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{
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uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
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/* One block = 128x128 pixels, one 8x8 tile has 4 bits..
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* (128*128) / (8*8) / 2 = 128 bytes per block. */
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uint32_t bytes = (block_max + 1) * 128;
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if (bytes + track->cb_color_tile_offset[i] >
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radeon_bo_size(track->cb_color_tile_bo[i])) {
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dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
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"(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
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__func__, block_max, bytes,
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track->cb_color_tile_offset[i],
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radeon_bo_size(track->cb_color_tile_bo[i]));
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return -EINVAL;
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}
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break;
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}
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default:
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dev_warn(p->dev, "%s invalid tile mode\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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@ -566,7 +612,7 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
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ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
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nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
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tmp = ntiles * bpe * 64 * nviews;
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tmp = ntiles * bpe * 64 * nviews * track->nsamples;
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if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
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dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
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array_mode,
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@ -1231,6 +1277,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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break;
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case R_028C04_PA_SC_AA_CONFIG:
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tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
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track->log_nsamples = tmp;
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track->nsamples = 1 << tmp;
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track->cb_dirty = true;
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break;
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@ -1312,16 +1359,21 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
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return -EINVAL;
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}
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ib[idx] = track->cb_color_base_last[tmp];
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track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
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track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
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ib[idx] = track->cb_color_base_last[tmp];
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} else {
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r = r600_cs_packet_next_reloc(p, &reloc);
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if (r) {
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dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
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return -EINVAL;
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}
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->cb_color_frag_bo[tmp] = reloc->robj;
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track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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}
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if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
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track->cb_dirty = true;
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}
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break;
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case R_0280C0_CB_COLOR0_TILE:
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@ -1338,16 +1390,35 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
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return -EINVAL;
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}
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ib[idx] = track->cb_color_base_last[tmp];
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track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
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track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
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ib[idx] = track->cb_color_base_last[tmp];
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} else {
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r = r600_cs_packet_next_reloc(p, &reloc);
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if (r) {
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dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
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return -EINVAL;
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}
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->cb_color_tile_bo[tmp] = reloc->robj;
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track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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}
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if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
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track->cb_dirty = true;
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}
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break;
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case R_028100_CB_COLOR0_MASK:
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case R_028104_CB_COLOR1_MASK:
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case R_028108_CB_COLOR2_MASK:
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case R_02810C_CB_COLOR3_MASK:
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case R_028110_CB_COLOR4_MASK:
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case R_028114_CB_COLOR5_MASK:
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case R_028118_CB_COLOR6_MASK:
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case R_02811C_CB_COLOR7_MASK:
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tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
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track->cb_color_mask[tmp] = ib[idx];
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if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
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track->cb_dirty = true;
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}
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break;
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case CB_COLOR0_BASE:
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@ -1492,7 +1563,7 @@ unsigned r600_mip_minify(unsigned size, unsigned level)
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}
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static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
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unsigned w0, unsigned h0, unsigned d0, unsigned format,
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unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
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unsigned block_align, unsigned height_align, unsigned base_align,
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unsigned *l0_size, unsigned *mipmap_size)
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{
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@ -1520,7 +1591,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
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depth = r600_mip_minify(d0, i);
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size = nbx * nby * blocksize;
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size = nbx * nby * blocksize * nsamples;
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if (nfaces)
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size *= nfaces;
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else
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@ -1672,7 +1743,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
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nfaces = larray - barray + 1;
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}
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r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
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r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
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pitch_align, height_align, base_align,
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&l0_size, &mipmap_size);
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/* using get ib will give us the offset into the texture bo */
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@ -92,6 +92,20 @@
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#define R_028094_CB_COLOR5_VIEW 0x028094
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#define R_028098_CB_COLOR6_VIEW 0x028098
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#define R_02809C_CB_COLOR7_VIEW 0x02809C
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#define R_028100_CB_COLOR0_MASK 0x028100
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#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
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#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
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#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
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#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
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#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
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#define C_028100_FMASK_TILE_MAX 0x00000FFF
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#define R_028104_CB_COLOR1_MASK 0x028104
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#define R_028108_CB_COLOR2_MASK 0x028108
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#define R_02810C_CB_COLOR3_MASK 0x02810C
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#define R_028110_CB_COLOR4_MASK 0x028110
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#define R_028114_CB_COLOR5_MASK 0x028114
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#define R_028118_CB_COLOR6_MASK 0x028118
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#define R_02811C_CB_COLOR7_MASK 0x02811C
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#define CB_COLOR0_INFO 0x280a0
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# define CB_FORMAT(x) ((x) << 2)
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# define CB_ARRAY_MODE(x) ((x) << 8)
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|
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@ -1400,6 +1414,9 @@
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#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
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#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
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#define C_0280A0_TILE_MODE 0xFFF3FFFF
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#define V_0280A0_TILE_DISABLE 0
|
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#define V_0280A0_CLEAR_ENABLE 1
|
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#define V_0280A0_FRAG_ENABLE 2
|
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#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
|
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#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
|
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#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
|
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|
|
|
|||
|
|
@ -142,21 +142,6 @@ struct radeon_device;
|
|||
/*
|
||||
* BIOS.
|
||||
*/
|
||||
#define ATRM_BIOS_PAGE 4096
|
||||
|
||||
#if defined(CONFIG_VGA_SWITCHEROO)
|
||||
bool radeon_atrm_supported(struct pci_dev *pdev);
|
||||
int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
|
||||
#else
|
||||
static inline bool radeon_atrm_supported(struct pci_dev *pdev)
|
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{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
|
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return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
bool radeon_get_bios(struct radeon_device *rdev);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -452,7 +452,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
|
|||
}
|
||||
|
||||
/* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
|
||||
if ((dev->pdev->device == 0x9802) &&
|
||||
if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
|
||||
(dev->pdev->subsystem_vendor == 0x1734) &&
|
||||
(dev->pdev->subsystem_device == 0x11bd)) {
|
||||
if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
|
||||
|
|
|
|||
|
|
@ -30,57 +30,8 @@ static struct radeon_atpx_priv {
|
|||
/* handle for device - and atpx */
|
||||
acpi_handle dhandle;
|
||||
acpi_handle atpx_handle;
|
||||
acpi_handle atrm_handle;
|
||||
} radeon_atpx_priv;
|
||||
|
||||
/* retrieve the ROM in 4k blocks */
|
||||
static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
|
||||
int offset, int len)
|
||||
{
|
||||
acpi_status status;
|
||||
union acpi_object atrm_arg_elements[2], *obj;
|
||||
struct acpi_object_list atrm_arg;
|
||||
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
|
||||
|
||||
atrm_arg.count = 2;
|
||||
atrm_arg.pointer = &atrm_arg_elements[0];
|
||||
|
||||
atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
|
||||
atrm_arg_elements[0].integer.value = offset;
|
||||
|
||||
atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
|
||||
atrm_arg_elements[1].integer.value = len;
|
||||
|
||||
status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
|
||||
if (ACPI_FAILURE(status)) {
|
||||
printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
obj = (union acpi_object *)buffer.pointer;
|
||||
memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
|
||||
len = obj->buffer.length;
|
||||
kfree(buffer.pointer);
|
||||
return len;
|
||||
}
|
||||
|
||||
bool radeon_atrm_supported(struct pci_dev *pdev)
|
||||
{
|
||||
/* get the discrete ROM only via ATRM */
|
||||
if (!radeon_atpx_priv.atpx_detected)
|
||||
return false;
|
||||
|
||||
if (radeon_atpx_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev))
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len)
|
||||
{
|
||||
return radeon_atrm_call(radeon_atpx_priv.atrm_handle, bios, offset, len);
|
||||
}
|
||||
|
||||
static int radeon_atpx_get_version(acpi_handle handle)
|
||||
{
|
||||
acpi_status status;
|
||||
|
|
@ -198,7 +149,7 @@ static int radeon_atpx_power_state(enum vga_switcheroo_client_id id,
|
|||
|
||||
static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
|
||||
{
|
||||
acpi_handle dhandle, atpx_handle, atrm_handle;
|
||||
acpi_handle dhandle, atpx_handle;
|
||||
acpi_status status;
|
||||
|
||||
dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
|
||||
|
|
@ -209,13 +160,8 @@ static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
|
|||
if (ACPI_FAILURE(status))
|
||||
return false;
|
||||
|
||||
status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
|
||||
if (ACPI_FAILURE(status))
|
||||
return false;
|
||||
|
||||
radeon_atpx_priv.dhandle = dhandle;
|
||||
radeon_atpx_priv.atpx_handle = atpx_handle;
|
||||
radeon_atpx_priv.atrm_handle = atrm_handle;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
|
||||
#include <linux/vga_switcheroo.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/acpi.h>
|
||||
/*
|
||||
* BIOS.
|
||||
*/
|
||||
|
|
@ -98,16 +99,81 @@ static bool radeon_read_bios(struct radeon_device *rdev)
|
|||
return true;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
/* ATRM is used to get the BIOS on the discrete cards in
|
||||
* dual-gpu systems.
|
||||
*/
|
||||
/* retrieve the ROM in 4k blocks */
|
||||
#define ATRM_BIOS_PAGE 4096
|
||||
/**
|
||||
* radeon_atrm_call - fetch a chunk of the vbios
|
||||
*
|
||||
* @atrm_handle: acpi ATRM handle
|
||||
* @bios: vbios image pointer
|
||||
* @offset: offset of vbios image data to fetch
|
||||
* @len: length of vbios image data to fetch
|
||||
*
|
||||
* Executes ATRM to fetch a chunk of the discrete
|
||||
* vbios image on PX systems (all asics).
|
||||
* Returns the length of the buffer fetched.
|
||||
*/
|
||||
static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
|
||||
int offset, int len)
|
||||
{
|
||||
acpi_status status;
|
||||
union acpi_object atrm_arg_elements[2], *obj;
|
||||
struct acpi_object_list atrm_arg;
|
||||
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
|
||||
|
||||
atrm_arg.count = 2;
|
||||
atrm_arg.pointer = &atrm_arg_elements[0];
|
||||
|
||||
atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
|
||||
atrm_arg_elements[0].integer.value = offset;
|
||||
|
||||
atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
|
||||
atrm_arg_elements[1].integer.value = len;
|
||||
|
||||
status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
|
||||
if (ACPI_FAILURE(status)) {
|
||||
printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
obj = (union acpi_object *)buffer.pointer;
|
||||
memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
|
||||
len = obj->buffer.length;
|
||||
kfree(buffer.pointer);
|
||||
return len;
|
||||
}
|
||||
|
||||
static bool radeon_atrm_get_bios(struct radeon_device *rdev)
|
||||
{
|
||||
int ret;
|
||||
int size = 256 * 1024;
|
||||
int i;
|
||||
struct pci_dev *pdev = NULL;
|
||||
acpi_handle dhandle, atrm_handle;
|
||||
acpi_status status;
|
||||
bool found = false;
|
||||
|
||||
if (!radeon_atrm_supported(rdev->pdev))
|
||||
/* ATRM is for the discrete card only */
|
||||
if (rdev->flags & RADEON_IS_IGP)
|
||||
return false;
|
||||
|
||||
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
|
||||
dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
|
||||
if (!dhandle)
|
||||
continue;
|
||||
|
||||
status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
|
||||
if (!ACPI_FAILURE(status)) {
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!found)
|
||||
return false;
|
||||
|
||||
rdev->bios = kmalloc(size, GFP_KERNEL);
|
||||
|
|
@ -117,7 +183,8 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
|
||||
ret = radeon_atrm_get_bios_chunk(rdev->bios,
|
||||
ret = radeon_atrm_call(atrm_handle,
|
||||
rdev->bios,
|
||||
(i * ATRM_BIOS_PAGE),
|
||||
ATRM_BIOS_PAGE);
|
||||
if (ret < ATRM_BIOS_PAGE)
|
||||
|
|
@ -130,6 +197,12 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
|
|||
}
|
||||
return true;
|
||||
}
|
||||
#else
|
||||
static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
static bool ni_read_disabled_bios(struct radeon_device *rdev)
|
||||
{
|
||||
|
|
@ -476,6 +549,61 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev)
|
|||
return legacy_read_disabled_bios(rdev);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
|
||||
{
|
||||
bool ret = false;
|
||||
struct acpi_table_header *hdr;
|
||||
acpi_size tbl_size;
|
||||
UEFI_ACPI_VFCT *vfct;
|
||||
GOP_VBIOS_CONTENT *vbios;
|
||||
VFCT_IMAGE_HEADER *vhdr;
|
||||
|
||||
if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
|
||||
return false;
|
||||
if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
|
||||
DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
vfct = (UEFI_ACPI_VFCT *)hdr;
|
||||
if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
|
||||
DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
|
||||
vhdr = &vbios->VbiosHeader;
|
||||
DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
|
||||
vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
|
||||
vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
|
||||
|
||||
if (vhdr->PCIBus != rdev->pdev->bus->number ||
|
||||
vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
|
||||
vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
|
||||
vhdr->VendorID != rdev->pdev->vendor ||
|
||||
vhdr->DeviceID != rdev->pdev->device) {
|
||||
DRM_INFO("ACPI VFCT table is not for this card\n");
|
||||
goto out_unmap;
|
||||
};
|
||||
|
||||
if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
|
||||
DRM_ERROR("ACPI VFCT image truncated\n");
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
|
||||
ret = !!rdev->bios;
|
||||
|
||||
out_unmap:
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
bool radeon_get_bios(struct radeon_device *rdev)
|
||||
{
|
||||
|
|
@ -483,6 +611,8 @@ bool radeon_get_bios(struct radeon_device *rdev)
|
|||
uint16_t tmp;
|
||||
|
||||
r = radeon_atrm_get_bios(rdev);
|
||||
if (r == false)
|
||||
r = radeon_acpi_vfct_bios(rdev);
|
||||
if (r == false)
|
||||
r = igp_read_bios_from_vram(rdev);
|
||||
if (r == false)
|
||||
|
|
|
|||
|
|
@ -62,9 +62,10 @@
|
|||
* 2.18.0 - r600-eg: allow "invalid" DB formats
|
||||
* 2.19.0 - r600-eg: MSAA textures
|
||||
* 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
|
||||
* 2.21.0 - r600-r700: FMASK and CMASK
|
||||
*/
|
||||
#define KMS_DRIVER_MAJOR 2
|
||||
#define KMS_DRIVER_MINOR 20
|
||||
#define KMS_DRIVER_MINOR 21
|
||||
#define KMS_DRIVER_PATCHLEVEL 0
|
||||
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
|
||||
int radeon_driver_unload_kms(struct drm_device *dev);
|
||||
|
|
|
|||
|
|
@ -132,6 +132,7 @@ int radeon_bo_create(struct radeon_device *rdev,
|
|||
acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
|
||||
sizeof(struct radeon_bo));
|
||||
|
||||
retry:
|
||||
bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
|
||||
if (bo == NULL)
|
||||
return -ENOMEM;
|
||||
|
|
@ -145,8 +146,6 @@ int radeon_bo_create(struct radeon_device *rdev,
|
|||
bo->surface_reg = -1;
|
||||
INIT_LIST_HEAD(&bo->list);
|
||||
INIT_LIST_HEAD(&bo->va);
|
||||
|
||||
retry:
|
||||
radeon_ttm_placement_from_domain(bo, domain);
|
||||
/* Kernel allocation are uninterruptible */
|
||||
down_read(&rdev->pm.mclk_lock);
|
||||
|
|
|
|||
|
|
@ -706,6 +706,7 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig
|
|||
if (radeon_debugfs_ring_init(rdev, ring)) {
|
||||
DRM_ERROR("Failed to register debugfs file for rings !\n");
|
||||
}
|
||||
radeon_ring_lockup_update(ring);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -744,14 +744,6 @@ r600 0x9400
|
|||
0x00028C38 CB_CLRCMP_DST
|
||||
0x00028C3C CB_CLRCMP_MSK
|
||||
0x00028C34 CB_CLRCMP_SRC
|
||||
0x00028100 CB_COLOR0_MASK
|
||||
0x00028104 CB_COLOR1_MASK
|
||||
0x00028108 CB_COLOR2_MASK
|
||||
0x0002810C CB_COLOR3_MASK
|
||||
0x00028110 CB_COLOR4_MASK
|
||||
0x00028114 CB_COLOR5_MASK
|
||||
0x00028118 CB_COLOR6_MASK
|
||||
0x0002811C CB_COLOR7_MASK
|
||||
0x00028808 CB_COLOR_CONTROL
|
||||
0x0002842C CB_FOG_BLUE
|
||||
0x00028428 CB_FOG_GREEN
|
||||
|
|
|
|||
Loading…
Reference in a new issue