iwlwifi: add TX aggregation code for 5000 HW
This patch adds TX aggregation handler for 5000 HW. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Tomas Winkler
John W. Linville
parent
7f3e4bb60f
commit
e26e47d944
1 changed files with 132 additions and 0 deletions
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@ -41,6 +41,7 @@
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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#include "iwl-sta.h"
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#include "iwl-helpers.h"
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#include "iwl-5000-hw.h"
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@ -976,6 +977,135 @@ static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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}
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}
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static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
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u16 txq_id)
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{
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u32 tbl_dw_addr;
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u32 tbl_dw;
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u16 scd_q2ratid;
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scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
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tbl_dw_addr = priv->scd_base_addr +
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IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
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tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
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if (txq_id & 0x1)
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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else
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
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return 0;
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}
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static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
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{
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/* Simply stop the queue, but don't change any configuration;
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* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
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iwl_write_prph(priv,
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IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
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(0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
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(1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
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}
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static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
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int tx_fifo, int sta_id, int tid, u16 ssn_idx)
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{
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unsigned long flags;
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int ret;
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u16 ra_tid;
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if (IWL50_FIRST_AMPDU_QUEUE > txq_id)
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IWL_WARNING("queue number too small: %d, must be > %d\n",
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txq_id, IWL50_FIRST_AMPDU_QUEUE);
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ra_tid = BUILD_RAxTID(sta_id, tid);
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/* Modify device's station table to Tx this TID */
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iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
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spin_lock_irqsave(&priv->lock, flags);
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ret = iwl_grab_nic_access(priv);
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if (ret) {
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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/* Stop this Tx queue before configuring it */
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iwl5000_tx_queue_stop_scheduler(priv, txq_id);
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/* Map receiver-address / traffic-ID to this queue */
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iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
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/* Set this queue as a chain-building queue */
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iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
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/* enable aggregations for the queue */
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iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
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/* Place first TFD at index corresponding to start sequence number.
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* Assumes that ssn_idx is valid (!= 0xFFF) */
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priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
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/* Set up Tx window size and frame limit for this queue */
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
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sizeof(u32),
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((SCD_WIN_SIZE <<
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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((SCD_FRAME_LIMIT <<
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
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/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
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u16 ssn_idx, u8 tx_fifo)
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{
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int ret;
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if (IWL50_FIRST_AMPDU_QUEUE > txq_id) {
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IWL_WARNING("queue number too small: %d, must be > %d\n",
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txq_id, IWL50_FIRST_AMPDU_QUEUE);
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return -EINVAL;
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}
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ret = iwl_grab_nic_access(priv);
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if (ret)
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return ret;
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iwl5000_tx_queue_stop_scheduler(priv, txq_id);
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iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
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priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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/* supposes that ssn_idx is valid (!= 0xFFF) */
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iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
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iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl_txq_ctx_deactivate(priv, txq_id);
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iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
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iwl_release_nic_access(priv);
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return 0;
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}
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static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
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{
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u16 size = (u16)sizeof(struct iwl_addsta_cmd);
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@ -1319,6 +1449,8 @@ static struct iwl_lib_ops iwl5000_lib = {
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwl5000_txq_set_sched,
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.txq_agg_enable = iwl5000_txq_agg_enable,
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.txq_agg_disable = iwl5000_txq_agg_disable,
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.rx_handler_setup = iwl5000_rx_handler_setup,
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.setup_deferred_work = iwl5000_setup_deferred_work,
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.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
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