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NTB: Split ntb_hw_intel and ntb_transport drivers

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Change ntb_hw_intel to use the new NTB hardware abstraction layer.

Split ntb_transport into its own driver.  Change it to use the new NTB
hardware abstraction layer.

Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
This commit is contained in:
Allen Hubbe 2015-04-09 10:33:20 -04:00 committed by Jon Mason
parent a1bd3baeb2
commit e26a5843f7
13 changed files with 2958 additions and 2564 deletions
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26
Documentation/ntb.txt
View file

@ -26,7 +26,33 @@ as ntb hardware, or hardware drivers, are inserted and removed. The
registration uses the Linux Device framework, so it should feel familiar to registration uses the Linux Device framework, so it should feel familiar to
anyone who has written a pci driver. anyone who has written a pci driver.
### NTB Transport Client (ntb\_transport) and NTB Netdev (ntb\_netdev)
The primary client for NTB is the Transport client, used in tandem with NTB
Netdev. These drivers function together to create a logical link to the peer,
across the ntb, to exchange packets of network data. The Transport client
establishes a logical link to the peer, and creates queue pairs to exchange
messages and data. The NTB Netdev then creates an ethernet device using a
Transport queue pair. Network data is copied between socket buffers and the
Transport queue pair buffer. The Transport client may be used for other things
besides Netdev, however no other applications have yet been written.
## NTB Hardware Drivers ## NTB Hardware Drivers
NTB hardware drivers should register devices with the NTB core driver. After NTB hardware drivers should register devices with the NTB core driver. After
registering, clients probe and remove functions will be called. registering, clients probe and remove functions will be called.
### NTB Intel Hardware Driver (ntb\_hw\_intel)
The Intel hardware driver supports NTB on Xeon and Atom CPUs.
Module Parameters:
* b2b\_mw\_idx - If the peer ntb is to be accessed via a memory window, then use
this memory window to access the peer ntb. A value of zero or positive
starts from the first mw idx, and a negative value starts from the last
mw idx. Both sides MUST set the same value here! The default value is
`-1`.
* b2b\_mw\_share - If the peer ntb is to be accessed via a memory window, and if
the memory window is large enough, still allow the client to use the
second half of the memory window for address translation to the peer.

8
MAINTAINERS
View file

@ -7007,6 +7007,14 @@ F: drivers/net/ntb_netdev.c
F: include/linux/ntb.h F: include/linux/ntb.h
F: include/linux/ntb_transport.h F: include/linux/ntb_transport.h
NTB INTEL DRIVER
M: Jon Mason <jdmason@kudzu.us>
M: Dave Jiang <dave.jiang@intel.com>
S: Supported
W: https://github.com/jonmason/ntb/wiki
T: git git://github.com/jonmason/ntb.git
F: drivers/ntb/hw/intel/
NTFS FILESYSTEM NTFS FILESYSTEM
M: Anton Altaparmakov <anton@tuxera.com> M: Anton Altaparmakov <anton@tuxera.com>
L: linux-ntfs-dev@lists.sourceforge.net L: linux-ntfs-dev@lists.sourceforge.net

54
drivers/net/ntb_netdev.c
View file

@ -5,6 +5,7 @@
* GPL LICENSE SUMMARY * GPL LICENSE SUMMARY
* *
* Copyright(c) 2012 Intel Corporation. All rights reserved. * Copyright(c) 2012 Intel Corporation. All rights reserved.
* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as * it under the terms of version 2 of the GNU General Public License as
@ -13,6 +14,7 @@
* BSD LICENSE * BSD LICENSE
* *
* Copyright(c) 2012 Intel Corporation. All rights reserved. * Copyright(c) 2012 Intel Corporation. All rights reserved.
* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -40,7 +42,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
* Intel PCIe NTB Network Linux driver * PCIe NTB Network Linux driver
* *
* Contact Information: * Contact Information:
* Jon Mason <jon.mason@intel.com> * Jon Mason <jon.mason@intel.com>
@ -49,6 +51,7 @@
#include <linux/ethtool.h> #include <linux/ethtool.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/ntb.h>
#include <linux/ntb_transport.h> #include <linux/ntb_transport.h>
#define NTB_NETDEV_VER "0.7" #define NTB_NETDEV_VER "0.7"
@ -70,26 +73,19 @@ struct ntb_netdev {
static LIST_HEAD(dev_list); static LIST_HEAD(dev_list);
static void ntb_netdev_event_handler(void *data, int status) static void ntb_netdev_event_handler(void *data, int link_is_up)
{ {
struct net_device *ndev = data; struct net_device *ndev = data;
struct ntb_netdev *dev = netdev_priv(ndev); struct ntb_netdev *dev = netdev_priv(ndev);
netdev_dbg(ndev, "Event %x, Link %x\n", status, netdev_dbg(ndev, "Event %x, Link %x\n", link_is_up,
ntb_transport_link_query(dev->qp)); ntb_transport_link_query(dev->qp));
switch (status) { if (link_is_up) {
case NTB_LINK_DOWN: if (ntb_transport_link_query(dev->qp))
netif_carrier_on(ndev);
} else {
netif_carrier_off(ndev); netif_carrier_off(ndev);
break;
case NTB_LINK_UP:
if (!ntb_transport_link_query(dev->qp))
return;
netif_carrier_on(ndev);
break;
default:
netdev_warn(ndev, "Unsupported event type %d\n", status);
} }
} }
@ -160,8 +156,6 @@ static netdev_tx_t ntb_netdev_start_xmit(struct sk_buff *skb,
struct ntb_netdev *dev = netdev_priv(ndev); struct ntb_netdev *dev = netdev_priv(ndev);
int rc; int rc;
netdev_dbg(ndev, "%s: skb len %d\n", __func__, skb->len);
rc = ntb_transport_tx_enqueue(dev->qp, skb, skb->data, skb->len); rc = ntb_transport_tx_enqueue(dev->qp, skb, skb->data, skb->len);
if (rc) if (rc)
goto err; goto err;
@ -322,20 +316,26 @@ static const struct ntb_queue_handlers ntb_netdev_handlers = {
.event_handler = ntb_netdev_event_handler, .event_handler = ntb_netdev_event_handler,
}; };
static int ntb_netdev_probe(struct pci_dev *pdev) static int ntb_netdev_probe(struct device *client_dev)
{ {
struct ntb_dev *ntb;
struct net_device *ndev; struct net_device *ndev;
struct pci_dev *pdev;
struct ntb_netdev *dev; struct ntb_netdev *dev;
int rc; int rc;
ndev = alloc_etherdev(sizeof(struct ntb_netdev)); ntb = dev_ntb(client_dev->parent);
pdev = ntb->pdev;
if (!pdev)
return -ENODEV;
ndev = alloc_etherdev(sizeof(*dev));
if (!ndev) if (!ndev)
return -ENOMEM; return -ENOMEM;
dev = netdev_priv(ndev); dev = netdev_priv(ndev);
dev->ndev = ndev; dev->ndev = ndev;
dev->pdev = pdev; dev->pdev = pdev;
BUG_ON(!dev->pdev);
ndev->features = NETIF_F_HIGHDMA; ndev->features = NETIF_F_HIGHDMA;
ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
@ -349,7 +349,8 @@ static int ntb_netdev_probe(struct pci_dev *pdev)
ndev->netdev_ops = &ntb_netdev_ops; ndev->netdev_ops = &ntb_netdev_ops;
ndev->ethtool_ops = &ntb_ethtool_ops; ndev->ethtool_ops = &ntb_ethtool_ops;
dev->qp = ntb_transport_create_queue(ndev, pdev, &ntb_netdev_handlers); dev->qp = ntb_transport_create_queue(ndev, client_dev,
&ntb_netdev_handlers);
if (!dev->qp) { if (!dev->qp) {
rc = -EIO; rc = -EIO;
goto err; goto err;
@ -372,12 +373,17 @@ static int ntb_netdev_probe(struct pci_dev *pdev)
return rc; return rc;
} }
static void ntb_netdev_remove(struct pci_dev *pdev) static void ntb_netdev_remove(struct device *client_dev)
{ {
struct ntb_dev *ntb;
struct net_device *ndev; struct net_device *ndev;
struct pci_dev *pdev;
struct ntb_netdev *dev; struct ntb_netdev *dev;
bool found = false; bool found = false;
ntb = dev_ntb(client_dev->parent);
pdev = ntb->pdev;
list_for_each_entry(dev, &dev_list, list) { list_for_each_entry(dev, &dev_list, list) {
if (dev->pdev == pdev) { if (dev->pdev == pdev) {
found = true; found = true;
@ -396,7 +402,7 @@ static void ntb_netdev_remove(struct pci_dev *pdev)
free_netdev(ndev); free_netdev(ndev);
} }
static struct ntb_client ntb_netdev_client = { static struct ntb_transport_client ntb_netdev_client = {
.driver.name = KBUILD_MODNAME, .driver.name = KBUILD_MODNAME,
.driver.owner = THIS_MODULE, .driver.owner = THIS_MODULE,
.probe = ntb_netdev_probe, .probe = ntb_netdev_probe,
@ -407,7 +413,7 @@ static int __init ntb_netdev_init_module(void)
{ {
int rc; int rc;
rc = ntb_register_client_dev(KBUILD_MODNAME); rc = ntb_transport_register_client_dev(KBUILD_MODNAME);
if (rc) if (rc)
return rc; return rc;
return ntb_transport_register_client(&ntb_netdev_client); return ntb_transport_register_client(&ntb_netdev_client);
@ -417,6 +423,6 @@ module_init(ntb_netdev_init_module);
static void __exit ntb_netdev_exit_module(void) static void __exit ntb_netdev_exit_module(void)
{ {
ntb_transport_unregister_client(&ntb_netdev_client); ntb_transport_unregister_client(&ntb_netdev_client);
ntb_unregister_client_dev(KBUILD_MODNAME); ntb_transport_unregister_client_dev(KBUILD_MODNAME);
} }
module_exit(ntb_netdev_exit_module); module_exit(ntb_netdev_exit_module);

35
drivers/ntb/Kconfig
View file

@ -1,13 +1,26 @@
config NTB menuconfig NTB
tristate "Intel Non-Transparent Bridge support" tristate "Non-Transparent Bridge support"
depends on PCI depends on PCI
depends on X86 help
help The PCI-E Non-transparent bridge hardware is a point-to-point PCI-E bus
The PCI-E Non-transparent bridge hardware is a point-to-point PCI-E bus connecting 2 systems. When configured, writes to the device's PCI
connecting 2 systems. When configured, writes to the device's PCI mapped memory will be mirrored to a buffer on the remote system. The
mapped memory will be mirrored to a buffer on the remote system. The ntb Linux driver uses this point-to-point communication as a method to
ntb Linux driver uses this point-to-point communication as a method to transfer data from one system to the other.
transfer data from one system to the other.
If unsure, say N. If unsure, say N.
if NTB
source "drivers/ntb/hw/Kconfig"
config NTB_TRANSPORT
tristate "NTB Transport Client"
help
This is a transport driver that enables connected systems to exchange
messages over the ntb hardware. The transport exposes a queue pair api
to client drivers.
If unsure, say N.
endif # NTB

6
drivers/ntb/Makefile
View file

@ -1,4 +1,2 @@
obj-$(CONFIG_NTB) += ntb.o obj-$(CONFIG_NTB) += ntb.o hw/
obj-$(CONFIG_NTB) += ntb_hw_intel.o obj-$(CONFIG_NTB_TRANSPORT) += ntb_transport.o
ntb_hw_intel-objs := hw/intel/ntb_hw_intel.o ntb_transport.o

1
drivers/ntb/hw/Kconfig Normal file
View file

@ -0,0 +1 @@
source "drivers/ntb/hw/intel/Kconfig"

1
drivers/ntb/hw/Makefile Normal file
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@ -0,0 +1 @@
obj-$(CONFIG_NTB_INTEL) += intel/

7
drivers/ntb/hw/intel/Kconfig Normal file
View file

@ -0,0 +1,7 @@
config NTB_INTEL
tristate "Intel Non-Transparent Bridge support"
depends on X86_64
help
This driver supports Intel NTB on capable Xeon and Atom hardware.
If unsure, say N.

1
drivers/ntb/hw/intel/Makefile Normal file
View file

@ -0,0 +1 @@
obj-$(CONFIG_NTB_INTEL) += ntb_hw_intel.o

3817
drivers/ntb/hw/intel/ntb_hw_intel.c
View file

File diff suppressed because it is too large Load diff

601
drivers/ntb/hw/intel/ntb_hw_intel.h
View file

@ -5,6 +5,7 @@
* GPL LICENSE SUMMARY * GPL LICENSE SUMMARY
* *
* Copyright(c) 2012 Intel Corporation. All rights reserved. * Copyright(c) 2012 Intel Corporation. All rights reserved.
* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as * it under the terms of version 2 of the GNU General Public License as
@ -13,6 +14,7 @@
* BSD LICENSE * BSD LICENSE
* *
* Copyright(c) 2012 Intel Corporation. All rights reserved. * Copyright(c) 2012 Intel Corporation. All rights reserved.
* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -45,341 +47,296 @@
* Contact Information: * Contact Information:
* Jon Mason <jon.mason@intel.com> * Jon Mason <jon.mason@intel.com>
*/ */
#include <linux/ntb_transport.h>
#define NTB_LINK_STATUS_ACTIVE 0x2000 #ifndef NTB_HW_INTEL_H
#define NTB_LINK_SPEED_MASK 0x000f #define NTB_HW_INTEL_H
#define NTB_LINK_WIDTH_MASK 0x03f0
#define SNB_MSIX_CNT 4 #include <linux/ntb.h>
#define SNB_MAX_B2B_SPADS 16 #include <linux/pci.h>
#define SNB_MAX_COMPAT_SPADS 16
/* Reserve the uppermost bit for link interrupt */
#define SNB_MAX_DB_BITS 15
#define SNB_LINK_DB 15
#define SNB_DB_BITS_PER_VEC 5
#define HSX_SPLITBAR_MAX_MW 3
#define SNB_MAX_MW 2
#define SNB_ERRATA_MAX_MW 1
#define SNB_DB_HW_LINK 0x8000 #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
#define SNB_UNCERRSTS_OFFSET 0x014C /* SNB hardware (and JSF, IVT, HSX) */
#define SNB_CORERRSTS_OFFSET 0x0158
#define SNB_LINK_STATUS_OFFSET 0x01A2
#define SNB_PCICMD_OFFSET 0x0504
#define SNB_DEVCTRL_OFFSET 0x0598
#define SNB_DEVSTS_OFFSET 0x059A
#define SNB_SLINK_STATUS_OFFSET 0x05A2
#define SNB_PBAR2LMT_OFFSET 0x0000 #define SNB_PBAR23LMT_OFFSET 0x0000
#define SNB_PBAR4LMT_OFFSET 0x0008 #define SNB_PBAR45LMT_OFFSET 0x0008
#define SNB_PBAR5LMT_OFFSET 0x000C #define SNB_PBAR4LMT_OFFSET 0x0008
#define SNB_PBAR2XLAT_OFFSET 0x0010 #define SNB_PBAR5LMT_OFFSET 0x000c
#define SNB_PBAR4XLAT_OFFSET 0x0018 #define SNB_PBAR23XLAT_OFFSET 0x0010
#define SNB_PBAR5XLAT_OFFSET 0x001C #define SNB_PBAR45XLAT_OFFSET 0x0018
#define SNB_SBAR2LMT_OFFSET 0x0020 #define SNB_PBAR4XLAT_OFFSET 0x0018
#define SNB_SBAR4LMT_OFFSET 0x0028 #define SNB_PBAR5XLAT_OFFSET 0x001c
#define SNB_SBAR5LMT_OFFSET 0x002C #define SNB_SBAR23LMT_OFFSET 0x0020
#define SNB_SBAR2XLAT_OFFSET 0x0030 #define SNB_SBAR45LMT_OFFSET 0x0028
#define SNB_SBAR4XLAT_OFFSET 0x0038 #define SNB_SBAR4LMT_OFFSET 0x0028
#define SNB_SBAR5XLAT_OFFSET 0x003C #define SNB_SBAR5LMT_OFFSET 0x002c
#define SNB_SBAR0BASE_OFFSET 0x0040 #define SNB_SBAR23XLAT_OFFSET 0x0030
#define SNB_SBAR2BASE_OFFSET 0x0048 #define SNB_SBAR45XLAT_OFFSET 0x0038
#define SNB_SBAR4BASE_OFFSET 0x0050 #define SNB_SBAR4XLAT_OFFSET 0x0038
#define SNB_SBAR5BASE_OFFSET 0x0054 #define SNB_SBAR5XLAT_OFFSET 0x003c
#define SNB_NTBCNTL_OFFSET 0x0058 #define SNB_SBAR0BASE_OFFSET 0x0040
#define SNB_SBDF_OFFSET 0x005C #define SNB_SBAR23BASE_OFFSET 0x0048
#define SNB_PDOORBELL_OFFSET 0x0060 #define SNB_SBAR45BASE_OFFSET 0x0050
#define SNB_PDBMSK_OFFSET 0x0062 #define SNB_SBAR4BASE_OFFSET 0x0050
#define SNB_SDOORBELL_OFFSET 0x0064 #define SNB_SBAR5BASE_OFFSET 0x0054
#define SNB_SDBMSK_OFFSET 0x0066 #define SNB_SBDF_OFFSET 0x005c
#define SNB_USMEMMISS_OFFSET 0x0070 #define SNB_NTBCNTL_OFFSET 0x0058
#define SNB_SPAD_OFFSET 0x0080 #define SNB_PDOORBELL_OFFSET 0x0060
#define SNB_SPADSEMA4_OFFSET 0x00c0 #define SNB_PDBMSK_OFFSET 0x0062
#define SNB_WCCNTRL_OFFSET 0x00e0 #define SNB_SDOORBELL_OFFSET 0x0064
#define SNB_B2B_SPAD_OFFSET 0x0100 #define SNB_SDBMSK_OFFSET 0x0066
#define SNB_B2B_DOORBELL_OFFSET 0x0140 #define SNB_USMEMMISS_OFFSET 0x0070
#define SNB_B2B_XLAT_OFFSETL 0x0144 #define SNB_SPAD_OFFSET 0x0080
#define SNB_B2B_XLAT_OFFSETU 0x0148 #define SNB_PBAR23SZ_OFFSET 0x00d0
#define SNB_PBAR45SZ_OFFSET 0x00d1
#define SNB_PBAR4SZ_OFFSET 0x00d1
#define SNB_SBAR23SZ_OFFSET 0x00d2
#define SNB_SBAR45SZ_OFFSET 0x00d3
#define SNB_SBAR4SZ_OFFSET 0x00d3
#define SNB_PPD_OFFSET 0x00d4
#define SNB_PBAR5SZ_OFFSET 0x00d5
#define SNB_SBAR5SZ_OFFSET 0x00d6
#define SNB_WCCNTRL_OFFSET 0x00e0
#define SNB_UNCERRSTS_OFFSET 0x014c
#define SNB_CORERRSTS_OFFSET 0x0158
#define SNB_LINK_STATUS_OFFSET 0x01a2
#define SNB_SPCICMD_OFFSET 0x0504
#define SNB_DEVCTRL_OFFSET 0x0598
#define SNB_DEVSTS_OFFSET 0x059a
#define SNB_SLINK_STATUS_OFFSET 0x05a2
#define SNB_B2B_SPAD_OFFSET 0x0100
#define SNB_B2B_DOORBELL_OFFSET 0x0140
#define SNB_B2B_XLAT_OFFSETL 0x0144
#define SNB_B2B_XLAT_OFFSETU 0x0148
#define SNB_PPD_CONN_MASK 0x03
#define SNB_PPD_CONN_TRANSPARENT 0x00
#define SNB_PPD_CONN_B2B 0x01
#define SNB_PPD_CONN_RP 0x02
#define SNB_PPD_DEV_MASK 0x10
#define SNB_PPD_DEV_USD 0x00
#define SNB_PPD_DEV_DSD 0x10
#define SNB_PPD_SPLIT_BAR_MASK 0x40
/* #define SNB_PPD_TOPO_MASK (SNB_PPD_CONN_MASK | SNB_PPD_DEV_MASK)
* The addresses are setup so the 32bit BARs can function. Thus #define SNB_PPD_TOPO_PRI_USD (SNB_PPD_CONN_RP | SNB_PPD_DEV_USD)
* the addresses are all in 32bit space #define SNB_PPD_TOPO_PRI_DSD (SNB_PPD_CONN_RP | SNB_PPD_DEV_DSD)
*/ #define SNB_PPD_TOPO_SEC_USD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_USD)
#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL #define SNB_PPD_TOPO_SEC_DSD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_DSD)
#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL #define SNB_PPD_TOPO_B2B_USD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_USD)
#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL #define SNB_PPD_TOPO_B2B_DSD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_DSD)
#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL
#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL
#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL
#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL
#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL
#define BWD_MSIX_CNT 34 #define SNB_MW_COUNT 2
#define BWD_MAX_SPADS 16 #define HSX_SPLIT_BAR_MW_COUNT 3
#define BWD_MAX_DB_BITS 34 #define SNB_DB_COUNT 15
#define BWD_DB_BITS_PER_VEC 1 #define SNB_DB_LINK 15
#define BWD_MAX_MW 2 #define SNB_DB_LINK_BIT BIT_ULL(SNB_DB_LINK)
#define SNB_DB_MSIX_VECTOR_COUNT 4
#define SNB_DB_MSIX_VECTOR_SHIFT 5
#define SNB_DB_TOTAL_SHIFT 16
#define SNB_SPAD_COUNT 16
#define BWD_PCICMD_OFFSET 0xb004 /* BWD hardware */
#define BWD_MBAR23_OFFSET 0xb018
#define BWD_MBAR45_OFFSET 0xb020
#define BWD_DEVCTRL_OFFSET 0xb048
#define BWD_LINK_STATUS_OFFSET 0xb052
#define BWD_ERRCORSTS_OFFSET 0xb110
#define BWD_SBAR2XLAT_OFFSET 0x0008 #define BWD_SBAR2XLAT_OFFSET 0x0008
#define BWD_SBAR4XLAT_OFFSET 0x0010 #define BWD_PDOORBELL_OFFSET 0x0020
#define BWD_PDOORBELL_OFFSET 0x0020 #define BWD_PDBMSK_OFFSET 0x0028
#define BWD_PDBMSK_OFFSET 0x0028 #define BWD_NTBCNTL_OFFSET 0x0060
#define BWD_NTBCNTL_OFFSET 0x0060 #define BWD_SPAD_OFFSET 0x0080
#define BWD_EBDF_OFFSET 0x0064 #define BWD_PPD_OFFSET 0x00d4
#define BWD_SPAD_OFFSET 0x0080 #define BWD_PBAR2XLAT_OFFSET 0x8008
#define BWD_SPADSEMA_OFFSET 0x00c0 #define BWD_B2B_DOORBELL_OFFSET 0x8020
#define BWD_STKYSPAD_OFFSET 0x00c4 #define BWD_B2B_SPAD_OFFSET 0x8080
#define BWD_PBAR2XLAT_OFFSET 0x8008 #define BWD_SPCICMD_OFFSET 0xb004
#define BWD_PBAR4XLAT_OFFSET 0x8010 #define BWD_LINK_STATUS_OFFSET 0xb052
#define BWD_B2B_DOORBELL_OFFSET 0x8020 #define BWD_ERRCORSTS_OFFSET 0xb110
#define BWD_B2B_SPAD_OFFSET 0x8080 #define BWD_IP_BASE 0xc000
#define BWD_B2B_SPADSEMA_OFFSET 0x80c0 #define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024)
#define BWD_B2B_STKYSPAD_OFFSET 0x80c4 #define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
#define BWD_MODPHY_PCSREG4 0x1c004
#define BWD_MODPHY_PCSREG6 0x1c006
#define BWD_IP_BASE 0xC000
#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024)
#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040) #define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040)
#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324) #define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324)
#define BWD_MODPHY_PCSREG4 0x1c004
#define BWD_MODPHY_PCSREG6 0x1c006
#define BWD_DESKEWSTS_DBERR (1 << 15) #define BWD_PPD_INIT_LINK 0x0008
#define BWD_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) #define BWD_PPD_CONN_MASK 0x0300
#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2) #define BWD_PPD_CONN_TRANSPARENT 0x0000
#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF #define BWD_PPD_CONN_B2B 0x0100
#define BWD_PPD_CONN_RP 0x0200
#define BWD_PPD_DEV_MASK 0x1000
#define BWD_PPD_DEV_USD 0x0000
#define BWD_PPD_DEV_DSD 0x1000
#define BWD_PPD_TOPO_MASK (BWD_PPD_CONN_MASK | BWD_PPD_DEV_MASK)
#define BWD_PPD_TOPO_PRI_USD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_USD)
#define BWD_PPD_TOPO_PRI_DSD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_DSD)
#define BWD_PPD_TOPO_SEC_USD (BWD_PPD_CONN_RP | BWD_PPD_DEV_USD)
#define BWD_PPD_TOPO_SEC_DSD (BWD_PPD_CONN_RP | BWD_PPD_DEV_DSD)
#define BWD_PPD_TOPO_B2B_USD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_USD)
#define BWD_PPD_TOPO_B2B_DSD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_DSD)
#define NTB_CNTL_CFG_LOCK (1 << 0) #define BWD_MW_COUNT 2
#define NTB_CNTL_LINK_DISABLE (1 << 1) #define BWD_DB_COUNT 34
#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) #define BWD_DB_VALID_MASK (BIT_ULL(BWD_DB_COUNT) - 1)
#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) #define BWD_DB_MSIX_VECTOR_COUNT 34
#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6) #define BWD_DB_MSIX_VECTOR_SHIFT 1
#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8) #define BWD_DB_TOTAL_SHIFT 34
#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12) #define BWD_SPAD_COUNT 16
#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
#define BWD_CNTL_LINK_DOWN (1 << 16)
#define NTB_PPD_OFFSET 0x00D4 #define BWD_NTB_CTL_DOWN_BIT BIT(16)
#define SNB_PPD_CONN_TYPE 0x0003 #define BWD_NTB_CTL_ACTIVE(x) !(x & BWD_NTB_CTL_DOWN_BIT)
#define SNB_PPD_DEV_TYPE 0x0010
#define SNB_PPD_SPLIT_BAR (1 << 6) #define BWD_DESKEWSTS_DBERR BIT(15)
#define BWD_PPD_INIT_LINK 0x0008 #define BWD_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
#define BWD_PPD_CONN_TYPE 0x0300 #define BWD_LTSSMSTATEJMP_FORCEDETECT BIT(2)
#define BWD_PPD_DEV_TYPE 0x1000 #define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 #define BWD_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 #define BWD_LINK_RECOVERY_TIME msecs_to_jiffies(500)
#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E /* Ntb control and link status */
#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D #define NTB_CTL_CFG_LOCK BIT(0)
#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E #define NTB_CTL_DISABLE BIT(1)
#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F #define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D #define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E #define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F #define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E #define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
#define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
#define NTB_LNK_STA_ACTIVE_BIT 0x2000
#define NTB_LNK_STA_SPEED_MASK 0x000f
#define NTB_LNK_STA_WIDTH_MASK 0x03f0
#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
/* Use the following addresses for translation between b2b ntb devices in case
* the hardware default values are not reliable. */
#define SNB_B2B_BAR0_USD_ADDR 0x1000000000000000ull
#define SNB_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
#define SNB_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
#define SNB_B2B_BAR4_USD_ADDR32 0x20000000u
#define SNB_B2B_BAR5_USD_ADDR32 0x40000000u
#define SNB_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
#define SNB_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
#define SNB_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
#define SNB_B2B_BAR4_DSD_ADDR32 0xa0000000u
#define SNB_B2B_BAR5_DSD_ADDR32 0xc0000000u
/* The peer ntb secondary config space is 32KB fixed size */
#define SNB_B2B_MIN_SIZE 0x8000
/* flags to indicate hardware errata */
#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
/* flags to indicate unsafe api */
#define NTB_UNSAFE_DB BIT_ULL(0)
#define NTB_UNSAFE_SPAD BIT_ULL(1)
struct intel_ntb_dev;
struct intel_ntb_reg {
int (*poll_link)(struct intel_ntb_dev *ndev);
int (*link_is_up)(struct intel_ntb_dev *ndev);
u64 (*db_ioread)(void __iomem *mmio);
void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
unsigned long ntb_ctl;
resource_size_t db_size;
int mw_bar[];
};
struct intel_ntb_alt_reg {
unsigned long db_bell;
unsigned long db_mask;
unsigned long spad;
};
struct intel_ntb_xlat_reg {
unsigned long bar0_base;
unsigned long bar2_xlat;
unsigned long bar2_limit;
};
struct intel_b2b_addr {
phys_addr_t bar0_addr;
phys_addr_t bar2_addr64;
phys_addr_t bar4_addr64;
phys_addr_t bar4_addr32;
phys_addr_t bar5_addr32;
};
struct intel_ntb_vec {
struct intel_ntb_dev *ndev;
int num;
};
struct intel_ntb_dev {
struct ntb_dev ntb;
/* offset of peer bar0 in b2b bar */
unsigned long b2b_off;
/* mw idx used to access peer bar0 */
unsigned int b2b_idx;
/* BAR45 is split into BAR4 and BAR5 */
bool bar4_split;
u32 ntb_ctl;
u32 lnk_sta;
unsigned char mw_count;
unsigned char spad_count;
unsigned char db_count;
unsigned char db_vec_count;
unsigned char db_vec_shift;
u64 db_valid_mask;
u64 db_link_mask;
u64 db_mask;
/* synchronize rmw access of db_mask and hw reg */
spinlock_t db_mask_lock;
struct msix_entry *msix;
struct intel_ntb_vec *vec;
const struct intel_ntb_reg *reg;
const struct intel_ntb_alt_reg *self_reg;
const struct intel_ntb_alt_reg *peer_reg;
const struct intel_ntb_xlat_reg *xlat_reg;
void __iomem *self_mmio;
void __iomem *peer_mmio;
phys_addr_t peer_addr;
unsigned long last_ts;
struct delayed_work hb_timer;
unsigned long hwerr_flags;
unsigned long unsafe_flags;
unsigned long unsafe_flags_ignore;
struct dentry *debugfs_dir;
struct dentry *debugfs_info;
};
#define ndev_pdev(ndev) ((ndev)->ntb.pdev)
#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
#define ntb_ndev(ntb) container_of(ntb, struct intel_ntb_dev, ntb)
#define hb_ndev(work) container_of(work, struct intel_ntb_dev, hb_timer.work)
#ifndef readq
static inline u64 readq(void __iomem *addr)
{
return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
}
#endif #endif
#ifndef writeq
static inline void writeq(u64 val, void __iomem *addr)
{
writel(val & 0xffffffff, addr);
writel(val >> 32, addr + 4);
}
#endif
#define NTB_BAR_MMIO 0
#define NTB_BAR_23 2
#define NTB_BAR_4 4
#define NTB_BAR_5 5
#define NTB_BAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\
(1 << NTB_BAR_4))
#define NTB_SPLITBAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\
(1 << NTB_BAR_4) | (1 << NTB_BAR_5))
#define NTB_HB_TIMEOUT msecs_to_jiffies(1000)
enum ntb_hw_event {
NTB_EVENT_SW_EVENT0 = 0,
NTB_EVENT_SW_EVENT1,
NTB_EVENT_SW_EVENT2,
NTB_EVENT_HW_ERROR,
NTB_EVENT_HW_LINK_UP,
NTB_EVENT_HW_LINK_DOWN,
};
struct ntb_mw {
dma_addr_t phys_addr;
void __iomem *vbase;
resource_size_t bar_sz;
};
struct ntb_db_cb {
int (*callback)(void *data, int db_num);
unsigned int db_num;
void *data;
struct ntb_device *ndev;
struct tasklet_struct irq_work;
};
#define WA_SNB_ERR 0x00000001
struct ntb_device {
struct pci_dev *pdev;
struct msix_entry *msix_entries;
void __iomem *reg_base;
struct ntb_mw *mw;
struct {
unsigned char max_mw;
unsigned char max_spads;
unsigned char max_db_bits;
unsigned char msix_cnt;
} limits;
struct {
void __iomem *ldb;
void __iomem *ldb_mask;
void __iomem *rdb;
void __iomem *bar2_xlat;
void __iomem *bar4_xlat;
void __iomem *bar5_xlat;
void __iomem *spad_write;
void __iomem *spad_read;
void __iomem *lnk_cntl;
void __iomem *lnk_stat;
void __iomem *spci_cmd;
} reg_ofs;
struct ntb_transport *ntb_transport;
void (*event_cb)(void *handle, enum ntb_hw_event event);
struct ntb_db_cb *db_cb;
unsigned char hw_type;
unsigned char conn_type;
unsigned char dev_type;
unsigned char num_msix;
unsigned char bits_per_vector;
unsigned char max_cbs;
unsigned char link_width;
unsigned char link_speed;
unsigned char link_status;
unsigned char split_bar;
struct delayed_work hb_timer;
unsigned long last_ts;
struct delayed_work lr_timer;
struct dentry *debugfs_dir;
struct dentry *debugfs_info;
unsigned int wa_flags;
};
/**
* ntb_max_cbs() - return the max callbacks
* @ndev: pointer to ntb_device instance
*
* Given the ntb pointer, return the maximum number of callbacks
*
* RETURNS: the maximum number of callbacks
*/
static inline unsigned char ntb_max_cbs(struct ntb_device *ndev)
{
return ndev->max_cbs;
}
/**
* ntb_max_mw() - return the max number of memory windows
* @ndev: pointer to ntb_device instance
*
* Given the ntb pointer, return the maximum number of memory windows
*
* RETURNS: the maximum number of memory windows
*/
static inline unsigned char ntb_max_mw(struct ntb_device *ndev)
{
return ndev->limits.max_mw;
}
/**
* ntb_hw_link_status() - return the hardware link status
* @ndev: pointer to ntb_device instance
*
* Returns true if the hardware is connected to the remote system
*
* RETURNS: true or false based on the hardware link state
*/
static inline bool ntb_hw_link_status(struct ntb_device *ndev)
{
return ndev->link_status == NTB_LINK_UP;
}
/**
* ntb_query_pdev() - return the pci_dev pointer
* @ndev: pointer to ntb_device instance
*
* Given the ntb pointer, return the pci_dev pointer for the NTB hardware device
*
* RETURNS: a pointer to the ntb pci_dev
*/
static inline struct pci_dev *ntb_query_pdev(struct ntb_device *ndev)
{
return ndev->pdev;
}
/**
* ntb_query_debugfs() - return the debugfs pointer
* @ndev: pointer to ntb_device instance
*
* Given the ntb pointer, return the debugfs directory pointer for the NTB
* hardware device
*
* RETURNS: a pointer to the debugfs directory
*/
static inline struct dentry *ntb_query_debugfs(struct ntb_device *ndev)
{
return ndev->debugfs_dir;
}
struct ntb_device *ntb_register_transport(struct pci_dev *pdev,
void *transport);
void ntb_unregister_transport(struct ntb_device *ndev);
void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr);
int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
void *data, int (*db_cb_func)(void *data,
int db_num));
void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx);
int ntb_register_event_callback(struct ntb_device *ndev,
void (*event_cb_func)(void *handle,
enum ntb_hw_event event));
void ntb_unregister_event_callback(struct ntb_device *ndev);
int ntb_get_max_spads(struct ntb_device *ndev);
int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val);
int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);
int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val);
int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);
resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw);
void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw);
u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw);
void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int idx);
void *ntb_find_transport(struct pci_dev *pdev);
int ntb_transport_init(struct pci_dev *pdev);
void ntb_transport_free(void *transport);

940
drivers/ntb/ntb_transport.c
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File diff suppressed because it is too large Load diff

25
include/linux/ntb_transport.h
View file

@ -5,6 +5,7 @@
* GPL LICENSE SUMMARY * GPL LICENSE SUMMARY
* *
* Copyright(c) 2012 Intel Corporation. All rights reserved. * Copyright(c) 2012 Intel Corporation. All rights reserved.
* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as * it under the terms of version 2 of the GNU General Public License as
@ -13,6 +14,7 @@
* BSD LICENSE * BSD LICENSE
* *
* Copyright(c) 2012 Intel Corporation. All rights reserved. * Copyright(c) 2012 Intel Corporation. All rights reserved.
* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -40,7 +42,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
* Intel PCIe NTB Linux driver * PCIe NTB Transport Linux driver
* *
* Contact Information: * Contact Information:
* Jon Mason <jon.mason@intel.com> * Jon Mason <jon.mason@intel.com>
@ -48,21 +50,16 @@
struct ntb_transport_qp; struct ntb_transport_qp;
struct ntb_client { struct ntb_transport_client {
struct device_driver driver; struct device_driver driver;
int (*probe)(struct pci_dev *pdev); int (*probe)(struct device *client_dev);
void (*remove)(struct pci_dev *pdev); void (*remove)(struct device *client_dev);
}; };
enum { int ntb_transport_register_client(struct ntb_transport_client *drvr);
NTB_LINK_DOWN = 0, void ntb_transport_unregister_client(struct ntb_transport_client *drvr);
NTB_LINK_UP, int ntb_transport_register_client_dev(char *device_name);
}; void ntb_transport_unregister_client_dev(char *device_name);
int ntb_transport_register_client(struct ntb_client *drvr);
void ntb_transport_unregister_client(struct ntb_client *drvr);
int ntb_register_client_dev(char *device_name);
void ntb_unregister_client_dev(char *device_name);
struct ntb_queue_handlers { struct ntb_queue_handlers {
void (*rx_handler)(struct ntb_transport_qp *qp, void *qp_data, void (*rx_handler)(struct ntb_transport_qp *qp, void *qp_data,
@ -75,7 +72,7 @@ struct ntb_queue_handlers {
unsigned char ntb_transport_qp_num(struct ntb_transport_qp *qp); unsigned char ntb_transport_qp_num(struct ntb_transport_qp *qp);
unsigned int ntb_transport_max_size(struct ntb_transport_qp *qp); unsigned int ntb_transport_max_size(struct ntb_transport_qp *qp);
struct ntb_transport_qp * struct ntb_transport_qp *
ntb_transport_create_queue(void *data, struct pci_dev *pdev, ntb_transport_create_queue(void *data, struct device *client_dev,
const struct ntb_queue_handlers *handlers); const struct ntb_queue_handlers *handlers);
void ntb_transport_free_queue(struct ntb_transport_qp *qp); void ntb_transport_free_queue(struct ntb_transport_qp *qp);
int ntb_transport_rx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data, int ntb_transport_rx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data,