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Revert "mmc: sdhci-msm: Disable SD Card's Clock Scaling"

Browse source 
This reverts commit e64d0071e1.
The reason for sqaushing reverts is, they are many changes
which are difficult to manage. And have reverted as these changes
are added only on top of SDCard porting.
To add eMMC support, need to revert these and then add these in
eMMC and SDCard porting changes together.

Revert "mmc: sdhci-msm: Fix issue with 1.8v switch sequence"
This reverts commit abe24b0a62.

Revert "mmc: sdhci-msm: No need to free-up dll-hsr table"
This reverts commit e9af258976.

Revert "mmc: sdhci-msm: Support for getting DLL HSR values from dt file"
This reverts commit 0c2baf447e.

Revert "mmc: core: Fix error when SD card is removed"
This reverts commit 6bdf4fce97.

Revert "mmc: Fix compile warnings"
This reverts commit 3850cd391d.

Revert "mmc: core: Use freq table with devfreq"
This reverts commit 6a56af622b.

All above commits were added before porting which are now part of
ported gerrits.

Change-Id: I8239708190195d1a7256f160320ae6487973766d
Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
This commit is contained in:
Ram Prakash Gupta 2019-05-08 08:30:29 +05:30
parent 6942b104a0
commit e1f4735c37
5 changed files with 61 additions and 128 deletions

58
drivers/mmc/core/core.c
View file

@ -543,7 +543,6 @@ static int mmc_devfreq_create_freq_table(struct mmc_host *host)
int mmc_init_clk_scaling(struct mmc_host *host)
{
int err;
struct devfreq *devfreq;
if (!host || !host->card) {
pr_err("%s: unexpected host/card parameters\n",
@ -594,34 +593,22 @@ int mmc_init_clk_scaling(struct mmc_host *host)
return err;
}
dev_pm_opp_add(mmc_classdev(host),
host->clk_scaling.devfreq_profile.freq_table[0], 0);
dev_pm_opp_add(mmc_classdev(host),
host->clk_scaling.devfreq_profile.freq_table[1], 0);
pr_debug("%s: adding devfreq with: upthreshold=%u downthreshold=%u polling=%u\n",
mmc_hostname(host),
host->clk_scaling.ondemand_gov_data.upthreshold,
host->clk_scaling.ondemand_gov_data.downdifferential,
host->clk_scaling.devfreq_profile.polling_ms);
devfreq = devfreq_add_device(
host->clk_scaling.devfreq = devfreq_add_device(
mmc_classdev(host),
&host->clk_scaling.devfreq_profile,
"simple_ondemand",
&host->clk_scaling.ondemand_gov_data);
if (IS_ERR(devfreq)) {
if (!host->clk_scaling.devfreq) {
pr_err("%s: unable to register with devfreq\n",
mmc_hostname(host));
dev_pm_opp_remove(mmc_classdev(host),
host->clk_scaling.devfreq_profile.freq_table[0]);
dev_pm_opp_remove(mmc_classdev(host),
host->clk_scaling.devfreq_profile.freq_table[1]);
return PTR_ERR(devfreq);
return -EPERM;
}
host->clk_scaling.devfreq = devfreq;
pr_debug("%s: clk scaling is enabled for device %s (%pK) with devfreq %pK (clock = %uHz)\n",
mmc_hostname(host),
dev_name(mmc_classdev(host)),
@ -779,11 +766,6 @@ int mmc_exit_clk_scaling(struct mmc_host *host)
return err;
}
dev_pm_opp_remove(mmc_classdev(host),
host->clk_scaling.devfreq_profile.freq_table[0]);
dev_pm_opp_remove(mmc_classdev(host),
host->clk_scaling.devfreq_profile.freq_table[1]);
kfree(host->clk_scaling.devfreq_profile.freq_table);
host->clk_scaling.devfreq = NULL;
@ -1806,13 +1788,12 @@ int mmc_try_claim_host(struct mmc_host *host, unsigned int delay_ms)
unsigned long flags;
int retry_cnt = delay_ms/10;
bool pm = false;
struct task_struct *task = current;
do {
spin_lock_irqsave(&host->lock, flags);
if (!host->claimed || mmc_ctx_matches(host, NULL, task)) {
if (!host->claimed || host->claimer->task == current) {
host->claimed = 1;
mmc_ctx_set_claimer(host, NULL, task);
host->claimer->task = current;
host->claim_cnt += 1;
claimed_host = 1;
if (host->claim_cnt == 1)
@ -2574,23 +2555,18 @@ int mmc_host_set_uhs_voltage(struct mmc_host *host)
* During a signal voltage level switch, the clock must be gated
* for 5 ms according to the SD spec
*/
host->card_clock_off = true;
clock = host->ios.clock;
host->ios.clock = 0;
mmc_set_ios(host);
if (mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180)) {
host->ios.clock = clock;
mmc_set_ios(host);
host->card_clock_off = false;
if (mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180))
return -EAGAIN;
}
/* Keep clock gated for at least 10 ms, though spec only says 5 ms */
mmc_delay(10);
host->ios.clock = clock;
mmc_set_ios(host);
host->card_clock_off = false;
return 0;
}
@ -2598,6 +2574,7 @@ int mmc_set_uhs_voltage(struct mmc_host *host, u32 ocr)
{
struct mmc_command cmd = {};
int err = 0;
u32 clock;
/*
* If we cannot switch voltages, return failure so the caller
@ -2635,16 +2612,33 @@ int mmc_set_uhs_voltage(struct mmc_host *host, u32 ocr)
err = -EAGAIN;
goto power_cycle;
}
/*
* During a signal voltage level switch, the clock must be gated
* for 5 ms according to the SD spec
*/
host->card_clock_off = true;
clock = host->ios.clock;
host->ios.clock = 0;
mmc_set_ios(host);
if (mmc_host_set_uhs_voltage(host)) {
if (mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180)) {
/*
* Voltages may not have been switched, but we've already
* sent CMD11, so a power cycle is required anyway
*/
err = -EAGAIN;
host->ios.clock = clock;
mmc_set_ios(host);
host->card_clock_off = false;
goto power_cycle;
}
/* Keep clock gated for at least 10 ms, though spec only says 5 ms */
mmc_delay(10);
host->ios.clock = clock;
mmc_set_ios(host);
host->card_clock_off = false;
/* Wait for at least 1 ms according to spec */
mmc_delay(1);

2
drivers/mmc/core/sd.c
View file

@ -1197,6 +1197,8 @@ static void mmc_sd_detect(struct mmc_host *host)
return;
}
mmc_get_card(host->card, NULL);
/*
* Just check if our card has been removed.
*/

111
drivers/mmc/host/sdhci-msm.c
View file

@ -354,9 +354,6 @@ enum dll_init_context {
DLL_INIT_FROM_CX_COLLAPSE_EXIT,
};
static unsigned int sdhci_msm_get_sup_clk_rate(struct sdhci_host *host,
u32 req_clk);
/* MSM platform specific tuning */
static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host,
u8 poll)
@ -758,7 +755,6 @@ static int msm_init_cm_dll(struct sdhci_host *host,
if (msm_host->use_updated_dll_reset) {
u32 mclk_freq = 0;
u32 actual_clk = sdhci_msm_get_sup_clk_rate(host, host->clock);
/*
* Only configure the mclk_freq in normal DLL init
@ -768,7 +764,7 @@ static int msm_init_cm_dll(struct sdhci_host *host,
* proper value prior to getting here.
*/
if (init_context == DLL_INIT_NORMAL) {
switch (actual_clk) {
switch (host->clock) {
case 208000000:
case 202000000:
case 201500000:
@ -779,9 +775,10 @@ static int msm_init_cm_dll(struct sdhci_host *host,
mclk_freq = 40;
break;
default:
mclk_freq = (u32)((actual_clk / TCXO_FREQ) * 4);
pr_info_once("%s: %s: Non standard clk freq =%u\n",
mmc_hostname(mmc), __func__, actual_clk);
pr_err("%s: %s: Error. Unsupported clk freq\n",
mmc_hostname(mmc), __func__);
rc = -EINVAL;
goto out;
}
if ((readl_relaxed(host->ioaddr +
@ -818,33 +815,12 @@ static int msm_init_cm_dll(struct sdhci_host *host,
/* Configure Tassadar DLL (Only applicable for 7FF projects) */
if (msm_host->use_7nm_dll) {
if (msm_host->dll_hsr) {
writel_relaxed(msm_host->dll_hsr->dll_usr_ctl,
host->ioaddr +
msm_host_offset->CORE_DLL_USR_CTL);
writel_relaxed(msm_host->dll_hsr->dll_config_3,
host->ioaddr +
msm_host_offset->CORE_DLL_CONFIG_3);
} else {
writel_relaxed(DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL,
host->ioaddr +
msm_host_offset->CORE_DLL_USR_CTL);
writel_relaxed(DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL, host->ioaddr +
msm_host_offset->CORE_DLL_USR_CTL);
writel_relaxed(DLL_CONFIG_3_POR_VAL, host->ioaddr +
msm_host_offset->CORE_DLL_CONFIG_3);
}
}
/*
* Update the lower two bytes of DLL_CONFIG only with HSR values.
* Since these are the static settings.
*/
if (msm_host->dll_hsr) {
writel_relaxed((readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_CONFIG) |
(msm_host->dll_hsr->dll_config & 0xffff)),
host->ioaddr + msm_host_offset->CORE_DLL_CONFIG);
writel_relaxed(DLL_CONFIG_3_POR_VAL, host->ioaddr +
msm_host_offset->CORE_DLL_CONFIG_3);
}
/* Set DLL_EN bit to 1. */
@ -1027,8 +1003,8 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
* Reprogramming the value in case it might have been modified by
* bootloaders.
*/
if (msm_host->dll_hsr && msm_host->dll_hsr->ddr_config) {
writel_relaxed(msm_host->dll_hsr->ddr_config, host->ioaddr +
if (msm_host->pdata->rclk_wa) {
writel_relaxed(msm_host->pdata->ddr_config, host->ioaddr +
msm_host_offset->CORE_DDR_CONFIG);
} else if (msm_host->rclk_delay_fix) {
writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
@ -1972,32 +1948,6 @@ static void sdhci_msm_pm_qos_parse(struct device *dev,
}
}
static int sdhci_msm_dt_parse_hsr_info(struct device *dev,
struct sdhci_msm_host *msm_host)
{
u32 *dll_hsr_table = NULL;
int dll_hsr_table_len, dll_hsr_reg_count;
int ret = 0;
if (sdhci_msm_dt_get_array(dev, "qcom,dll-hsr-list",
&dll_hsr_table, &dll_hsr_table_len, 0))
goto skip_hsr;
dll_hsr_reg_count = sizeof(struct sdhci_msm_dll_hsr) / sizeof(u32);
if (dll_hsr_table_len != dll_hsr_reg_count) {
dev_err(dev, "Number of HSR entries are not matching\n");
ret = -EINVAL;
} else {
msm_host->dll_hsr = (struct sdhci_msm_dll_hsr *)dll_hsr_table;
}
skip_hsr:
if (!msm_host->dll_hsr)
dev_info(dev, "Failed to get dll hsr settings from dt\n");
return ret;
}
/* Parse platform data */
static
struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev,
@ -2166,8 +2116,8 @@ struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev,
msm_host->regs_restore.is_supported =
of_property_read_bool(np, "qcom,restore-after-cx-collapse");
if (sdhci_msm_dt_parse_hsr_info(dev, msm_host))
goto out;
if (!of_property_read_u32(np, "qcom,ddr-config", &pdata->ddr_config))
pdata->rclk_wa = true;
return pdata;
out:
@ -3792,34 +3742,32 @@ void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
msm_host_offset->CORE_MCI_FIFO_CNT),
sdhci_msm_readl_relaxed(host,
msm_host_offset->CORE_MCI_STATUS));
pr_info("DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_STATUS),
pr_info("DLL cfg: 0x%08x | DLL sts: 0x%08x | SDCC ver: 0x%08x\n",
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_CONFIG),
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_STATUS),
sdhci_msm_readl_relaxed(host,
msm_host_offset->CORE_DLL_CONFIG_2));
pr_info("DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
msm_host_offset->CORE_MCI_VERSION));
pr_info("Vndr func: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n",
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_CONFIG_3),
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_USR_CTL),
sdhci_msm_readl_relaxed(host,
msm_host_offset->CORE_DDR_CONFIG));
pr_info("SDCC ver: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n",
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_MCI_VERSION),
msm_host_offset->CORE_VENDOR_SPEC),
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_VENDOR_SPEC_ADMA_ERR_ADDR0),
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_VENDOR_SPEC_ADMA_ERR_ADDR1));
pr_info("Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_VENDOR_SPEC),
pr_info("Vndr func2: 0x%08x | dll_config_2: 0x%08x\n",
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_VENDOR_SPEC_FUNC2),
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_VENDOR_SPEC3));
msm_host_offset->CORE_DLL_CONFIG_2));
pr_info("dll_config_3: 0x%08x | ddr_config: 0x%08x | dll_usr_ctl: 0x%08x\n",
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_CONFIG_3),
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DDR_CONFIG),
readl_relaxed(host->ioaddr +
msm_host_offset->CORE_DLL_USR_CTL));
/*
* tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits
* of CORE_TESTBUS_CONFIG register.
@ -5057,6 +5005,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
msm_host->mmc->caps2 |= msm_host->pdata->caps2;
msm_host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
msm_host->mmc->caps2 |= MMC_CAP2_HS400_POST_TUNING;
msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE;
msm_host->mmc->caps2 |= MMC_CAP2_SANITIZE;
msm_host->mmc->caps2 |= MMC_CAP2_MAX_DISCARD_SIZE;
msm_host->mmc->caps2 |= MMC_CAP2_SLEEP_AWAKE;

16
drivers/mmc/host/sdhci-msm.h
View file

@ -147,6 +147,8 @@ struct sdhci_msm_pltfm_data {
struct sdhci_msm_pm_qos_data pm_qos_data;
u32 ice_clk_max;
u32 ice_clk_min;
u32 ddr_config;
bool rclk_wa;
u32 *bus_clk_table;
unsigned char bus_clk_cnt;
};
@ -189,19 +191,6 @@ struct sdhci_msm_regs_restore {
u32 dll_usr_ctl;
};
/*
* DLL registers which needs be programmed with HSR settings.
* Add any new register only at the end and don't change the
* sequence.
*/
struct sdhci_msm_dll_hsr {
u32 dll_config;
u32 dll_config_2;
u32 dll_config_3;
u32 dll_usr_ctl;
u32 ddr_config;
};
struct sdhci_msm_debug_data {
struct mmc_host copy_mmc;
struct mmc_card copy_card;
@ -265,7 +254,6 @@ struct sdhci_msm_host {
struct workqueue_struct *pm_qos_wq;
bool use_cdr;
u32 transfer_mode;
struct sdhci_msm_dll_hsr *dll_hsr;
};
extern char *saved_command_line;

2
drivers/mmc/host/sdhci.c
View file

@ -4764,7 +4764,7 @@ int __sdhci_add_host(struct sdhci_host *host)
mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
(host->flags & SDHCI_USE_ADMA) ?
((host->flags & SDHCI_USE_64_BIT_DMA) ?
"64-bit ADMA" : "32-bit ADMA") : "",
"64-bit ADMA" : "32-bit ADMA") :
((host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"));
sdhci_enable_card_detection(host);