media: doc: media/v4l-drivers: Update Qualcomm CAMSS driver document for 8x96
Update the document to describe the support of Camera Subsystem on MSM8996/APQ8096. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Hans Verkuil <hansverk@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Todor Tomov
Mauro Carvalho Chehab
parent
cc8fe07398
commit
e1cf4b2f17
2 changed files with 164 additions and 33 deletions
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@ -7,34 +7,34 @@ Introduction
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------------
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This file documents the Qualcomm Camera Subsystem driver located under
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drivers/media/platform/qcom/camss-8x16.
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drivers/media/platform/qcom/camss.
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The current version of the driver supports the Camera Subsystem found on
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Qualcomm MSM8916 and APQ8016 processors.
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Qualcomm MSM8916/APQ8016 and MSM8996/APQ8096 processors.
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The driver implements V4L2, Media controller and V4L2 subdev interfaces.
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Camera sensor using V4L2 subdev interface in the kernel is supported.
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The driver is implemented using as a reference the Qualcomm Camera Subsystem
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driver for Android as found in Code Aurora [#f1]_.
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driver for Android as found in Code Aurora [#f1]_ [#f2]_.
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Qualcomm Camera Subsystem hardware
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----------------------------------
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The Camera Subsystem hardware found on 8x16 processors and supported by the
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driver consists of:
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The Camera Subsystem hardware found on 8x16 / 8x96 processors and supported by
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the driver consists of:
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- 2 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
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- 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
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A separate camera sensor can be connected to each of the CSIPHY module;
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- 2 CSID (CSI Decoder) modules. They handle the Protocol and Application layer
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of the CSI2 receivers. A CSID can decode data stream from any of the CSIPHY.
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Each CSID also contains a TG (Test Generator) block which can generate
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- 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application
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layer of the CSI2 receivers. A CSID can decode data stream from any of the
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CSIPHY. Each CSID also contains a TG (Test Generator) block which can generate
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artificial input data for test purposes;
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- ISPIF (ISP Interface) module. Handles the routing of the data streams from
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the CSIDs to the inputs of the VFE;
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- VFE (Video Front End) module. Contains a pipeline of image processing hardware
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blocks. The VFE has different input interfaces. The PIX (Pixel) input
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- 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
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hardware blocks. The VFE has different input interfaces. The PIX (Pixel) input
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interface feeds the input data to the image processing pipeline. The image
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processing pipeline contains also a scale and crop module at the end. Three
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RDI (Raw Dump Interface) input interfaces bypass the image processing
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@ -49,18 +49,33 @@ The current version of the driver supports:
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- Input from camera sensor via CSIPHY;
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- Generation of test input data by the TG in CSID;
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- RDI interface of VFE - raw dump of the input data to memory.
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- RDI interface of VFE
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Supported formats:
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- Raw dump of the input data to memory.
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- YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
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V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY);
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- MIPI RAW8 (8bit Bayer RAW - V4L2_PIX_FMT_SRGGB8 /
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V4L2_PIX_FMT_SGRBG8 / V4L2_PIX_FMT_SGBRG8 / V4L2_PIX_FMT_SBGGR8);
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- MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P /
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V4L2_PIX_FMT_SGBRG10P / V4L2_PIX_FMT_SGRBG10P / V4L2_PIX_FMT_SRGGB10P);
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- MIPI RAW12 (12bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB12P /
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V4L2_PIX_FMT_SGBRG12P / V4L2_PIX_FMT_SGRBG12P / V4L2_PIX_FMT_SRGGB12P).
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Supported formats:
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- YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
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V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY);
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- MIPI RAW8 (8bit Bayer RAW - V4L2_PIX_FMT_SRGGB8 /
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V4L2_PIX_FMT_SGRBG8 / V4L2_PIX_FMT_SGBRG8 / V4L2_PIX_FMT_SBGGR8);
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- MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P /
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V4L2_PIX_FMT_SGBRG10P / V4L2_PIX_FMT_SGRBG10P / V4L2_PIX_FMT_SRGGB10P /
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V4L2_PIX_FMT_Y10P);
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- MIPI RAW12 (12bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB12P /
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V4L2_PIX_FMT_SGBRG12P / V4L2_PIX_FMT_SGRBG12P / V4L2_PIX_FMT_SRGGB12P).
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- (8x96 only) MIPI RAW14 (14bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB14P /
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V4L2_PIX_FMT_SGBRG14P / V4L2_PIX_FMT_SGRBG14P / V4L2_PIX_FMT_SRGGB14P).
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- (8x96 only) Format conversion of the input data.
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Supported input formats:
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- MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P / V4L2_PIX_FMT_Y10P).
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Supported output formats:
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- Plain16 RAW10 (10bit unpacked Bayer RAW - V4L2_PIX_FMT_SBGGR10 / V4L2_PIX_FMT_Y10).
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- PIX interface of VFE
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@ -75,14 +90,16 @@ The current version of the driver supports:
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- NV12/NV21 (two plane YUV 4:2:0 - V4L2_PIX_FMT_NV12 / V4L2_PIX_FMT_NV21);
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- NV16/NV61 (two plane YUV 4:2:2 - V4L2_PIX_FMT_NV16 / V4L2_PIX_FMT_NV61).
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- (8x96 only) YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
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V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY).
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- Scaling support. Configuration of the VFE Encoder Scale module
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for downscalling with ratio up to 16x.
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- Cropping support. Configuration of the VFE Encoder Crop module.
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- Concurrent and independent usage of two data inputs - could be camera sensors
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and/or TG.
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- Concurrent and independent usage of two (8x96: three) data inputs -
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could be camera sensors and/or TG.
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Driver Architecture and Design
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@ -90,14 +107,14 @@ Driver Architecture and Design
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The driver implements the V4L2 subdev interface. With the goal to model the
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hardware links between the modules and to expose a clean, logical and usable
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interface, the driver is split into V4L2 sub-devices as follows:
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interface, the driver is split into V4L2 sub-devices as follows (8x16 / 8x96):
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- 2 CSIPHY sub-devices - each CSIPHY is represented by a single sub-device;
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- 2 CSID sub-devices - each CSID is represented by a single sub-device;
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- 2 ISPIF sub-devices - ISPIF is represented by a number of sub-devices equal
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to the number of CSID sub-devices;
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- 4 VFE sub-devices - VFE is represented by a number of sub-devices equal to
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the number of the input interfaces (3 RDI and 1 PIX).
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- 2 / 3 CSIPHY sub-devices - each CSIPHY is represented by a single sub-device;
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- 2 / 4 CSID sub-devices - each CSID is represented by a single sub-device;
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- 2 / 4 ISPIF sub-devices - ISPIF is represented by a number of sub-devices
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equal to the number of CSID sub-devices;
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- 4 / 8 VFE sub-devices - VFE is represented by a number of sub-devices equal to
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the number of the input interfaces (3 RDI and 1 PIX for each VFE).
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The considerations to split the driver in this particular way are as follows:
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@ -115,8 +132,8 @@ The considerations to split the driver in this particular way are as follows:
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Each VFE sub-device is linked to a separate video device node.
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The media controller pipeline graph is as follows (with connected two OV5645
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camera sensors):
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The media controller pipeline graph is as follows (with connected two / three
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OV5645 camera sensors):
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.. _qcom_camss_graph:
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@ -124,7 +141,13 @@ camera sensors):
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:alt: qcom_camss_graph.dot
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:align: center
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Media pipeline graph
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Media pipeline graph 8x16
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.. kernel-figure:: qcom_camss_8x96_graph.dot
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:alt: qcom_camss_8x96_graph.dot
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:align: center
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Media pipeline graph 8x96
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Implementation
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@ -149,8 +172,12 @@ APQ8016 Specification:
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https://developer.qualcomm.com/download/sd410/snapdragon-410-processor-device-specification.pdf
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Referenced 2016-11-24.
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APQ8096 Specification:
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https://developer.qualcomm.com/download/sd820e/qualcomm-snapdragon-820e-processor-apq8096sge-device-specification.pdf
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Referenced 2018-06-22.
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References
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----------
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.. [#f1] https://source.codeaurora.org/quic/la/kernel/msm-3.10/
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.. [#f2] https://source.codeaurora.org/quic/la/kernel/msm-3.18/
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104
Documentation/media/v4l-drivers/qcom_camss_8x96_graph.dot
Normal file
104
Documentation/media/v4l-drivers/qcom_camss_8x96_graph.dot
Normal file
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@ -0,0 +1,104 @@
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digraph board {
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rankdir=TB
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n00000001 [label="{{<port0> 0} | msm_csiphy0\n/dev/v4l-subdev0 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000001:port1 -> n0000000a:port0 [style=dashed]
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n00000001:port1 -> n0000000d:port0 [style=dashed]
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n00000001:port1 -> n00000010:port0 [style=dashed]
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n00000001:port1 -> n00000013:port0 [style=dashed]
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n00000004 [label="{{<port0> 0} | msm_csiphy1\n/dev/v4l-subdev1 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000004:port1 -> n0000000a:port0 [style=dashed]
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n00000004:port1 -> n0000000d:port0 [style=dashed]
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n00000004:port1 -> n00000010:port0 [style=dashed]
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n00000004:port1 -> n00000013:port0 [style=dashed]
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n00000007 [label="{{<port0> 0} | msm_csiphy2\n/dev/v4l-subdev2 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000007:port1 -> n0000000a:port0 [style=dashed]
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n00000007:port1 -> n0000000d:port0 [style=dashed]
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n00000007:port1 -> n00000010:port0 [style=dashed]
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n00000007:port1 -> n00000013:port0 [style=dashed]
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n0000000a [label="{{<port0> 0} | msm_csid0\n/dev/v4l-subdev3 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n0000000a:port1 -> n00000016:port0 [style=dashed]
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n0000000a:port1 -> n00000019:port0 [style=dashed]
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n0000000a:port1 -> n0000001c:port0 [style=dashed]
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n0000000a:port1 -> n0000001f:port0 [style=dashed]
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n0000000d [label="{{<port0> 0} | msm_csid1\n/dev/v4l-subdev4 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n0000000d:port1 -> n00000016:port0 [style=dashed]
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n0000000d:port1 -> n00000019:port0 [style=dashed]
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n0000000d:port1 -> n0000001c:port0 [style=dashed]
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n0000000d:port1 -> n0000001f:port0 [style=dashed]
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n00000010 [label="{{<port0> 0} | msm_csid2\n/dev/v4l-subdev5 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000010:port1 -> n00000016:port0 [style=dashed]
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n00000010:port1 -> n00000019:port0 [style=dashed]
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n00000010:port1 -> n0000001c:port0 [style=dashed]
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n00000010:port1 -> n0000001f:port0 [style=dashed]
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n00000013 [label="{{<port0> 0} | msm_csid3\n/dev/v4l-subdev6 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000013:port1 -> n00000016:port0 [style=dashed]
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n00000013:port1 -> n00000019:port0 [style=dashed]
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n00000013:port1 -> n0000001c:port0 [style=dashed]
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n00000013:port1 -> n0000001f:port0 [style=dashed]
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n00000016 [label="{{<port0> 0} | msm_ispif0\n/dev/v4l-subdev7 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000016:port1 -> n00000022:port0 [style=dashed]
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n00000016:port1 -> n0000002b:port0 [style=dashed]
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n00000016:port1 -> n00000034:port0 [style=dashed]
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n00000016:port1 -> n0000003d:port0 [style=dashed]
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n00000016:port1 -> n00000046:port0 [style=dashed]
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n00000016:port1 -> n0000004f:port0 [style=dashed]
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n00000016:port1 -> n00000058:port0 [style=dashed]
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n00000016:port1 -> n00000061:port0 [style=dashed]
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n00000019 [label="{{<port0> 0} | msm_ispif1\n/dev/v4l-subdev8 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000019:port1 -> n00000022:port0 [style=dashed]
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n00000019:port1 -> n0000002b:port0 [style=dashed]
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n00000019:port1 -> n00000034:port0 [style=dashed]
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n00000019:port1 -> n0000003d:port0 [style=dashed]
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n00000019:port1 -> n00000046:port0 [style=dashed]
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n00000019:port1 -> n0000004f:port0 [style=dashed]
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n00000019:port1 -> n00000058:port0 [style=dashed]
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n00000019:port1 -> n00000061:port0 [style=dashed]
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n0000001c [label="{{<port0> 0} | msm_ispif2\n/dev/v4l-subdev9 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n0000001c:port1 -> n00000022:port0 [style=dashed]
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n0000001c:port1 -> n0000002b:port0 [style=dashed]
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n0000001c:port1 -> n00000034:port0 [style=dashed]
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n0000001c:port1 -> n0000003d:port0 [style=dashed]
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n0000001c:port1 -> n00000046:port0 [style=dashed]
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n0000001c:port1 -> n0000004f:port0 [style=dashed]
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n0000001c:port1 -> n00000058:port0 [style=dashed]
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n0000001c:port1 -> n00000061:port0 [style=dashed]
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n0000001f [label="{{<port0> 0} | msm_ispif3\n/dev/v4l-subdev10 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n0000001f:port1 -> n00000022:port0 [style=dashed]
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n0000001f:port1 -> n0000002b:port0 [style=dashed]
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n0000001f:port1 -> n00000034:port0 [style=dashed]
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n0000001f:port1 -> n0000003d:port0 [style=dashed]
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n0000001f:port1 -> n00000046:port0 [style=dashed]
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n0000001f:port1 -> n0000004f:port0 [style=dashed]
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n0000001f:port1 -> n00000058:port0 [style=dashed]
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n0000001f:port1 -> n00000061:port0 [style=dashed]
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n00000022 [label="{{<port0> 0} | msm_vfe0_rdi0\n/dev/v4l-subdev11 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000022:port1 -> n00000025 [style=bold]
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n00000025 [label="msm_vfe0_video0\n/dev/video0", shape=box, style=filled, fillcolor=yellow]
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n0000002b [label="{{<port0> 0} | msm_vfe0_rdi1\n/dev/v4l-subdev12 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n0000002b:port1 -> n0000002e [style=bold]
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n0000002e [label="msm_vfe0_video1\n/dev/video1", shape=box, style=filled, fillcolor=yellow]
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n00000034 [label="{{<port0> 0} | msm_vfe0_rdi2\n/dev/v4l-subdev13 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000034:port1 -> n00000037 [style=bold]
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n00000037 [label="msm_vfe0_video2\n/dev/video2", shape=box, style=filled, fillcolor=yellow]
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n0000003d [label="{{<port0> 0} | msm_vfe0_pix\n/dev/v4l-subdev14 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n0000003d:port1 -> n00000040 [style=bold]
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n00000040 [label="msm_vfe0_video3\n/dev/video3", shape=box, style=filled, fillcolor=yellow]
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n00000046 [label="{{<port0> 0} | msm_vfe1_rdi0\n/dev/v4l-subdev15 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000046:port1 -> n00000049 [style=bold]
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n00000049 [label="msm_vfe1_video0\n/dev/video4", shape=box, style=filled, fillcolor=yellow]
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n0000004f [label="{{<port0> 0} | msm_vfe1_rdi1\n/dev/v4l-subdev16 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n0000004f:port1 -> n00000052 [style=bold]
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n00000052 [label="msm_vfe1_video1\n/dev/video5", shape=box, style=filled, fillcolor=yellow]
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n00000058 [label="{{<port0> 0} | msm_vfe1_rdi2\n/dev/v4l-subdev17 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000058:port1 -> n0000005b [style=bold]
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n0000005b [label="msm_vfe1_video2\n/dev/video6", shape=box, style=filled, fillcolor=yellow]
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n00000061 [label="{{<port0> 0} | msm_vfe1_pix\n/dev/v4l-subdev18 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
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n00000061:port1 -> n00000064 [style=bold]
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n00000064 [label="msm_vfe1_video3\n/dev/video7", shape=box, style=filled, fillcolor=yellow]
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n000000e2 [label="{{} | ov5645 3-0039\n/dev/v4l-subdev19 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
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n000000e2:port0 -> n00000004:port0 [style=bold]
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n000000e4 [label="{{} | ov5645 3-003a\n/dev/v4l-subdev20 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
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n000000e4:port0 -> n00000007:port0 [style=bold]
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n000000e6 [label="{{} | ov5645 3-003b\n/dev/v4l-subdev21 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
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n000000e6:port0 -> n00000001:port0 [style=bold]
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}
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