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Blackfin: MPU: support XIP in async flash memory

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The NOMPU code already supported executing in the async banks, so this
brings the MPU code in line.

Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Barry Song 2009-12-02 02:50:43 +00:00 committed by Mike Frysinger
parent d45e8db1b2
commit e187837b6f
1 changed files with 9 additions and 4 deletions
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13
arch/blackfin/kernel/cplb-mpu/cplbmgr.c
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@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu)
addr = L2_START;
d_data = L2_DMEMORY;
} else if (addr >= physical_mem_end) {
if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
&& (status & FAULT_USERSUPV)) {
addr &= ~0x3fffff;
if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
addr &= ~(4 * 1024 * 1024 - 1);
d_data &= ~PAGE_SIZE_4KB;
d_data |= PAGE_SIZE_4MB;
d_data |= CPLB_USER_RD | CPLB_USER_WR;
} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
&& (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
addr &= ~(1 * 1024 * 1024 - 1);
@ -203,7 +203,12 @@ static noinline int icplb_miss(unsigned int cpu)
addr = L2_START;
i_data = L2_IMEMORY;
} else if (addr >= physical_mem_end) {
if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
addr &= ~(4 * 1024 * 1024 - 1);
i_data &= ~PAGE_SIZE_4KB;
i_data |= PAGE_SIZE_4MB;
i_data |= CPLB_USER_RD;
} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
&& (status & FAULT_USERSUPV)) {
addr &= ~(1 * 1024 * 1024 - 1);
i_data &= ~PAGE_SIZE_4KB;