drm/radeon: 6xx/7xx non-kms endian fixes
agd5f: minor cleanups Signed-off-by: Cédric Cano <ccano@interfaceconcept.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
40b4a7599d
commit
dee54c40a1
3 changed files with 34 additions and 9 deletions
|
@ -137,9 +137,9 @@ set_shaders(struct drm_device *dev)
|
||||||
ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
|
ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
|
||||||
|
|
||||||
for (i = 0; i < r6xx_vs_size; i++)
|
for (i = 0; i < r6xx_vs_size; i++)
|
||||||
vs[i] = r6xx_vs[i];
|
vs[i] = cpu_to_le32(r6xx_vs[i]);
|
||||||
for (i = 0; i < r6xx_ps_size; i++)
|
for (i = 0; i < r6xx_ps_size; i++)
|
||||||
ps[i] = r6xx_ps[i];
|
ps[i] = cpu_to_le32(r6xx_ps[i]);
|
||||||
|
|
||||||
dev_priv->blit_vb->used = 512;
|
dev_priv->blit_vb->used = 512;
|
||||||
|
|
||||||
|
@ -192,6 +192,9 @@ set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
|
||||||
DRM_DEBUG("\n");
|
DRM_DEBUG("\n");
|
||||||
|
|
||||||
sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
|
sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
|
||||||
|
#ifdef __BIG_ENDIAN
|
||||||
|
sq_vtx_constant_word2 |= (2 << 30);
|
||||||
|
#endif
|
||||||
|
|
||||||
BEGIN_RING(9);
|
BEGIN_RING(9);
|
||||||
OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
|
OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
|
||||||
|
@ -291,7 +294,11 @@ draw_auto(drm_radeon_private_t *dev_priv)
|
||||||
OUT_RING(DI_PT_RECTLIST);
|
OUT_RING(DI_PT_RECTLIST);
|
||||||
|
|
||||||
OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
|
OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
|
||||||
|
#ifdef __BIG_ENDIAN
|
||||||
|
OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);
|
||||||
|
#else
|
||||||
OUT_RING(DI_INDEX_SIZE_16_BIT);
|
OUT_RING(DI_INDEX_SIZE_16_BIT);
|
||||||
|
#endif
|
||||||
|
|
||||||
OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
|
OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
|
||||||
OUT_RING(1);
|
OUT_RING(1);
|
||||||
|
|
|
@ -396,6 +396,9 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
|
||||||
r600_do_cp_stop(dev_priv);
|
r600_do_cp_stop(dev_priv);
|
||||||
|
|
||||||
RADEON_WRITE(R600_CP_RB_CNTL,
|
RADEON_WRITE(R600_CP_RB_CNTL,
|
||||||
|
#ifdef __BIG_ENDIAN
|
||||||
|
R600_BUF_SWAP_32BIT |
|
||||||
|
#endif
|
||||||
R600_RB_NO_UPDATE |
|
R600_RB_NO_UPDATE |
|
||||||
R600_RB_BLKSZ(15) |
|
R600_RB_BLKSZ(15) |
|
||||||
R600_RB_BUFSZ(3));
|
R600_RB_BUFSZ(3));
|
||||||
|
@ -486,9 +489,12 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
|
||||||
r600_do_cp_stop(dev_priv);
|
r600_do_cp_stop(dev_priv);
|
||||||
|
|
||||||
RADEON_WRITE(R600_CP_RB_CNTL,
|
RADEON_WRITE(R600_CP_RB_CNTL,
|
||||||
|
#ifdef __BIG_ENDIAN
|
||||||
|
R600_BUF_SWAP_32BIT |
|
||||||
|
#endif
|
||||||
R600_RB_NO_UPDATE |
|
R600_RB_NO_UPDATE |
|
||||||
(15 << 8) |
|
R600_RB_BLKSZ(15) |
|
||||||
(3 << 0));
|
R600_RB_BUFSZ(3));
|
||||||
|
|
||||||
RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
|
RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
|
||||||
RADEON_READ(R600_GRBM_SOFT_RESET);
|
RADEON_READ(R600_GRBM_SOFT_RESET);
|
||||||
|
@ -550,8 +556,12 @@ static void r600_test_writeback(drm_radeon_private_t *dev_priv)
|
||||||
|
|
||||||
if (!dev_priv->writeback_works) {
|
if (!dev_priv->writeback_works) {
|
||||||
/* Disable writeback to avoid unnecessary bus master transfer */
|
/* Disable writeback to avoid unnecessary bus master transfer */
|
||||||
RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
|
RADEON_WRITE(R600_CP_RB_CNTL,
|
||||||
RADEON_RB_NO_UPDATE);
|
#ifdef __BIG_ENDIAN
|
||||||
|
R600_BUF_SWAP_32BIT |
|
||||||
|
#endif
|
||||||
|
RADEON_READ(R600_CP_RB_CNTL) |
|
||||||
|
R600_RB_NO_UPDATE);
|
||||||
RADEON_WRITE(R600_SCRATCH_UMSK, 0);
|
RADEON_WRITE(R600_SCRATCH_UMSK, 0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -575,7 +585,11 @@ int r600_do_engine_reset(struct drm_device *dev)
|
||||||
|
|
||||||
RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
|
RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
|
||||||
cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
|
cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
|
||||||
RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
|
RADEON_WRITE(R600_CP_RB_CNTL,
|
||||||
|
#ifdef __BIG_ENDIAN
|
||||||
|
R600_BUF_SWAP_32BIT |
|
||||||
|
#endif
|
||||||
|
R600_RB_RPTR_WR_ENA);
|
||||||
|
|
||||||
RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
|
RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
|
||||||
RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
|
RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
|
||||||
|
@ -1838,7 +1852,10 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
|
||||||
+ dev_priv->gart_vm_start;
|
+ dev_priv->gart_vm_start;
|
||||||
}
|
}
|
||||||
RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
|
RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
|
||||||
rptr_addr & 0xffffffff);
|
#ifdef __BIG_ENDIAN
|
||||||
|
(2 << 0) |
|
||||||
|
#endif
|
||||||
|
(rptr_addr & 0xfffffffc));
|
||||||
RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
|
RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
|
||||||
upper_32_bits(rptr_addr));
|
upper_32_bits(rptr_addr));
|
||||||
|
|
||||||
|
@ -1889,7 +1906,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
|
||||||
{
|
{
|
||||||
u64 scratch_addr;
|
u64 scratch_addr;
|
||||||
|
|
||||||
scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
|
scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
|
||||||
scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
|
scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
|
||||||
scratch_addr += R600_SCRATCH_REG_OFFSET;
|
scratch_addr += R600_SCRATCH_REG_OFFSET;
|
||||||
scratch_addr >>= 8;
|
scratch_addr >>= 8;
|
||||||
|
|
|
@ -1524,6 +1524,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
|
||||||
#define R600_CP_RB_CNTL 0xc104
|
#define R600_CP_RB_CNTL 0xc104
|
||||||
# define R600_RB_BUFSZ(x) ((x) << 0)
|
# define R600_RB_BUFSZ(x) ((x) << 0)
|
||||||
# define R600_RB_BLKSZ(x) ((x) << 8)
|
# define R600_RB_BLKSZ(x) ((x) << 8)
|
||||||
|
# define R600_BUF_SWAP_32BIT (2 << 16)
|
||||||
# define R600_RB_NO_UPDATE (1 << 27)
|
# define R600_RB_NO_UPDATE (1 << 27)
|
||||||
# define R600_RB_RPTR_WR_ENA (1 << 31)
|
# define R600_RB_RPTR_WR_ENA (1 << 31)
|
||||||
#define R600_CP_RB_RPTR_WR 0xc108
|
#define R600_CP_RB_RPTR_WR 0xc108
|
||||||
|
|
Loading…
Reference in a new issue