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[MIPS] TX49XX has prefetch.

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The TX49XX has the prefetch instruction.  It supports only Pref_Load
(hint 0).  Actually changes in this patch except for Kconfig are not
have any effects, I added these changes to prevent misuse of unsupported
hints.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto 2006-03-17 12:59:22 +09:00 committed by Ralf Baechle
parent c6281edb1d
commit de862b488e
3 changed files with 10 additions and 2 deletions
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1
arch/mips/Kconfig
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@ -1160,6 +1160,7 @@ config CPU_R4X00
config CPU_TX49XX
bool "R49XX"
depends on SYS_HAS_CPU_TX49XX
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL

1
arch/mips/mm/c-r4k.c
View file

@ -786,6 +786,7 @@ static void __init probe_pcache(void)
c->dcache.waybit = 0;
c->options |= MIPS_CPU_CACHE_CDEX_P;
c->options |= MIPS_CPU_PREFETCH;
break;
case CPU_R4000PC:

10
arch/mips/mm/pg-r4k.c
View file

@ -124,7 +124,7 @@ static inline void build_nop(void)
static inline void build_src_pref(int advance)
{
if (!(load_offset & (cpu_dcache_line_size() - 1))) {
if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) {
union mips_instruction mi;
mi.i_format.opcode = pref_op;
@ -166,7 +166,7 @@ static inline void build_load_reg(int reg)
static inline void build_dst_pref(int advance)
{
if (!(store_offset & (cpu_dcache_line_size() - 1))) {
if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) {
union mips_instruction mi;
mi.i_format.opcode = pref_op;
@ -340,6 +340,12 @@ void __init build_clear_page(void)
if (cpu_has_prefetch) {
switch (current_cpu_data.cputype) {
case CPU_TX49XX:
/* TX49 supports only Pref_Load */
pref_offset_clear = 0;
pref_offset_copy = 0;
break;
case CPU_RM9000:
/*
* As a workaround for erratum G105 which make the