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spi: omap2-mcspi: Fix native cs with new set_cs

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GPIO chip select patch series appears to have broken the native chip select
support. This patch pulls the manual native chip select toggling out of
the transfer_one routine and adds a set_cs routine.

Tested natively on AM3354 with SPI serial flash on spi0cs0.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Michael Welling <mwelling@ieee.org>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Michael Welling 2015-05-12 12:38:57 -05:00 committed by Mark Brown
parent bc7f9bbc80
commit ddcad7e906
1 changed files with 11 additions and 22 deletions
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27
drivers/spi/spi-omap2-mcspi.c
View file

@ -243,18 +243,21 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
} }
static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
{ {
u32 l; u32 l;
if (spi->controller_state) {
l = mcspi_cached_chconf0(spi); l = mcspi_cached_chconf0(spi);
if (cs_active)
l |= OMAP2_MCSPI_CHCONF_FORCE; if (enable)
else
l &= ~OMAP2_MCSPI_CHCONF_FORCE; l &= ~OMAP2_MCSPI_CHCONF_FORCE;
else
l |= OMAP2_MCSPI_CHCONF_FORCE;
mcspi_write_chconf0(spi, l); mcspi_write_chconf0(spi, l);
} }
}
static void omap2_mcspi_set_master_mode(struct spi_master *master) static void omap2_mcspi_set_master_mode(struct spi_master *master)
{ {
@ -1075,7 +1078,6 @@ static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
struct spi_master *master; struct spi_master *master;
struct omap2_mcspi_dma *mcspi_dma; struct omap2_mcspi_dma *mcspi_dma;
int cs_active = 0;
struct omap2_mcspi_cs *cs; struct omap2_mcspi_cs *cs;
struct omap2_mcspi_device_config *cd; struct omap2_mcspi_device_config *cd;
int par_override = 0; int par_override = 0;
@ -1118,11 +1120,6 @@ static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
} }
if (!cs_active) {
omap2_mcspi_force_cs(spi, 1);
cs_active = 1;
}
chconf = mcspi_cached_chconf0(spi); chconf = mcspi_cached_chconf0(spi);
chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
@ -1169,12 +1166,6 @@ static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
if (t->delay_usecs) if (t->delay_usecs)
udelay(t->delay_usecs); udelay(t->delay_usecs);
/* ignore the "leave it on after last xfer" hint */
if (t->cs_change) {
omap2_mcspi_force_cs(spi, 0);
cs_active = 0;
}
omap2_mcspi_set_enable(spi, 0); omap2_mcspi_set_enable(spi, 0);
if (mcspi->fifo_depth > 0) if (mcspi->fifo_depth > 0)
@ -1187,9 +1178,6 @@ static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
status = omap2_mcspi_setup_transfer(spi, NULL); status = omap2_mcspi_setup_transfer(spi, NULL);
} }
if (cs_active)
omap2_mcspi_force_cs(spi, 0);
if (cd && cd->cs_per_word) { if (cd && cd->cs_per_word) {
chconf = mcspi->ctx.modulctrl; chconf = mcspi->ctx.modulctrl;
chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
@ -1334,6 +1322,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
master->setup = omap2_mcspi_setup; master->setup = omap2_mcspi_setup;
master->auto_runtime_pm = true; master->auto_runtime_pm = true;
master->transfer_one = omap2_mcspi_transfer_one; master->transfer_one = omap2_mcspi_transfer_one;
master->set_cs = omap2_mcspi_set_cs;
master->cleanup = omap2_mcspi_cleanup; master->cleanup = omap2_mcspi_cleanup;
master->dev.of_node = node; master->dev.of_node = node;
master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;