vmlfb: framebuffer driver for Intel Vermilion Range
Add the Intel Vermilion Range framebuffer support. Signed-off-by: Alan Hourihane <alanh@tungstengraphics.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Alan Hourihane
Linus Torvalds
parent
249bdbbf0d
commit
dbe7e429fe
9 changed files with 1981 additions and 0 deletions
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@ -882,6 +882,22 @@ config FB_I810_I2C
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select FB_DDC
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help
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config FB_LE80578
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tristate "Intel LE80578 (Vermilion) support"
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depends on FB && PCI && X86
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select FB_MODE_HELPERS
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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This driver supports the LE80578 (Vermilion Range) chipset
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config FB_CARILLO_RANCH
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tristate "Intel Carillo Ranch support"
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depends on FB_LE80578 && FB && PCI && X86
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help
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This driver supports the LE80578 (Carillo Ranch) board
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config FB_INTEL
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tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)"
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depends on FB && EXPERIMENTAL && PCI && X86
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@ -56,6 +56,7 @@ obj-$(CONFIG_FB_IMSTT) += imsttfb.o
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obj-$(CONFIG_FB_FM2) += fm2fb.o
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obj-$(CONFIG_FB_CYBLA) += cyblafb.o
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obj-$(CONFIG_FB_TRIDENT) += tridentfb.o
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obj-$(CONFIG_FB_LE80578) += vermilion/
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obj-$(CONFIG_FB_S3) += s3fb.o
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obj-$(CONFIG_FB_STI) += stifb.o
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obj-$(CONFIG_FB_FFB) += ffb.o sbuslib.o
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@ -63,3 +63,11 @@ config BACKLIGHT_PROGEAR
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help
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If you have a Frontpath ProGear say Y to enable the
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backlight driver.
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config BACKLIGHT_CARILLO_RANCH
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tristate "Intel Carillo Ranch Backlight Driver"
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depends on BACKLIGHT_CLASS_DEVICE && LCD_CLASS_DEVICE && PCI && X86 && FB_LE80578
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default n
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help
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If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
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backlight driver.
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@ -6,3 +6,4 @@ obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o
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obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
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obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
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obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
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obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
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287
drivers/video/backlight/cr_bllcd.c
Normal file
287
drivers/video/backlight/cr_bllcd.c
Normal file
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@ -0,0 +1,287 @@
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/*
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* Copyright (c) Intel Corp. 2007.
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* All Rights Reserved.
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*
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* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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* develop this driver.
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*
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* This file is part of the Carillo Ranch video subsystem driver.
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* The Carillo Ranch video subsystem driver is free software;
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* you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The Carillo Ranch video subsystem driver is distributed
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* in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this driver; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Authors:
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Alan Hourihane <alanh-at-tungstengraphics-dot-com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mutex.h>
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#include <linux/fb.h>
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#include <linux/backlight.h>
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#include <linux/lcd.h>
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#include <linux/pci.h>
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#include <asm/uaccess.h>
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/* The LVDS- and panel power controls sits on the
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* GPIO port of the ISA bridge.
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*/
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#define CRVML_DEVICE_LPC 0x27B8
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#define CRVML_REG_GPIOBAR 0x48
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#define CRVML_REG_GPIOEN 0x4C
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#define CRVML_GPIOEN_BIT (1 << 4)
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#define CRVML_PANEL_PORT 0x38
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#define CRVML_LVDS_ON 0x00000001
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#define CRVML_PANEL_ON 0x00000002
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#define CRVML_BACKLIGHT_OFF 0x00000004
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/* The PLL Clock register sits on Host bridge */
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#define CRVML_DEVICE_MCH 0x5001
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#define CRVML_REG_MCHBAR 0x44
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#define CRVML_REG_MCHEN 0x54
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#define CRVML_MCHEN_BIT (1 << 28)
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#define CRVML_MCHMAP_SIZE 4096
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#define CRVML_REG_CLOCK 0xc3c
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#define CRVML_CLOCK_SHIFT 8
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#define CRVML_CLOCK_MASK 0x00000f00
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static struct pci_dev *lpc_dev;
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static u32 gpio_bar;
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struct cr_panel {
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struct backlight_device *cr_backlight_device;
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struct lcd_device *cr_lcd_device;
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};
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static int cr_backlight_set_intensity(struct backlight_device *bd)
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{
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int intensity = bd->props.brightness;
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u32 addr = gpio_bar + CRVML_PANEL_PORT;
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u32 cur = inl(addr);
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if (bd->props.power == FB_BLANK_UNBLANK)
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intensity = FB_BLANK_UNBLANK;
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if (bd->props.fb_blank == FB_BLANK_UNBLANK)
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intensity = FB_BLANK_UNBLANK;
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if (bd->props.power == FB_BLANK_POWERDOWN)
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intensity = FB_BLANK_POWERDOWN;
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if (bd->props.fb_blank == FB_BLANK_POWERDOWN)
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intensity = FB_BLANK_POWERDOWN;
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if (intensity == FB_BLANK_UNBLANK) { /* FULL ON */
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cur &= ~CRVML_BACKLIGHT_OFF;
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outl(cur, addr);
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} else if (intensity == FB_BLANK_POWERDOWN) { /* OFF */
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cur |= CRVML_BACKLIGHT_OFF;
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outl(cur, addr);
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} /* anything else, don't bother */
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return 0;
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}
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static int cr_backlight_get_intensity(struct backlight_device *bd)
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{
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u32 addr = gpio_bar + CRVML_PANEL_PORT;
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u32 cur = inl(addr);
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u8 intensity;
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if (cur & CRVML_BACKLIGHT_OFF)
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intensity = FB_BLANK_POWERDOWN;
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else
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intensity = FB_BLANK_UNBLANK;
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return intensity;
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}
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static struct backlight_ops cr_backlight_ops = {
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.get_brightness = cr_backlight_get_intensity,
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.update_status = cr_backlight_set_intensity,
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};
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static void cr_panel_on(void)
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{
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u32 addr = gpio_bar + CRVML_PANEL_PORT;
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u32 cur = inl(addr);
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if (!(cur & CRVML_PANEL_ON)) {
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/* Make sure LVDS controller is down. */
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if (cur & 0x00000001) {
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cur &= ~CRVML_LVDS_ON;
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outl(cur, addr);
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}
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/* Power up Panel */
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schedule_timeout(HZ / 10);
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cur |= CRVML_PANEL_ON;
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outl(cur, addr);
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}
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/* Power up LVDS controller */
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if (!(cur & CRVML_LVDS_ON)) {
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schedule_timeout(HZ / 10);
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outl(cur | CRVML_LVDS_ON, addr);
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}
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}
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static void cr_panel_off(void)
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{
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u32 addr = gpio_bar + CRVML_PANEL_PORT;
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u32 cur = inl(addr);
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/* Power down LVDS controller first to avoid high currents */
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if (cur & CRVML_LVDS_ON) {
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cur &= ~CRVML_LVDS_ON;
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outl(cur, addr);
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}
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if (cur & CRVML_PANEL_ON) {
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schedule_timeout(HZ / 10);
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outl(cur & ~CRVML_PANEL_ON, addr);
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}
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}
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static int cr_lcd_set_power(struct lcd_device *ld, int power)
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{
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if (power == FB_BLANK_UNBLANK)
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cr_panel_on();
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if (power == FB_BLANK_POWERDOWN)
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cr_panel_off();
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return 0;
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}
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static struct lcd_ops cr_lcd_ops = {
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.set_power = cr_lcd_set_power,
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};
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static int cr_backlight_probe(struct platform_device *pdev)
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{
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struct cr_panel *crp;
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u8 dev_en;
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crp = kzalloc(sizeof(crp), GFP_KERNEL);
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if (crp == NULL)
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return -ENOMEM;
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lpc_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
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CRVML_DEVICE_LPC, NULL);
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if (!lpc_dev) {
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printk("INTEL CARILLO RANCH LPC not found.\n");
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return -ENODEV;
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}
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pci_read_config_byte(lpc_dev, CRVML_REG_GPIOEN, &dev_en);
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if (!(dev_en & CRVML_GPIOEN_BIT)) {
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printk(KERN_ERR
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"Carillo Ranch GPIO device was not enabled.\n");
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pci_dev_put(lpc_dev);
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return -ENODEV;
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}
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crp->cr_backlight_device = backlight_device_register("cr-backlight",
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&pdev->dev, NULL,
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&cr_backlight_ops);
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if (IS_ERR(crp->cr_backlight_device)) {
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pci_dev_put(lpc_dev);
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return PTR_ERR(crp->cr_backlight_device);
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}
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crp->cr_lcd_device = lcd_device_register("cr-lcd",
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&pdev->dev,
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&cr_lcd_ops);
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if (IS_ERR(crp->cr_lcd_device)) {
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pci_dev_put(lpc_dev);
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return PTR_ERR(crp->cr_backlight_device);
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}
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pci_read_config_dword(lpc_dev, CRVML_REG_GPIOBAR,
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&gpio_bar);
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gpio_bar &= ~0x3F;
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crp->cr_backlight_device->props.power = FB_BLANK_UNBLANK;
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crp->cr_backlight_device->props.brightness = 0;
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crp->cr_backlight_device->props.max_brightness = 0;
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cr_backlight_set_intensity(crp->cr_backlight_device);
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cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_UNBLANK);
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platform_set_drvdata(pdev, crp);
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return 0;
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}
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static int cr_backlight_remove(struct platform_device *pdev)
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{
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struct cr_panel *crp = platform_get_drvdata(pdev);
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crp->cr_backlight_device->props.power = FB_BLANK_POWERDOWN;
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crp->cr_backlight_device->props.brightness = 0;
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crp->cr_backlight_device->props.max_brightness = 0;
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cr_backlight_set_intensity(crp->cr_backlight_device);
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cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_POWERDOWN);
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backlight_device_unregister(crp->cr_backlight_device);
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lcd_device_unregister(crp->cr_lcd_device);
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pci_dev_put(lpc_dev);
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return 0;
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}
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static struct platform_driver cr_backlight_driver = {
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.probe = cr_backlight_probe,
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.remove = cr_backlight_remove,
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.driver = {
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.name = "cr_backlight",
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},
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};
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static struct platform_device *crp;
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static int __init cr_backlight_init(void)
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{
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int ret = platform_driver_register(&cr_backlight_driver);
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if (!ret) {
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crp = platform_device_alloc("cr_backlight", -1);
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if (!crp)
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return -ENOMEM;
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ret = platform_device_add(crp);
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if (ret) {
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platform_device_put(crp);
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platform_driver_unregister(&cr_backlight_driver);
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}
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}
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printk("Carillo Ranch Backlight Driver Initialized.\n");
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return ret;
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}
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static void __exit cr_backlight_exit(void)
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{
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platform_device_unregister(crp);
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platform_driver_unregister(&cr_backlight_driver);
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}
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module_init(cr_backlight_init);
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module_exit(cr_backlight_exit);
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MODULE_AUTHOR("Tungsten Graphics Inc.");
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MODULE_DESCRIPTION("Carillo Ranch Backlight Driver");
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MODULE_LICENSE("GPL");
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5
drivers/video/vermilion/Makefile
Normal file
5
drivers/video/vermilion/Makefile
Normal file
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@ -0,0 +1,5 @@
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obj-$(CONFIG_FB_LE80578) += vmlfb.o
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obj-$(CONFIG_FB_CARILLO_RANCH) += crvml.o
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vmlfb-objs := vermilion.o
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crvml-objs := cr_pll.o
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208
drivers/video/vermilion/cr_pll.c
Normal file
208
drivers/video/vermilion/cr_pll.c
Normal file
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@ -0,0 +1,208 @@
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/*
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* Copyright (c) Intel Corp. 2007.
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* All Rights Reserved.
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*
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* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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* develop this driver.
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*
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* This file is part of the Carillo Ranch video subsystem driver.
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* The Carillo Ranch video subsystem driver is free software;
|
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* you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
|
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*
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* The Carillo Ranch video subsystem driver is distributed
|
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* in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
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* You should have received a copy of the GNU General Public License
|
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* along with this driver; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Authors:
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Alan Hourihane <alanh-at-tungstengraphics-dot-com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/fb.h>
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#include "vermilion.h"
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/* The PLL Clock register sits on Host bridge */
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#define CRVML_DEVICE_MCH 0x5001
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#define CRVML_REG_MCHBAR 0x44
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#define CRVML_REG_MCHEN 0x54
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#define CRVML_MCHEN_BIT (1 << 28)
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#define CRVML_MCHMAP_SIZE 4096
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#define CRVML_REG_CLOCK 0xc3c
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#define CRVML_CLOCK_SHIFT 8
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#define CRVML_CLOCK_MASK 0x00000f00
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static struct pci_dev *mch_dev;
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static u32 mch_bar;
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static void __iomem *mch_regs_base;
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static u32 saved_clock;
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static const unsigned crvml_clocks[] = {
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6750,
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13500,
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27000,
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29700,
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37125,
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54000,
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59400,
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74250,
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120000
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/*
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* There are more clocks, but they are disabled on the CR board.
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*/
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};
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static const u32 crvml_clock_bits[] = {
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0x0a,
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0x09,
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0x08,
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0x07,
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0x06,
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0x05,
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0x04,
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0x03,
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0x0b
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};
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static const unsigned crvml_num_clocks = ARRAY_SIZE(crvml_clocks);
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static int crvml_sys_restore(struct vml_sys *sys)
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{
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void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
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iowrite32(saved_clock, clock_reg);
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ioread32(clock_reg);
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return 0;
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}
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static int crvml_sys_save(struct vml_sys *sys)
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{
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void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
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saved_clock = ioread32(clock_reg);
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return 0;
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}
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static int crvml_nearest_index(const struct vml_sys *sys, int clock)
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{
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int i;
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int cur_index = 0;
|
||||
int cur_diff;
|
||||
int diff;
|
||||
|
||||
cur_diff = clock - crvml_clocks[0];
|
||||
cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff;
|
||||
for (i = 1; i < crvml_num_clocks; ++i) {
|
||||
diff = clock - crvml_clocks[i];
|
||||
diff = (diff < 0) ? -diff : diff;
|
||||
if (diff < cur_diff) {
|
||||
cur_index = i;
|
||||
cur_diff = diff;
|
||||
}
|
||||
}
|
||||
return cur_index;
|
||||
}
|
||||
|
||||
static int crvml_nearest_clock(const struct vml_sys *sys, int clock)
|
||||
{
|
||||
return crvml_clocks[crvml_nearest_index(sys, clock)];
|
||||
}
|
||||
|
||||
static int crvml_set_clock(struct vml_sys *sys, int clock)
|
||||
{
|
||||
void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
|
||||
int index;
|
||||
u32 clock_val;
|
||||
|
||||
index = crvml_nearest_index(sys, clock);
|
||||
|
||||
if (crvml_clocks[index] != clock)
|
||||
return -EINVAL;
|
||||
|
||||
clock_val = ioread32(clock_reg) & ~CRVML_CLOCK_MASK;
|
||||
clock_val = crvml_clock_bits[index] << CRVML_CLOCK_SHIFT;
|
||||
iowrite32(clock_val, clock_reg);
|
||||
ioread32(clock_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct vml_sys cr_pll_ops = {
|
||||
.name = "Carillo Ranch",
|
||||
.save = crvml_sys_save,
|
||||
.restore = crvml_sys_restore,
|
||||
.set_clock = crvml_set_clock,
|
||||
.nearest_clock = crvml_nearest_clock,
|
||||
};
|
||||
|
||||
static int __init cr_pll_init(void)
|
||||
{
|
||||
int err;
|
||||
u32 dev_en;
|
||||
|
||||
mch_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
CRVML_DEVICE_MCH, NULL);
|
||||
if (!mch_dev) {
|
||||
printk(KERN_ERR
|
||||
"Could not find Carillo Ranch MCH device.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pci_read_config_dword(mch_dev, CRVML_REG_MCHEN, &dev_en);
|
||||
if (!(dev_en & CRVML_MCHEN_BIT)) {
|
||||
printk(KERN_ERR
|
||||
"Carillo Ranch MCH device was not enabled.\n");
|
||||
pci_dev_put(mch_dev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pci_read_config_dword(mch_dev, CRVML_REG_MCHBAR,
|
||||
&mch_bar);
|
||||
mch_regs_base =
|
||||
ioremap_nocache(mch_bar, CRVML_MCHMAP_SIZE);
|
||||
if (!mch_regs_base) {
|
||||
printk(KERN_ERR
|
||||
"Carillo Ranch MCH device was not enabled.\n");
|
||||
pci_dev_put(mch_dev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
err = vmlfb_register_subsys(&cr_pll_ops);
|
||||
if (err) {
|
||||
printk(KERN_ERR
|
||||
"Carillo Ranch failed to initialize vml_sys.\n");
|
||||
pci_dev_put(mch_dev);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit cr_pll_exit(void)
|
||||
{
|
||||
vmlfb_unregister_subsys(&cr_pll_ops);
|
||||
|
||||
iounmap(mch_regs_base);
|
||||
pci_dev_put(mch_dev);
|
||||
}
|
||||
|
||||
module_init(cr_pll_init);
|
||||
module_exit(cr_pll_exit);
|
||||
|
||||
MODULE_AUTHOR("Tungsten Graphics Inc.");
|
||||
MODULE_DESCRIPTION("Carillo Ranch PLL Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
1195
drivers/video/vermilion/vermilion.c
Normal file
1195
drivers/video/vermilion/vermilion.c
Normal file
File diff suppressed because it is too large
Load diff
260
drivers/video/vermilion/vermilion.h
Normal file
260
drivers/video/vermilion/vermilion.h
Normal file
|
|
@ -0,0 +1,260 @@
|
|||
/*
|
||||
* Copyright (c) Intel Corp. 2007.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
|
||||
* develop this driver.
|
||||
*
|
||||
* This file is part of the Vermilion Range fb driver.
|
||||
* The Vermilion Range fb driver is free software;
|
||||
* you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The Vermilion Range fb driver is distributed
|
||||
* in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this driver; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
* Authors:
|
||||
* Thomas Hellström <thomas-at-tungstengraphics-dot-com>
|
||||
*/
|
||||
|
||||
#ifndef _VERMILION_H_
|
||||
#define _VERMILION_H_
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/pci.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#define VML_DEVICE_GPU 0x5002
|
||||
#define VML_DEVICE_VDC 0x5009
|
||||
|
||||
#define VML_VRAM_AREAS 3
|
||||
#define VML_MAX_XRES 1024
|
||||
#define VML_MAX_YRES 768
|
||||
#define VML_MAX_XRES_VIRTUAL 1040
|
||||
|
||||
/*
|
||||
* Display controller registers:
|
||||
*/
|
||||
|
||||
/* Display controller 10-bit color representation */
|
||||
|
||||
#define VML_R_MASK 0x3FF00000
|
||||
#define VML_R_SHIFT 20
|
||||
#define VML_G_MASK 0x000FFC00
|
||||
#define VML_G_SHIFT 10
|
||||
#define VML_B_MASK 0x000003FF
|
||||
#define VML_B_SHIFT 0
|
||||
|
||||
/* Graphics plane control */
|
||||
#define VML_DSPCCNTR 0x00072180
|
||||
#define VML_GFX_ENABLE 0x80000000
|
||||
#define VML_GFX_GAMMABYPASS 0x40000000
|
||||
#define VML_GFX_ARGB1555 0x0C000000
|
||||
#define VML_GFX_RGB0888 0x18000000
|
||||
#define VML_GFX_ARGB8888 0x1C000000
|
||||
#define VML_GFX_ALPHACONST 0x02000000
|
||||
#define VML_GFX_ALPHAMULT 0x01000000
|
||||
#define VML_GFX_CONST_ALPHA 0x000000FF
|
||||
|
||||
/* Graphics plane start address. Pixel aligned. */
|
||||
#define VML_DSPCADDR 0x00072184
|
||||
|
||||
/* Graphics plane stride register. */
|
||||
#define VML_DSPCSTRIDE 0x00072188
|
||||
|
||||
/* Graphics plane position register. */
|
||||
#define VML_DSPCPOS 0x0007218C
|
||||
#define VML_POS_YMASK 0x0FFF0000
|
||||
#define VML_POS_YSHIFT 16
|
||||
#define VML_POS_XMASK 0x00000FFF
|
||||
#define VML_POS_XSHIFT 0
|
||||
|
||||
/* Graphics plane height and width */
|
||||
#define VML_DSPCSIZE 0x00072190
|
||||
#define VML_SIZE_HMASK 0x0FFF0000
|
||||
#define VML_SIZE_HSHIFT 16
|
||||
#define VML_SISE_WMASK 0x00000FFF
|
||||
#define VML_SIZE_WSHIFT 0
|
||||
|
||||
/* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
|
||||
#define VML_DSPCGAMLUT 0x00072200
|
||||
|
||||
/* Pixel video output configuration register */
|
||||
#define VML_PVOCONFIG 0x00061140
|
||||
#define VML_CONFIG_BASE 0x80000000
|
||||
#define VML_CONFIG_PIXEL_SWAP 0x04000000
|
||||
#define VML_CONFIG_DE_INV 0x01000000
|
||||
#define VML_CONFIG_HREF_INV 0x00400000
|
||||
#define VML_CONFIG_VREF_INV 0x00100000
|
||||
#define VML_CONFIG_CLK_INV 0x00040000
|
||||
#define VML_CONFIG_CLK_DIV2 0x00010000
|
||||
#define VML_CONFIG_ESTRB_INV 0x00008000
|
||||
|
||||
/* Pipe A Horizontal total register */
|
||||
#define VML_HTOTAL_A 0x00060000
|
||||
#define VML_HTOTAL_MASK 0x1FFF0000
|
||||
#define VML_HTOTAL_SHIFT 16
|
||||
#define VML_HTOTAL_VAL 8192
|
||||
#define VML_HACTIVE_MASK 0x000007FF
|
||||
#define VML_HACTIVE_SHIFT 0
|
||||
#define VML_HACTIVE_VAL 4096
|
||||
|
||||
/* Pipe A Horizontal Blank register */
|
||||
#define VML_HBLANK_A 0x00060004
|
||||
#define VML_HBLANK_END_MASK 0x1FFF0000
|
||||
#define VML_HBLANK_END_SHIFT 16
|
||||
#define VML_HBLANK_END_VAL 8192
|
||||
#define VML_HBLANK_START_MASK 0x00001FFF
|
||||
#define VML_HBLANK_START_SHIFT 0
|
||||
#define VML_HBLANK_START_VAL 8192
|
||||
|
||||
/* Pipe A Horizontal Sync register */
|
||||
#define VML_HSYNC_A 0x00060008
|
||||
#define VML_HSYNC_END_MASK 0x1FFF0000
|
||||
#define VML_HSYNC_END_SHIFT 16
|
||||
#define VML_HSYNC_END_VAL 8192
|
||||
#define VML_HSYNC_START_MASK 0x00001FFF
|
||||
#define VML_HSYNC_START_SHIFT 0
|
||||
#define VML_HSYNC_START_VAL 8192
|
||||
|
||||
/* Pipe A Vertical total register */
|
||||
#define VML_VTOTAL_A 0x0006000C
|
||||
#define VML_VTOTAL_MASK 0x1FFF0000
|
||||
#define VML_VTOTAL_SHIFT 16
|
||||
#define VML_VTOTAL_VAL 8192
|
||||
#define VML_VACTIVE_MASK 0x000007FF
|
||||
#define VML_VACTIVE_SHIFT 0
|
||||
#define VML_VACTIVE_VAL 4096
|
||||
|
||||
/* Pipe A Vertical Blank register */
|
||||
#define VML_VBLANK_A 0x00060010
|
||||
#define VML_VBLANK_END_MASK 0x1FFF0000
|
||||
#define VML_VBLANK_END_SHIFT 16
|
||||
#define VML_VBLANK_END_VAL 8192
|
||||
#define VML_VBLANK_START_MASK 0x00001FFF
|
||||
#define VML_VBLANK_START_SHIFT 0
|
||||
#define VML_VBLANK_START_VAL 8192
|
||||
|
||||
/* Pipe A Vertical Sync register */
|
||||
#define VML_VSYNC_A 0x00060014
|
||||
#define VML_VSYNC_END_MASK 0x1FFF0000
|
||||
#define VML_VSYNC_END_SHIFT 16
|
||||
#define VML_VSYNC_END_VAL 8192
|
||||
#define VML_VSYNC_START_MASK 0x00001FFF
|
||||
#define VML_VSYNC_START_SHIFT 0
|
||||
#define VML_VSYNC_START_VAL 8192
|
||||
|
||||
/* Pipe A Source Image size (minus one - equal to active size)
|
||||
* Programmable while pipe is enabled.
|
||||
*/
|
||||
#define VML_PIPEASRC 0x0006001C
|
||||
#define VML_PIPEASRC_HMASK 0x0FFF0000
|
||||
#define VML_PIPEASRC_HSHIFT 16
|
||||
#define VML_PIPEASRC_VMASK 0x00000FFF
|
||||
#define VML_PIPEASRC_VSHIFT 0
|
||||
|
||||
/* Pipe A Border Color Pattern register (10 bit color) */
|
||||
#define VML_BCLRPAT_A 0x00060020
|
||||
|
||||
/* Pipe A Canvas Color register (10 bit color) */
|
||||
#define VML_CANVSCLR_A 0x00060024
|
||||
|
||||
/* Pipe A Configuration register */
|
||||
#define VML_PIPEACONF 0x00070008
|
||||
#define VML_PIPE_BASE 0x00000000
|
||||
#define VML_PIPE_ENABLE 0x80000000
|
||||
#define VML_PIPE_FORCE_BORDER 0x02000000
|
||||
#define VML_PIPE_PLANES_OFF 0x00080000
|
||||
#define VML_PIPE_ARGB_OUTPUT_MODE 0x00040000
|
||||
|
||||
/* Pipe A FIFO setting */
|
||||
#define VML_DSPARB 0x00070030
|
||||
#define VML_FIFO_DEFAULT 0x00001D9C
|
||||
|
||||
/* MDVO rcomp status & pads control register */
|
||||
#define VML_RCOMPSTAT 0x00070048
|
||||
#define VML_MDVO_VDC_I_RCOMP 0x80000000
|
||||
#define VML_MDVO_POWERSAVE_OFF 0x00000008
|
||||
#define VML_MDVO_PAD_ENABLE 0x00000004
|
||||
#define VML_MDVO_PULLDOWN_ENABLE 0x00000001
|
||||
|
||||
struct vml_par {
|
||||
struct pci_dev *vdc;
|
||||
u64 vdc_mem_base;
|
||||
u64 vdc_mem_size;
|
||||
char __iomem *vdc_mem;
|
||||
|
||||
struct pci_dev *gpu;
|
||||
u64 gpu_mem_base;
|
||||
u64 gpu_mem_size;
|
||||
char __iomem *gpu_mem;
|
||||
|
||||
atomic_t refcount;
|
||||
};
|
||||
|
||||
struct vram_area {
|
||||
unsigned long logical;
|
||||
unsigned long phys;
|
||||
unsigned long size;
|
||||
unsigned order;
|
||||
};
|
||||
|
||||
struct vml_info {
|
||||
struct fb_info info;
|
||||
struct vml_par *par;
|
||||
struct list_head head;
|
||||
struct vram_area vram[VML_VRAM_AREAS];
|
||||
u64 vram_start;
|
||||
u64 vram_contig_size;
|
||||
u32 num_areas;
|
||||
void __iomem *vram_logical;
|
||||
u32 pseudo_palette[16];
|
||||
u32 stride;
|
||||
u32 bytes_per_pixel;
|
||||
atomic_t vmas;
|
||||
int cur_blank_mode;
|
||||
int pipe_disabled;
|
||||
};
|
||||
|
||||
/*
|
||||
* Subsystem
|
||||
*/
|
||||
|
||||
struct vml_sys {
|
||||
char *name;
|
||||
|
||||
/*
|
||||
* Save / Restore;
|
||||
*/
|
||||
|
||||
int (*save) (struct vml_sys * sys);
|
||||
int (*restore) (struct vml_sys * sys);
|
||||
|
||||
/*
|
||||
* PLL programming;
|
||||
*/
|
||||
|
||||
int (*set_clock) (struct vml_sys * sys, int clock);
|
||||
int (*nearest_clock) (const struct vml_sys * sys, int clock);
|
||||
};
|
||||
|
||||
extern int vmlfb_register_subsys(struct vml_sys *sys);
|
||||
extern void vmlfb_unregister_subsys(struct vml_sys *sys);
|
||||
|
||||
#define VML_READ32(_par, _offset) \
|
||||
(ioread32((_par)->vdc_mem + (_offset)))
|
||||
#define VML_WRITE32(_par, _offset, _value) \
|
||||
iowrite32(_value, (_par)->vdc_mem + (_offset))
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue