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sky2: put PHY in sleep when down

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Put PHY int sleep mode (from vendor sk98lin 10.50 driver) when the
network device is brought down.

Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Stephen Hemminger 2008-05-14 17:04:16 -07:00 committed by Jeff Garzik
parent b96936da7a
commit db99b98885
2 changed files with 45 additions and 2 deletions
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40
drivers/net/sky2.c
View file

@ -641,11 +641,47 @@ static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
{ {
u32 reg1; u32 reg1;
u16 ctrl;
/* release GPHY Control reset */
sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
/* release GMAC reset */
sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
if (hw->flags & SKY2_HW_NEWER_PHY) {
/* select page 2 to access MAC control register */
gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
/* allow GMII Power Down */
ctrl &= ~PHY_M_MAC_GMIF_PUP;
gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
/* set page register back to 0 */
gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
}
/* setup General Purpose Control Register */
gma_write16(hw, port, GM_GP_CTRL,
GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
if (hw->chip_id != CHIP_ID_YUKON_EC) {
if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
/* enable Power Down */
ctrl |= PHY_M_PC_POW_D_ENA;
gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
}
/* set IEEE compatible Power Down Mode (dev. #4.99) */
gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
}
sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
reg1 |= phy_power[port]; reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
sky2_pci_write32(hw, PCI_DEV_REG1, reg1); sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
} }

7
drivers/net/sky2.h
View file

@ -1143,6 +1143,12 @@ enum {
PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
}; };
/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
enum {
PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */
PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */
};
/* for 10/100 Fast Ethernet PHY (88E3082 only) */ /* for 10/100 Fast Ethernet PHY (88E3082 only) */
enum { enum {
PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
@ -1411,6 +1417,7 @@ enum {
/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
enum { enum {
PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */
PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
PHY_M_MAC_MD_COPPER = 5,/* Copper only */ PHY_M_MAC_MD_COPPER = 5,/* Copper only */
PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */