Merge branch 'clkfwk'
This commit is contained in:
Paul Mundt
commit
da9f0ac2f1
5 changed files with 113 additions and 135 deletions
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@ -475,7 +475,7 @@ source "drivers/cpufreq/Kconfig"
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config SH_CPU_FREQ
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tristate "SuperH CPU Frequency driver"
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depends on CPU_FREQ && CPU_SH4 && BROKEN
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depends on CPU_FREQ
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select CPU_FREQ_TABLE
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help
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This adds the cpufreq driver for SuperH. At present, only
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@ -229,6 +229,22 @@ void clk_recalc_rate(struct clk *clk)
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}
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EXPORT_SYMBOL_GPL(clk_recalc_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (likely(clk->ops && clk->ops->round_rate)) {
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unsigned long flags, rounded;
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spin_lock_irqsave(&clock_lock, flags);
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rounded = clk->ops->round_rate(clk, rate);
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spin_unlock_irqrestore(&clock_lock, flags);
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return rounded;
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}
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return clk_get_rate(clk);
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}
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EXPORT_SYMBOL_GPL(clk_round_rate);
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/*
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* Returns a clock. Note that we first try to use device id on the bus
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* and clock name. If this fails, we try to use clock name only.
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@ -387,9 +387,24 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
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return err;
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}
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static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long parent_rate = clk->parent->rate;
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int div;
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/* look for multiplier/divisor pair */
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div = sh7722_find_divisors(parent_rate, rate);
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if (div < 0)
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return clk->rate;
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/* calculate new value of clock rate */
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return parent_rate * 2 / div;
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}
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static struct clk_ops sh7722_frqcr_clk_ops = {
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.recalc = sh7722_frqcr_recalc,
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.set_rate = sh7722_frqcr_set_rate,
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.round_rate = sh7722_frqcr_round_rate,
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};
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/*
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@ -3,89 +3,51 @@
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*
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* cpufreq driver for the SuperH processors.
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*
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* Copyright (C) 2002, 2003, 2004, 2005 Paul Mundt
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* Copyright (C) 2002 - 2007 Paul Mundt
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* Copyright (C) 2002 M. R. Brown
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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* Clock framework bits from arch/avr32/mach-at32ap/cpufreq.c
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*
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* Copyright (C) 2004-2007 Atmel Corporation
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/cpufreq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/cpumask.h>
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#include <linux/smp.h>
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#include <linux/sched.h> /* set_cpus_allowed() */
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/processor.h>
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#include <asm/watchdog.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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#include <asm/clock.h>
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/*
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* For SuperH, each policy change requires that we change the IFC, BFC, and
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* PFC at the same time. Here we define sane values that won't trash the
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* system.
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*
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* Note the max set is computed at runtime, we use the divisors that we booted
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* with to setup our maximum operating frequencies.
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*/
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struct clock_set {
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unsigned int ifc;
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unsigned int bfc;
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unsigned int pfc;
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} clock_sets[] = {
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#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH2)
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{ 0, 0, 0 }, /* not implemented yet */
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#elif defined(CONFIG_CPU_SH4)
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{ 4, 8, 8 }, /* min - IFC: 1/4, BFC: 1/8, PFC: 1/8 */
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{ 1, 2, 2 }, /* max - IFC: 1, BFC: 1/2, PFC: 1/2 */
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#endif
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};
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static struct clk *cpuclk;
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#define MIN_CLOCK_SET 0
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#define MAX_CLOCK_SET (ARRAY_SIZE(clock_sets) - 1)
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/*
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* For the time being, we only support two frequencies, which in turn are
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* aimed at the POWERSAVE and PERFORMANCE policies, which in turn are derived
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* directly from the respective min/max clock sets. Technically we could
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* support a wider range of frequencies, but these vary far too much for each
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* CPU subtype (and we'd have to construct a frequency table for each subtype).
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*
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* Maybe something to implement in the future..
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*/
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#define SH_FREQ_MAX 0
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#define SH_FREQ_MIN 1
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static struct cpufreq_frequency_table sh_freqs[] = {
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{ SH_FREQ_MAX, 0 },
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{ SH_FREQ_MIN, 0 },
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{ 0, CPUFREQ_TABLE_END },
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};
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static void sh_cpufreq_update_clocks(unsigned int set)
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static unsigned int sh_cpufreq_get(unsigned int cpu)
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{
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current_cpu_data.cpu_clock = current_cpu_data.master_clock / clock_sets[set].ifc;
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current_cpu_data.bus_clock = current_cpu_data.master_clock / clock_sets[set].bfc;
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current_cpu_data.module_clock = current_cpu_data.master_clock / clock_sets[set].pfc;
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current_cpu_data.loops_per_jiffy = loops_per_jiffy;
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return (clk_get_rate(cpuclk) + 500) / 1000;
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}
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/* XXX: This needs to be split out per CPU and CPU subtype. */
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/*
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* Here we notify other drivers of the proposed change and the final change.
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*/
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static int sh_cpufreq_setstate(unsigned int cpu, unsigned int set)
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static int sh_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned short frqcr = ctrl_inw(FRQCR);
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unsigned int cpu = policy->cpu;
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cpumask_t cpus_allowed;
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struct cpufreq_freqs freqs;
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long freq;
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if (!cpu_online(cpu))
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return -ENODEV;
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@ -95,125 +57,109 @@ static int sh_cpufreq_setstate(unsigned int cpu, unsigned int set)
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BUG_ON(smp_processor_id() != cpu);
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freqs.cpu = cpu;
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freqs.old = current_cpu_data.cpu_clock / 1000;
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freqs.new = (current_cpu_data.master_clock / clock_sets[set].ifc) / 1000;
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/* Convert target_freq from kHz to Hz */
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freq = clk_round_rate(cpuclk, target_freq * 1000);
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if (freq < (policy->min * 1000) || freq > (policy->max * 1000))
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return -EINVAL;
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pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
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freqs.cpu = cpu;
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freqs.old = sh_cpufreq_get(cpu);
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freqs.new = (freq + 500) / 1000;
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freqs.flags = 0;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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#if defined(CONFIG_CPU_SH3)
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frqcr |= (newstate & 0x4000) << 14;
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frqcr |= (newstate & 0x000c) << 2;
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#elif defined(CONFIG_CPU_SH4)
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/*
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* FRQCR.PLL2EN is 1, we need to allow the PLL to stabilize by
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* initializing the WDT.
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*/
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if (frqcr & (1 << 9)) {
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__u8 csr;
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/*
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* Set the overflow period to the highest available,
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* in this case a 1/4096 division ratio yields a 5.25ms
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* overflow period. See asm-sh/watchdog.h for more
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* information and a range of other divisors.
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*/
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csr = sh_wdt_read_csr();
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csr |= WTCSR_CKS_4096;
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sh_wdt_write_csr(csr);
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sh_wdt_write_cnt(0);
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}
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frqcr &= 0x0e00; /* Clear ifc, bfc, pfc */
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frqcr |= get_ifc_value(clock_sets[set].ifc) << 6;
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frqcr |= get_bfc_value(clock_sets[set].bfc) << 3;
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frqcr |= get_pfc_value(clock_sets[set].pfc);
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#endif
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ctrl_outw(frqcr, FRQCR);
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sh_cpufreq_update_clocks(set);
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set_cpus_allowed(current, cpus_allowed);
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clk_set_rate(cpuclk, freq);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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pr_debug("cpufreq: set frequency %lu Hz\n", freq);
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return 0;
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}
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static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned int min_freq, max_freq;
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unsigned int ifc, bfc, pfc;
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printk(KERN_INFO "cpufreq: SuperH CPU frequency driver.\n");
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if (!cpu_online(policy->cpu))
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return -ENODEV;
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/* Update our maximum clock set */
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get_current_frequency_divisors(&ifc, &bfc, &pfc);
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clock_sets[MAX_CLOCK_SET].ifc = ifc;
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clock_sets[MAX_CLOCK_SET].bfc = bfc;
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clock_sets[MAX_CLOCK_SET].pfc = pfc;
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/* Convert from Hz to kHz */
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max_freq = current_cpu_data.cpu_clock / 1000;
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min_freq = (current_cpu_data.master_clock / clock_sets[MIN_CLOCK_SET].ifc) / 1000;
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sh_freqs[SH_FREQ_MAX].frequency = max_freq;
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sh_freqs[SH_FREQ_MIN].frequency = min_freq;
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cpuclk = clk_get(NULL, "cpu_clk");
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if (IS_ERR(cpuclk)) {
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printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
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return PTR_ERR(cpuclk);
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}
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/* cpuinfo and default policy values */
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cpuinfo.min_freq = (clk_round_rate(cpuclk, 1) + 500) / 1000;
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policy->cpuinfo.max_freq = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000;
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policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
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policy->cur = max_freq;
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return cpufreq_frequency_table_cpuinfo(policy, &sh_freqs[0]);
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cur = sh_cpufreq_get(policy->cpu);
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policy->min = policy->cpuinfo.min_freq;
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policy->max = policy->cpuinfo.max_freq;
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/*
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* Catch the cases where the clock framework hasn't been wired up
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* properly to support scaling.
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*/
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if (unlikely(policy->min == policy->max)) {
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printk(KERN_ERR "cpufreq: clock framework rate rounding "
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"not supported on this CPU.\n");
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clk_put(cpuclk);
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return -EINVAL;
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}
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printk(KERN_INFO "cpufreq: Frequencies - Minimum %u.%03u MHz, "
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"Maximum %u.%03u MHz.\n",
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policy->min / 1000, policy->min % 1000,
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policy->max / 1000, policy->max % 1000);
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return 0;
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}
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static int sh_cpufreq_verify(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, &sh_freqs[0]);
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cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
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policy->cpuinfo.max_freq);
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return 0;
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}
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static int sh_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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static int sh_cpufreq_exit(struct cpufreq_policy *policy)
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{
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unsigned int set, idx = 0;
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if (cpufreq_frequency_table_target(policy, &sh_freqs[0], target_freq, relation, &idx))
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return -EINVAL;
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set = (idx == SH_FREQ_MIN) ? MIN_CLOCK_SET : MAX_CLOCK_SET;
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sh_cpufreq_setstate(policy->cpu, set);
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clk_put(cpuclk);
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return 0;
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}
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static struct cpufreq_driver sh_cpufreq_driver = {
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.owner = THIS_MODULE,
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.name = "SH cpufreq",
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.name = "sh",
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.init = sh_cpufreq_cpu_init,
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.verify = sh_cpufreq_verify,
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.target = sh_cpufreq_target,
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.get = sh_cpufreq_get,
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.exit = sh_cpufreq_exit,
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};
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static int __init sh_cpufreq_init(void)
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static int __init sh_cpufreq_module_init(void)
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{
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if (!current_cpu_data.cpu_clock)
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return -EINVAL;
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if (cpufreq_register_driver(&sh_cpufreq_driver))
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return -EINVAL;
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return 0;
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return cpufreq_register_driver(&sh_cpufreq_driver);
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}
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static void __exit sh_cpufreq_exit(void)
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static void __exit sh_cpufreq_module_exit(void)
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{
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cpufreq_unregister_driver(&sh_cpufreq_driver);
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}
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module_init(sh_cpufreq_init);
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module_exit(sh_cpufreq_exit);
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module_init(sh_cpufreq_module_init);
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module_exit(sh_cpufreq_module_exit);
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MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
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MODULE_DESCRIPTION("cpufreq driver for SuperH");
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MODULE_LICENSE("GPL");
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@ -14,6 +14,7 @@ struct clk_ops {
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void (*disable)(struct clk *clk);
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void (*recalc)(struct clk *clk);
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int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
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long (*round_rate)(struct clk *clk, unsigned long rate);
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};
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struct clk {
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