usb: dwc2: Check core parameters
Check that core parameters have valid values and adjust them if they aren't. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
John Youn
Felipe Balbi
parent
57b8e23511
commit
d936e666ae
1 changed files with 185 additions and 0 deletions
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@ -377,6 +377,189 @@ static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
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}
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}
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static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
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{
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int valid = 1;
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switch (hsotg->params.otg_cap) {
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case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
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if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
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valid = 0;
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break;
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case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
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switch (hsotg->hw_params.op_mode) {
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case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
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case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
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case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
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case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
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break;
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default:
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valid = 0;
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break;
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}
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break;
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case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
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/* always valid */
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break;
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default:
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valid = 0;
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break;
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}
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if (!valid)
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dwc2_set_param_otg_cap(hsotg);
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}
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static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
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{
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int valid = 0;
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u32 hs_phy_type;
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u32 fs_phy_type;
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hs_phy_type = hsotg->hw_params.hs_phy_type;
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fs_phy_type = hsotg->hw_params.fs_phy_type;
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switch (hsotg->params.phy_type) {
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case DWC2_PHY_TYPE_PARAM_FS:
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if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
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valid = 1;
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break;
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case DWC2_PHY_TYPE_PARAM_UTMI:
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if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
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(hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
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valid = 1;
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break;
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case DWC2_PHY_TYPE_PARAM_ULPI:
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if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
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(hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
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valid = 1;
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break;
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default:
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break;
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}
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if (!valid)
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dwc2_set_param_phy_type(hsotg);
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}
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static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
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{
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int valid = 1;
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int phy_type = hsotg->params.phy_type;
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int speed = hsotg->params.speed;
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switch (speed) {
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case DWC2_SPEED_PARAM_HIGH:
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if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
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(phy_type == DWC2_PHY_TYPE_PARAM_FS))
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valid = 0;
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break;
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case DWC2_SPEED_PARAM_FULL:
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case DWC2_SPEED_PARAM_LOW:
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break;
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default:
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valid = 0;
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break;
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}
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if (!valid)
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dwc2_set_param_speed(hsotg);
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}
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static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
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{
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int valid = 0;
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int param = hsotg->params.phy_utmi_width;
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int width = hsotg->hw_params.utmi_phy_data_width;
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switch (width) {
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case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
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valid = (param == 8);
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break;
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case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
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valid = (param == 16);
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break;
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case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
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valid = (param == 8 || param == 16);
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break;
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}
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if (!valid)
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dwc2_set_param_phy_utmi_width(hsotg);
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}
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#define CHECK_RANGE(_param, _min, _max, _def) do { \
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if ((hsotg->params._param) < (_min) || \
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(hsotg->params._param) > (_max)) { \
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dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
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__func__, #_param, hsotg->params._param); \
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hsotg->params._param = (_def); \
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} \
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} while (0)
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#define CHECK_BOOL(_param, _check) do { \
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if (hsotg->params._param && !(_check)) { \
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dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
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__func__, #_param, hsotg->params._param); \
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hsotg->params._param = false; \
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} \
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} while (0)
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static void dwc2_check_params(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_hw_params *hw = &hsotg->hw_params;
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struct dwc2_core_params *p = &hsotg->params;
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bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
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dwc2_check_param_otg_cap(hsotg);
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dwc2_check_param_phy_type(hsotg);
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dwc2_check_param_speed(hsotg);
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dwc2_check_param_phy_utmi_width(hsotg);
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CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
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CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
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CHECK_BOOL(i2c_enable, hw->i2c_enable);
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CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
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CHECK_RANGE(max_packet_count,
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15, hw->max_packet_count,
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hw->max_packet_count);
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CHECK_RANGE(max_transfer_size,
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2047, hw->max_transfer_size,
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hw->max_transfer_size);
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if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
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(hsotg->dr_mode == USB_DR_MODE_OTG)) {
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CHECK_BOOL(host_dma, dma_capable);
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CHECK_BOOL(dma_desc_enable, p->host_dma);
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CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
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CHECK_BOOL(host_ls_low_power_phy_clk,
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p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
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CHECK_RANGE(host_channels,
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1, hw->host_channels,
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hw->host_channels);
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CHECK_RANGE(host_rx_fifo_size,
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16, hw->rx_fifo_size,
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hw->rx_fifo_size);
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CHECK_RANGE(host_nperio_tx_fifo_size,
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16, hw->host_nperio_tx_fifo_size,
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hw->host_nperio_tx_fifo_size);
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CHECK_RANGE(host_perio_tx_fifo_size,
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16, hw->host_perio_tx_fifo_size,
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hw->host_perio_tx_fifo_size);
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}
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if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
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(hsotg->dr_mode == USB_DR_MODE_OTG)) {
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CHECK_BOOL(g_dma, dma_capable);
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CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
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CHECK_RANGE(g_rx_fifo_size,
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16, hw->rx_fifo_size,
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hw->rx_fifo_size);
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CHECK_RANGE(g_np_tx_fifo_size,
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16, hw->dev_nperio_tx_fifo_size,
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hw->dev_nperio_tx_fifo_size);
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}
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}
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/*
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* Gets host hardware parameters. Forces host mode if not currently in
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* host mode. Should be called immediately after a core soft reset in
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@ -591,5 +774,7 @@ int dwc2_init_params(struct dwc2_hsotg *hsotg)
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dwc2_set_default_params(hsotg);
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dwc2_get_device_properties(hsotg);
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dwc2_check_params(hsotg);
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return 0;
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}
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