Merge branch 'pci/gavin-msi-cleanup' into next
* pci/gavin-msi-cleanup: vfio-pci: Use cached MSI/MSI-X capabilities vfio-pci: Use PCI_MSIX_TABLE_BIR, not PCI_MSIX_FLAGS_BIRMASK PCI: Remove "extern" from function declarations PCI: Use PCI_MSIX_TABLE_BIR, not PCI_MSIX_FLAGS_BIRMASK PCI: Drop msi_mask_reg() and remove drivers/pci/msi.h PCI: Use msix_table_size() directly, drop multi_msix_capable() PCI: Drop msix_table_offset_reg() and msix_pba_offset_reg() macros PCI: Drop is_64bit_address() and is_mask_bit_support() macros PCI: Drop msi_data_reg() macro PCI: Drop msi_lower_address_reg() and msi_upper_address_reg() macros PCI: Drop msi_control_reg() macro and use PCI_MSI_FLAGS directly PCI: Use cached MSI/MSI-X offsets from dev, not from msi_desc PCI: Clean up MSI/MSI-X capability #defines PCI: Use cached MSI-X cap while enabling MSI-X PCI: Use cached MSI cap while enabling MSI interrupts PCI: Remove MSI/MSI-X cap check in pci_msi_check_device() PCI: Cache MSI/MSI-X capability offsets in struct pci_dev PCI: Use u8, not int, for PM capability offset [SCSI] megaraid_sas: Use correct #define for MSI-X capability
This commit is contained in:
Bjorn Helgaas
commit
d4f09c5d7f
8 changed files with 118 additions and 157 deletions
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@ -22,10 +22,12 @@
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#include <linux/slab.h>
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#include "pci.h"
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#include "msi.h"
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static int pci_msi_enable = 1;
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#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
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/* Arch hooks */
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#ifndef arch_msi_check_device
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@ -111,32 +113,26 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq)
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}
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#endif
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static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
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static void msi_set_enable(struct pci_dev *dev, int enable)
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{
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u16 control;
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BUG_ON(!pos);
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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control &= ~PCI_MSI_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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static void msix_set_enable(struct pci_dev *dev, int enable)
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{
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int pos;
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u16 control;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
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control &= ~PCI_MSIX_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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}
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
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control &= ~PCI_MSIX_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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}
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static inline __attribute_const__ u32 msi_mask(unsigned x)
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@ -247,18 +243,18 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
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} else {
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struct pci_dev *dev = entry->dev;
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int pos = entry->msi_attrib.pos;
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int pos = dev->msi_cap;
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u16 data;
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pci_read_config_dword(dev, msi_lower_address_reg(pos),
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&msg->address_lo);
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
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&msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_read_config_dword(dev, msi_upper_address_reg(pos),
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&msg->address_hi);
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pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
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&msg->address_hi);
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pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
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} else {
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msg->address_hi = 0;
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pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
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pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
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}
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msg->data = data;
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}
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@ -302,24 +298,24 @@ void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
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} else {
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struct pci_dev *dev = entry->dev;
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int pos = entry->msi_attrib.pos;
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int pos = dev->msi_cap;
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u16 msgctl;
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pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
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msgctl &= ~PCI_MSI_FLAGS_QSIZE;
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msgctl |= entry->msi_attrib.multiple << 4;
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pci_write_config_word(dev, msi_control_reg(pos), msgctl);
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
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pci_write_config_dword(dev, msi_lower_address_reg(pos),
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msg->address_lo);
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
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msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_write_config_dword(dev, msi_upper_address_reg(pos),
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msg->address_hi);
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pci_write_config_word(dev, msi_data_reg(pos, 1),
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msg->data);
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
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msg->address_hi);
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pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
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msg->data);
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} else {
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pci_write_config_word(dev, msi_data_reg(pos, 0),
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msg->data);
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pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
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msg->data);
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}
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}
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entry->msg = *msg;
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@ -391,7 +387,6 @@ static void pci_intx_for_msi(struct pci_dev *dev, int enable)
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static void __pci_restore_msi_state(struct pci_dev *dev)
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{
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int pos;
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u16 control;
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struct msi_desc *entry;
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@ -399,22 +394,20 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
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return;
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entry = irq_get_msi_desc(dev->irq);
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pos = entry->msi_attrib.pos;
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pci_intx_for_msi(dev, 0);
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msi_set_enable(dev, pos, 0);
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msi_set_enable(dev, 0);
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arch_restore_msi_irqs(dev, dev->irq);
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
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control &= ~PCI_MSI_FLAGS_QSIZE;
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control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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static void __pci_restore_msix_state(struct pci_dev *dev)
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{
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int pos;
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struct msi_desc *entry;
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u16 control;
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@ -422,13 +415,12 @@ static void __pci_restore_msix_state(struct pci_dev *dev)
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return;
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BUG_ON(list_empty(&dev->msi_list));
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entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
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pos = entry->msi_attrib.pos;
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pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
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/* route the table */
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pci_intx_for_msi(dev, 0);
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control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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list_for_each_entry(entry, &dev->msi_list, list) {
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arch_restore_msi_irqs(dev, entry->irq);
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@ -436,7 +428,7 @@ static void __pci_restore_msix_state(struct pci_dev *dev)
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}
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control &= ~PCI_MSIX_FLAGS_MASKALL;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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}
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void pci_restore_msi_state(struct pci_dev *dev)
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@ -552,27 +544,27 @@ static int populate_msi_sysfs(struct pci_dev *pdev)
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static int msi_capability_init(struct pci_dev *dev, int nvec)
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{
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struct msi_desc *entry;
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int pos, ret;
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int ret;
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u16 control;
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unsigned mask;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
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msi_set_enable(dev, 0); /* Disable MSI during set up */
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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/* MSI Entry Initialization */
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entry = alloc_msi_entry(dev);
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if (!entry)
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return -ENOMEM;
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entry->msi_attrib.is_msix = 0;
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entry->msi_attrib.is_64 = is_64bit_address(control);
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entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
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entry->msi_attrib.entry_nr = 0;
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entry->msi_attrib.maskbit = is_mask_bit_support(control);
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entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
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entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
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entry->msi_attrib.pos = pos;
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entry->msi_attrib.pos = dev->msi_cap;
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entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
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entry->mask_pos = dev->msi_cap + (control & PCI_MSI_FLAGS_64BIT) ?
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PCI_MSI_MASK_64 : PCI_MSI_MASK_32;
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/* All MSIs are unmasked by default, Mask them all */
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if (entry->msi_attrib.maskbit)
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pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
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@ -598,31 +590,30 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
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/* Set MSI enabled bits */
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pci_intx_for_msi(dev, 0);
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msi_set_enable(dev, pos, 1);
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msi_set_enable(dev, 1);
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dev->msi_enabled = 1;
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dev->irq = entry->irq;
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return 0;
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}
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static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
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unsigned nr_entries)
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static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
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{
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resource_size_t phys_addr;
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u32 table_offset;
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u8 bir;
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pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
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bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
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table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
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pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
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&table_offset);
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bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
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table_offset &= PCI_MSIX_TABLE_OFFSET;
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phys_addr = pci_resource_start(dev, bir) + table_offset;
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return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
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}
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static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
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void __iomem *base, struct msix_entry *entries,
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int nvec)
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static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
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struct msix_entry *entries, int nvec)
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{
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struct msi_desc *entry;
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int i;
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@ -642,7 +633,7 @@ static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
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entry->msi_attrib.is_64 = 1;
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entry->msi_attrib.entry_nr = entries[i].entry;
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entry->msi_attrib.default_irq = dev->irq;
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entry->msi_attrib.pos = pos;
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entry->msi_attrib.pos = dev->msix_cap;
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entry->mask_base = base;
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list_add_tail(&entry->list, &dev->msi_list);
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@ -652,7 +643,7 @@ static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
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}
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static void msix_program_entries(struct pci_dev *dev,
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struct msix_entry *entries)
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struct msix_entry *entries)
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{
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struct msi_desc *entry;
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int i = 0;
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@ -682,23 +673,22 @@ static void msix_program_entries(struct pci_dev *dev,
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static int msix_capability_init(struct pci_dev *dev,
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struct msix_entry *entries, int nvec)
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{
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int pos, ret;
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int ret;
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u16 control;
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void __iomem *base;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
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/* Ensure MSI-X is disabled while it is set up */
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control &= ~PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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/* Request & Map MSI-X table region */
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base = msix_map_region(dev, pos, multi_msix_capable(control));
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base = msix_map_region(dev, msix_table_size(control));
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if (!base)
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return -ENOMEM;
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ret = msix_setup_entries(dev, pos, base, entries, nvec);
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ret = msix_setup_entries(dev, base, entries, nvec);
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if (ret)
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return ret;
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@ -712,7 +702,7 @@ static int msix_capability_init(struct pci_dev *dev,
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* interrupts coming in before they're fully set up.
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*/
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control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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msix_program_entries(dev, entries);
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@ -727,7 +717,7 @@ static int msix_capability_init(struct pci_dev *dev,
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dev->msix_enabled = 1;
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control &= ~PCI_MSIX_FLAGS_MASKALL;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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return 0;
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@ -795,9 +785,6 @@ static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
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if (ret)
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return ret;
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if (!pci_find_capability(dev, type))
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return -EINVAL;
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return 0;
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}
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@ -816,13 +803,13 @@ static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
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*/
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int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
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{
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int status, pos, maxvec;
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int status, maxvec;
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u16 msgctl;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (!pos)
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if (!dev->msi_cap)
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return -EINVAL;
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
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maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
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if (nvec > maxvec)
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return maxvec;
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@ -847,14 +834,13 @@ EXPORT_SYMBOL(pci_enable_msi_block);
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int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
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{
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int ret, pos, nvec;
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int ret, nvec;
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u16 msgctl;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (!pos)
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if (!dev->msi_cap)
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return -EINVAL;
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
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ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
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if (maxvec)
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@ -876,21 +862,19 @@ void pci_msi_shutdown(struct pci_dev *dev)
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struct msi_desc *desc;
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u32 mask;
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u16 ctrl;
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unsigned pos;
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if (!pci_msi_enable || !dev || !dev->msi_enabled)
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return;
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BUG_ON(list_empty(&dev->msi_list));
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desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
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pos = desc->msi_attrib.pos;
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msi_set_enable(dev, pos, 0);
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||||
msi_set_enable(dev, 0);
|
||||
pci_intx_for_msi(dev, 1);
|
||||
dev->msi_enabled = 0;
|
||||
|
||||
/* Return the device with MSI unmasked as initial states */
|
||||
pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
|
||||
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
|
||||
mask = msi_capable_mask(ctrl);
|
||||
/* Keep cached state to be restored */
|
||||
__msi_mask_irq(desc, mask, ~mask);
|
||||
|
|
@ -917,15 +901,13 @@ EXPORT_SYMBOL(pci_disable_msi);
|
|||
*/
|
||||
int pci_msix_table_size(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u16 control;
|
||||
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
||||
if (!pos)
|
||||
if (!dev->msix_cap)
|
||||
return 0;
|
||||
|
||||
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
||||
return multi_msix_capable(control);
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
||||
return msix_table_size(control);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -948,7 +930,7 @@ int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
|
|||
int status, nr_entries;
|
||||
int i, j;
|
||||
|
||||
if (!entries)
|
||||
if (!entries || !dev->msix_cap)
|
||||
return -EINVAL;
|
||||
|
||||
status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
|
||||
|
|
@ -1048,15 +1030,17 @@ EXPORT_SYMBOL(pci_msi_enabled);
|
|||
|
||||
void pci_msi_init_pci_dev(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
INIT_LIST_HEAD(&dev->msi_list);
|
||||
|
||||
/* Disable the msi hardware to avoid screaming interrupts
|
||||
* during boot. This is the power on reset default so
|
||||
* usually this should be a noop.
|
||||
*/
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
||||
if (pos)
|
||||
msi_set_enable(dev, pos, 0);
|
||||
msix_set_enable(dev, 0);
|
||||
dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
||||
if (dev->msi_cap)
|
||||
msi_set_enable(dev, 0);
|
||||
|
||||
dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
||||
if (dev->msix_cap)
|
||||
msix_set_enable(dev, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2003-2004 Intel
|
||||
* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
|
||||
*/
|
||||
|
||||
#ifndef MSI_H
|
||||
#define MSI_H
|
||||
|
||||
#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
|
||||
#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
|
||||
#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
|
||||
#define msi_data_reg(base, is64bit) \
|
||||
(base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32))
|
||||
#define msi_mask_reg(base, is64bit) \
|
||||
(base + ((is64bit == 1) ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32))
|
||||
#define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
|
||||
#define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
|
||||
|
||||
#define msix_table_offset_reg(base) (base + PCI_MSIX_TABLE)
|
||||
#define msix_pba_offset_reg(base) (base + PCI_MSIX_PBA)
|
||||
#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
|
||||
#define multi_msix_capable(control) msix_table_size((control))
|
||||
|
||||
#endif /* MSI_H */
|
||||
|
|
@ -1488,7 +1488,4 @@ struct megasas_mgmt_info {
|
|||
int max_index;
|
||||
};
|
||||
|
||||
#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
|
||||
#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
|
||||
|
||||
#endif /*LSI_MEGARAID_SAS_H */
|
||||
|
|
|
|||
|
|
@ -3984,12 +3984,12 @@ static int megasas_probe_one(struct pci_dev *pdev,
|
|||
if (reset_devices) {
|
||||
pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
|
||||
if (pos) {
|
||||
pci_read_config_word(pdev, msi_control_reg(pos),
|
||||
pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS,
|
||||
&control);
|
||||
if (control & PCI_MSIX_FLAGS_ENABLE) {
|
||||
dev_info(&pdev->dev, "resetting MSI-X\n");
|
||||
pci_write_config_word(pdev,
|
||||
msi_control_reg(pos),
|
||||
pos + PCI_MSIX_FLAGS,
|
||||
control &
|
||||
~PCI_MSIX_FLAGS_ENABLE);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
|
|||
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
||||
}
|
||||
|
||||
msix_pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
|
||||
msix_pos = pdev->msix_cap;
|
||||
if (msix_pos) {
|
||||
u16 flags;
|
||||
u32 table;
|
||||
|
|
@ -78,8 +78,8 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
|
|||
pci_read_config_word(pdev, msix_pos + PCI_MSIX_FLAGS, &flags);
|
||||
pci_read_config_dword(pdev, msix_pos + PCI_MSIX_TABLE, &table);
|
||||
|
||||
vdev->msix_bar = table & PCI_MSIX_FLAGS_BIRMASK;
|
||||
vdev->msix_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
|
||||
vdev->msix_bar = table & PCI_MSIX_TABLE_BIR;
|
||||
vdev->msix_offset = table & PCI_MSIX_TABLE_OFFSET;
|
||||
vdev->msix_size = ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) * 16;
|
||||
} else
|
||||
vdev->msix_bar = 0xFF;
|
||||
|
|
@ -183,7 +183,7 @@ static int vfio_pci_get_irq_count(struct vfio_pci_device *vdev, int irq_type)
|
|||
u8 pos;
|
||||
u16 flags;
|
||||
|
||||
pos = pci_find_capability(vdev->pdev, PCI_CAP_ID_MSI);
|
||||
pos = vdev->pdev->msi_cap;
|
||||
if (pos) {
|
||||
pci_read_config_word(vdev->pdev,
|
||||
pos + PCI_MSI_FLAGS, &flags);
|
||||
|
|
@ -194,7 +194,7 @@ static int vfio_pci_get_irq_count(struct vfio_pci_device *vdev, int irq_type)
|
|||
u8 pos;
|
||||
u16 flags;
|
||||
|
||||
pos = pci_find_capability(vdev->pdev, PCI_CAP_ID_MSIX);
|
||||
pos = vdev->pdev->msix_cap;
|
||||
if (pos) {
|
||||
pci_read_config_word(vdev->pdev,
|
||||
pos + PCI_MSIX_FLAGS, &flags);
|
||||
|
|
|
|||
|
|
@ -13,14 +13,14 @@ struct msi_msg {
|
|||
/* Helper functions */
|
||||
struct irq_data;
|
||||
struct msi_desc;
|
||||
extern void mask_msi_irq(struct irq_data *data);
|
||||
extern void unmask_msi_irq(struct irq_data *data);
|
||||
extern void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
||||
extern void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
||||
extern void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
||||
extern void read_msi_msg(unsigned int irq, struct msi_msg *msg);
|
||||
extern void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
|
||||
extern void write_msi_msg(unsigned int irq, struct msi_msg *msg);
|
||||
void mask_msi_irq(struct irq_data *data);
|
||||
void unmask_msi_irq(struct irq_data *data);
|
||||
void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
||||
void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
||||
void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
|
||||
void read_msi_msg(unsigned int irq, struct msi_msg *msg);
|
||||
void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
|
||||
void write_msi_msg(unsigned int irq, struct msi_msg *msg);
|
||||
|
||||
struct msi_desc {
|
||||
struct {
|
||||
|
|
@ -54,9 +54,8 @@ struct msi_desc {
|
|||
*/
|
||||
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
|
||||
void arch_teardown_msi_irq(unsigned int irq);
|
||||
extern int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
|
||||
extern void arch_teardown_msi_irqs(struct pci_dev *dev);
|
||||
extern int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
|
||||
|
||||
int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
|
||||
void arch_teardown_msi_irqs(struct pci_dev *dev);
|
||||
int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
|
||||
|
||||
#endif /* LINUX_MSI_H */
|
||||
|
|
|
|||
|
|
@ -247,6 +247,8 @@ struct pci_dev {
|
|||
u8 revision; /* PCI revision, low byte of class word */
|
||||
u8 hdr_type; /* PCI header type (`multi' flag masked out) */
|
||||
u8 pcie_cap; /* PCI-E capability offset */
|
||||
u8 msi_cap; /* MSI capability offset */
|
||||
u8 msix_cap; /* MSI-X capability offset */
|
||||
u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
|
||||
u8 rom_base_reg; /* which config register controls the ROM */
|
||||
u8 pin; /* which interrupt pin this device uses */
|
||||
|
|
@ -264,8 +266,7 @@ struct pci_dev {
|
|||
pci_power_t current_state; /* Current operating state. In ACPI-speak,
|
||||
this is D0-D3, D0 being fully functional,
|
||||
and D3 being off. */
|
||||
int pm_cap; /* PM capability offset in the
|
||||
configuration space */
|
||||
u8 pm_cap; /* PM capability offset */
|
||||
unsigned int pme_support:5; /* Bitmask of states from which PME#
|
||||
can be generated */
|
||||
unsigned int pme_interrupt:1;
|
||||
|
|
|
|||
|
|
@ -292,12 +292,12 @@
|
|||
|
||||
/* Message Signalled Interrupts registers */
|
||||
|
||||
#define PCI_MSI_FLAGS 2 /* Various flags */
|
||||
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
|
||||
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
|
||||
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
|
||||
#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
|
||||
#define PCI_MSI_FLAGS 2 /* Message Control */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
|
||||
#define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */
|
||||
#define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */
|
||||
#define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
|
||||
#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
|
||||
#define PCI_MSI_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
|
||||
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
|
||||
|
|
@ -309,13 +309,17 @@
|
|||
#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
|
||||
|
||||
/* MSI-X registers */
|
||||
#define PCI_MSIX_FLAGS 2
|
||||
#define PCI_MSIX_FLAGS_QSIZE 0x7FF
|
||||
#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
|
||||
#define PCI_MSIX_FLAGS_MASKALL (1 << 14)
|
||||
#define PCI_MSIX_TABLE 4
|
||||
#define PCI_MSIX_PBA 8
|
||||
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
|
||||
#define PCI_MSIX_FLAGS 2 /* Message Control */
|
||||
#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
|
||||
#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
|
||||
#define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
|
||||
#define PCI_MSIX_TABLE 4 /* Table offset */
|
||||
#define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */
|
||||
#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */
|
||||
#define PCI_MSIX_PBA 8 /* Pending Bit Array offset */
|
||||
#define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */
|
||||
#define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */
|
||||
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) /* deprecated */
|
||||
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
|
||||
|
||||
/* MSI-X entry's format */
|
||||
|
|
|
|||
Loading…
Reference in a new issue