x86, ioapic: Optimize pin_2_irq
Now that all ioapics have valid gsi_base values use this to accellerate pin_2_irq. In the case of acpi this also ensures that pin_2_irq will compute the same irq value for an ioapic pin as acpi will. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> LKML-Reference: <1269936436-7039-12-git-send-email-ebiederm@xmission.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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1 changed files with 4 additions and 9 deletions
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@ -1019,7 +1019,7 @@ static inline int irq_trigger(int idx)
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int (*ioapic_renumber_irq)(int ioapic, int irq);
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static int pin_2_irq(int idx, int apic, int pin)
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{
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int irq, i;
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int irq;
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int bus = mp_irqs[idx].srcbus;
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/*
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@ -1031,18 +1031,13 @@ static int pin_2_irq(int idx, int apic, int pin)
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if (test_bit(bus, mp_bus_not_pci)) {
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irq = mp_irqs[idx].srcbusirq;
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} else {
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/*
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* PCI IRQs are mapped in order
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*/
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i = irq = 0;
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while (i < apic)
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irq += nr_ioapic_registers[i++];
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irq += pin;
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u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
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/*
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* For MPS mode, so far only needed by ES7000 platform
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*/
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if (ioapic_renumber_irq)
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irq = ioapic_renumber_irq(apic, irq);
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gsi = ioapic_renumber_irq(apic, gsi);
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irq = gsi;
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}
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#ifdef CONFIG_X86_32
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