Merge branch 'bcm7xxx-next'
Florian Fainelli says: ==================== net: phy: bcm7xxx: workaround updates This patch series contains some updates to the Broadcom BCM7xxx internal PHY driver, including: - removing an annonying print that would appear during interface up/down and suspend/resume cycles - drop a workaround sequence for a non-production PHY revision - add new workarounds for the latest and greatest PHY devices found out there ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
d3f15dbd42
1 changed files with 90 additions and 44 deletions
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@ -39,45 +39,15 @@
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#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
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#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
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#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
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#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
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#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
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#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
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#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
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#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
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#define CORE_EXPB0 0xb0
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static int bcm7445_config_init(struct phy_device *phydev)
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{
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int ret;
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const struct bcm7445_regs {
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int reg;
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u16 value;
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} bcm7445_regs_cfg[] = {
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/* increases ADC latency by 24ns */
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{ MII_BCM54XX_EXP_SEL, 0x0038 },
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{ MII_BCM54XX_EXP_DATA, 0xAB95 },
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/* increases internal 1V LDO voltage by 5% */
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{ MII_BCM54XX_EXP_SEL, 0x2038 },
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{ MII_BCM54XX_EXP_DATA, 0xBB22 },
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/* reduce RX low pass filter corner frequency */
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{ MII_BCM54XX_EXP_SEL, 0x6038 },
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{ MII_BCM54XX_EXP_DATA, 0xFFC5 },
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/* reduce RX high pass filter corner frequency */
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{ MII_BCM54XX_EXP_SEL, 0x003a },
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{ MII_BCM54XX_EXP_DATA, 0x2002 },
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};
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {
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ret = phy_write(phydev,
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bcm7445_regs_cfg[i].reg,
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bcm7445_regs_cfg[i].value);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void phy_write_exp(struct phy_device *phydev,
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u16 reg, u16 value)
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{
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@ -102,7 +72,16 @@ static void phy_write_misc(struct phy_device *phydev,
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phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
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}
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static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
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static void r_rc_cal_reset(struct phy_device *phydev)
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{
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/* Reset R_CAL/RC_CAL Engine */
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phy_write_exp(phydev, 0x00b0, 0x0010);
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/* Disable Reset R_AL/RC_CAL Engine */
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phy_write_exp(phydev, 0x00b0, 0x0000);
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}
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static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
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{
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/* Increase VCO range to prevent unlocking problem of PLL at low
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* temp
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@ -123,11 +102,7 @@ static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
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/* Switch to CORE_BASE1E */
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phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
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/* Reset R_CAL/RC_CAL Engine */
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phy_write_exp(phydev, CORE_EXPB0, 0x0010);
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/* Disable Reset R_CAL/RC_CAL Engine */
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phy_write_exp(phydev, CORE_EXPB0, 0x0000);
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r_rc_cal_reset(phydev);
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/* write AFE_RXCONFIG_0 */
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phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
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@ -147,6 +122,71 @@ static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
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return 0;
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}
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static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
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{
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/* AFE_RXCONFIG_0 */
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phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
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/* AFE_RXCONFIG_1 */
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phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
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/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
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phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
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/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
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phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
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/* AFE_TX_CONFIG, set 1000BT Cfeed=110 for all ports */
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phy_write_misc(phydev, AFE_TX_CONFIG, 0x0061);
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/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
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phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
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/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
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phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
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/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
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* offset for HT=0 code
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*/
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phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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phy_write_misc(phydev, DSP_TAP10, 0x011b);
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/* Reset R_CAL/RC_CAL engine */
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r_rc_cal_reset(phydev);
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return 0;
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}
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static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
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{
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/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
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phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
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/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
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phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
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/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
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* offset for HT=0 code
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*/
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phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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phy_write_misc(phydev, DSP_TAP10, 0x011b);
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/* Reset R_CAL/RC_CAL engine */
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r_rc_cal_reset(phydev);
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return 0;
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}
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static int bcm7xxx_apd_enable(struct phy_device *phydev)
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{
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int val;
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@ -200,15 +240,21 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
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u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
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int ret = 0;
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dev_info(&phydev->dev, "PHY revision: 0x%02x, patch: %d\n", rev, patch);
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pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
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dev_name(&phydev->dev), phydev->drv->name, rev, patch);
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switch (rev) {
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case 0xa0:
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case 0xb0:
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ret = bcm7445_config_init(phydev);
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ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
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break;
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case 0xd0:
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ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
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break;
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case 0xe0:
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case 0xf0:
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ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
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break;
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default:
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ret = bcm7xxx_28nm_afe_config_init(phydev);
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break;
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}
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@ -336,7 +382,7 @@ static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
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.features = PHY_GBIT_FEATURES | \
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SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
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.flags = PHY_IS_INTERNAL, \
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.config_init = bcm7xxx_28nm_afe_config_init, \
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.config_init = bcm7xxx_28nm_config_init, \
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.config_aneg = genphy_config_aneg, \
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.read_status = genphy_read_status, \
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.resume = bcm7xxx_28nm_resume, \
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