sparc: unify kernel/cpu
o use cpu_32.c as base o move all sparc64 definitions to the common cpu.c o use ifdef for the parts that differs and use cpu_32 as base o spitfire.h required a CONFIG_SPARC64 guard to fix build on 32 bit Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sam Ravnborg
David S. Miller
parent
2bf05fa03e
commit
d34dd82905
4 changed files with 95 additions and 169 deletions
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@ -6,6 +6,8 @@
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#ifndef _SPARC64_SPITFIRE_H
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#define _SPARC64_SPITFIRE_H
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#ifdef CONFIG_SPARC64
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#include <asm/asi.h>
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/* The following register addresses are accessible via ASI_DMMU
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@ -338,5 +340,5 @@ static inline void cheetah_put_itlb_data(int entry, unsigned long data)
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* CONFIG_SPARC64 */
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#endif /* !(_SPARC64_SPITFIRE_H) */
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@ -27,7 +27,7 @@ obj-y += sys_sparc_$(BITS).o
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obj-$(CONFIG_SPARC32) += systbls_32.o
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obj-y += time_$(BITS).o
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obj-$(CONFIG_SPARC32) += windows.o
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obj-y += cpu_$(BITS).o
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obj-y += cpu.o
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obj-$(CONFIG_SPARC32) += devices.o
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obj-$(CONFIG_SPARC32) += tadpole.o
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obj-$(CONFIG_SPARC32) += tick14.o
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@ -8,6 +8,8 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <asm/spitfire.h>
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#include <asm/oplib.h>
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#include <asm/page.h>
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#include <asm/head.h>
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@ -176,6 +178,52 @@ static const struct manufacturer_info __initconst manufacturer_info[] = {
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FPU(3, "Fujitsu or Weitek on-chip FPU"),
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FPU(-1, NULL)
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}
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},{
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0x17,
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.cpu_info = {
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CPU(0x10, "TI UltraSparc I (SpitFire)"),
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CPU(0x11, "TI UltraSparc II (BlackBird)"),
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CPU(0x12, "TI UltraSparc IIi (Sabre)"),
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CPU(0x13, "TI UltraSparc IIe (Hummingbird)"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0x10, "UltraSparc I integrated FPU"),
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FPU(0x11, "UltraSparc II integrated FPU"),
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FPU(0x12, "UltraSparc IIi integrated FPU"),
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FPU(0x13, "UltraSparc IIe integrated FPU"),
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FPU(-1, NULL)
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}
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},{
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0x22,
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.cpu_info = {
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CPU(0x10, "TI UltraSparc I (SpitFire)"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0x10, "UltraSparc I integrated FPU"),
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FPU(-1, NULL)
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}
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},{
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0x3e,
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.cpu_info = {
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CPU(0x14, "TI UltraSparc III (Cheetah)"),
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CPU(0x15, "TI UltraSparc III+ (Cheetah+)"),
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CPU(0x16, "TI UltraSparc IIIi (Jalapeno)"),
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CPU(0x18, "TI UltraSparc IV (Jaguar)"),
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CPU(0x19, "TI UltraSparc IV+ (Panther)"),
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CPU(0x22, "TI UltraSparc IIIi+ (Serrano)"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0x14, "UltraSparc III integrated FPU"),
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FPU(0x15, "UltraSparc III+ integrated FPU"),
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FPU(0x16, "UltraSparc IIIi integrated FPU"),
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FPU(0x18, "UltraSparc IV integrated FPU"),
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FPU(0x19, "UltraSparc IV+ integrated FPU"),
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FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
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FPU(-1, NULL)
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}
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}};
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/* In order to get the fpu type correct, you need to take the IDPROM's
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@ -230,6 +278,7 @@ static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers)
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}
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}
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#ifdef CONFIG_SPARC32
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void __cpuinit cpu_probe(void)
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{
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int psr_impl, psr_vers, fpu_vers;
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@ -245,3 +294,45 @@ void __cpuinit cpu_probe(void)
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set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
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}
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#else
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static void __init sun4v_cpu_probe(void)
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{
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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sparc_cpu_type = "UltraSparc T1 (Niagara)";
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sparc_fpu_type = "UltraSparc T1 integrated FPU";
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break;
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case SUN4V_CHIP_NIAGARA2:
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sparc_cpu_type = "UltraSparc T2 (Niagara2)";
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sparc_fpu_type = "UltraSparc T2 integrated FPU";
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break;
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default:
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printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
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prom_cpu_compatible);
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sparc_cpu_type = "Unknown SUN4V CPU";
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sparc_fpu_type = "Unknown SUN4V FPU";
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break;
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}
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}
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static int __init cpu_type_probe(void)
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{
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if (tlb_type == hypervisor) {
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sun4v_cpu_probe();
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} else {
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unsigned long ver;
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int manuf, impl;
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__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
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manuf = ((ver >> 48) & 0xffff);
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impl = ((ver >> 32) & 0xffff);
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set_cpu_and_fpu(manuf, impl, impl);
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}
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return 0;
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}
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arch_initcall(cpu_type_probe);
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#endif
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@ -1,167 +0,0 @@
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/* cpu.c: Dinky routines to look for the kind of Sparc cpu
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* we are on.
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*
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* Copyright (C) 1996, 2007, 2008 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/asi.h>
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#include <asm/system.h>
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#include <asm/fpumacro.h>
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#include <asm/cpudata.h>
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#include <asm/spitfire.h>
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#include <asm/oplib.h>
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#include "entry.h"
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#include "kernel.h"
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DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
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struct cpu_chip_info {
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unsigned short manuf;
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unsigned short impl;
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const char *cpu_name;
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const char *fp_name;
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};
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static const struct cpu_chip_info cpu_chips[] = {
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{
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.manuf = 0x17,
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.impl = 0x10,
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.cpu_name = "TI UltraSparc I (SpitFire)",
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.fp_name = "UltraSparc I integrated FPU",
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},
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{
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.manuf = 0x22,
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.impl = 0x10,
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.cpu_name = "TI UltraSparc I (SpitFire)",
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.fp_name = "UltraSparc I integrated FPU",
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},
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{
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.manuf = 0x17,
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.impl = 0x11,
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.cpu_name = "TI UltraSparc II (BlackBird)",
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.fp_name = "UltraSparc II integrated FPU",
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},
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{
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.manuf = 0x17,
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.impl = 0x12,
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.cpu_name = "TI UltraSparc IIi (Sabre)",
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.fp_name = "UltraSparc IIi integrated FPU",
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},
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{
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.manuf = 0x17,
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.impl = 0x13,
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.cpu_name = "TI UltraSparc IIe (Hummingbird)",
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.fp_name = "UltraSparc IIe integrated FPU",
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},
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{
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.manuf = 0x3e,
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.impl = 0x14,
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.cpu_name = "TI UltraSparc III (Cheetah)",
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.fp_name = "UltraSparc III integrated FPU",
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},
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{
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.manuf = 0x3e,
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.impl = 0x15,
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.cpu_name = "TI UltraSparc III+ (Cheetah+)",
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.fp_name = "UltraSparc III+ integrated FPU",
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},
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{
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.manuf = 0x3e,
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.impl = 0x16,
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.cpu_name = "TI UltraSparc IIIi (Jalapeno)",
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.fp_name = "UltraSparc IIIi integrated FPU",
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},
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{
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.manuf = 0x3e,
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.impl = 0x18,
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.cpu_name = "TI UltraSparc IV (Jaguar)",
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.fp_name = "UltraSparc IV integrated FPU",
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},
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{
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.manuf = 0x3e,
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.impl = 0x19,
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.cpu_name = "TI UltraSparc IV+ (Panther)",
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.fp_name = "UltraSparc IV+ integrated FPU",
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},
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{
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.manuf = 0x3e,
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.impl = 0x22,
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.cpu_name = "TI UltraSparc IIIi+ (Serrano)",
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.fp_name = "UltraSparc IIIi+ integrated FPU",
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},
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};
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#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips)
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const char *sparc_cpu_type;
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const char *sparc_fpu_type;
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static void __init sun4v_cpu_probe(void)
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{
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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sparc_cpu_type = "UltraSparc T1 (Niagara)";
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sparc_fpu_type = "UltraSparc T1 integrated FPU";
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break;
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case SUN4V_CHIP_NIAGARA2:
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sparc_cpu_type = "UltraSparc T2 (Niagara2)";
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sparc_fpu_type = "UltraSparc T2 integrated FPU";
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break;
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default:
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printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
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prom_cpu_compatible);
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sparc_cpu_type = "Unknown SUN4V CPU";
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sparc_fpu_type = "Unknown SUN4V FPU";
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break;
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}
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}
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static const struct cpu_chip_info * __init find_cpu_chip(unsigned short manuf,
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unsigned short impl)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cpu_chips); i++) {
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const struct cpu_chip_info *p = &cpu_chips[i];
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if (p->manuf == manuf && p->impl == impl)
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return p;
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}
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return NULL;
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}
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static int __init cpu_type_probe(void)
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{
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if (tlb_type == hypervisor) {
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sun4v_cpu_probe();
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} else {
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unsigned long ver, manuf, impl;
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const struct cpu_chip_info *p;
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__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
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manuf = ((ver >> 48) & 0xffff);
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impl = ((ver >> 32) & 0xffff);
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p = find_cpu_chip(manuf, impl);
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if (p) {
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sparc_cpu_type = p->cpu_name;
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sparc_fpu_type = p->fp_name;
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} else {
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printk(KERN_ERR "CPU: Unknown chip, manuf[%lx] impl[%lx]\n",
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manuf, impl);
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sparc_cpu_type = "Unknown CPU";
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sparc_fpu_type = "Unknown FPU";
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}
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}
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return 0;
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}
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arch_initcall(cpu_type_probe);
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