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MIPS: FRE: Use set/clear_c0_config5 instead of open coded sequences.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2014-12-17 11:46:40 +01:00
parent b0c34f6155
commit d33e6fe3ca
1 changed files with 3 additions and 5 deletions
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8
arch/mips/include/asm/fpu.h
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@ -64,7 +64,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
return SIGFPE; return SIGFPE;
/* set FRE */ /* set FRE */
write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE); set_c0_config5(MIPS_CONF5_FRE);
goto fr_common; goto fr_common;
case FPU_64BIT: case FPU_64BIT:
@ -76,7 +76,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
case FPU_32BIT: case FPU_32BIT:
if (cpu_has_fre) { if (cpu_has_fre) {
/* clear FRE */ /* clear FRE */
write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE); clear_c0_config5(MIPS_CONF5_FRE);
} }
fr_common: fr_common:
/* set CU1 & change FR appropriately */ /* set CU1 & change FR appropriately */
@ -196,15 +196,13 @@ static inline int init_fpu(void)
return 0; return 0;
} }
config5 = read_c0_config5();
/* /*
* Ensure FRE is clear whilst running _init_fpu, since * Ensure FRE is clear whilst running _init_fpu, since
* single precision FP instructions are used. If FRE * single precision FP instructions are used. If FRE
* was set then we'll just end up initialising all 32 * was set then we'll just end up initialising all 32
* 64b registers. * 64b registers.
*/ */
write_c0_config5(config5 & ~MIPS_CONF5_FRE); config5 = clear_c0_config5(MIPS_CONF5_FRE);
enable_fpu_hazard(); enable_fpu_hazard();
_init_fpu(); _init_fpu();