The second half of the clock framework pull requeust for 3.14 is
dominated by platform support for Qualcomm's MSM SoCs, DT binding updates for TI's OMAP-ish processors and additional support for Samsung chips. Additionally there are other smaller clock driver changes and several last minute fixes. This pull request also includes the HiSilicon support that depends on the already-merged arm-soc pull request. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS5tJoAAoJEDqPOy9afJhJg2YP/1hZueLNwJwtasgSlrjPAKai +VDc1Sn0lB7p0D0r0cyd6kUPlAMBwZOMJ3wLvbI+z/yItCfXNxIDpaQszMoHmBox Dgj3BmnM0GJgtE124qKynFdDqJ09aHcJZ9iEXQAxwo3mWvmHW8U2P2nDQJbxz3Qm i/F7KzpXk6seUV7f14doPD0PY5CVRm0p5dfMXLsroLvWjrvTqA4imbAuOeHI1UuG siboNe94nLcAj8iBQanugpKjlKT4+jjeTCfCuJ2OeS5o2Lz3KO2BYr6HekbsNZiz atydhPO840fCNxR/SSKAgIzr9FjQ5Q2fJvF7m+6XyFND9gZ/yjN14LdlTU1SX3kD 1yB8OSqKjjLOBU5P1UwvD8NL8kldwoynYT7T4JqYIZQHZyjNGToBZ1SzUZ/yVsnE sMbfVC8X5RMEJzGIWNbm6kz+37CRQWNn4aPghGjkyLDGpyVf7dn+jlGBgGiahb8g io1Ir35/FykHAVx16veYD09sB+VYAeD23P/nuP7MbdCzYLmu4ibAiJyBiPQvcxmq YZWENS2j4NvG2XdHW07SpWC0U0mr5MLOkFjVkcW8h+aaT3FJUwaP0wjRyWoaF3Dt sEZ10OJLuXK5x3oiLFhuqHwGSGy+XoIq3FL00jjkib6uKcv2hNYQ+ZpPzG/CDbNx ndMT57cycXMYrOp8jklw =WRJD -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux Pull more clock framework changes from Mike Turquette: "The second half of the clock framework pull requeust for 3.14 is dominated by platform support for Qualcomm's MSM SoCs, DT binding updates for TI's OMAP-ish processors and additional support for Samsung chips. Additionally there are other smaller clock driver changes and several last minute fixes. This pull request also includes the HiSilicon support that depends on the already-merged arm-soc pull request" [ Fix up stupid compile error in the source tree with evil merge - Grumpy Linus ] * tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux: (49 commits) clk: sort Makefile clk: sunxi: fix overflow when setting up divided factors clk: Export more clk-provider functions dt-bindings: qcom: Fix warning with duplicate dt define clk: si5351: remove variant from platform_data clk: samsung: Remove unneeded semicolon clk: qcom: Fix modular build ARM: OMAP3: use DT clock init if DT data is available ARM: AM33xx: remove old clock data and link in new clock init code ARM: AM43xx: Enable clock init ARM: OMAP: DRA7: Enable clock init ARM: OMAP4: remove old clock data and link in new clock init code ARM: OMAP2+: io: use new clock init API ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT ARM: OMAP3: hwmod: initialize clkdm from clkdm_name ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm ARM: OMAP2+: clock: use driver API instead of direct memory read/write ARM: OMAP2+: clock: add support for indexed memmaps ARM: dts: am43xx clock data ARM: dts: AM35xx: use DT clock data ...
This commit is contained in:
Linus Torvalds
commit
d30492adea
83 changed files with 14876 additions and 3139 deletions
31
Documentation/devicetree/bindings/clock/ti/apll.txt
Normal file
31
Documentation/devicetree/bindings/clock/ti/apll.txt
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
Binding for Texas Instruments APLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped APLL with usually two selectable input clocks
|
||||
(reference clock and bypass clock), with analog phase locked
|
||||
loop logic for multiplying the input clock to a desired output
|
||||
clock. This clock also typically supports different operation
|
||||
modes (locked, low power stop etc.) APLL mostly behaves like
|
||||
a subtype of a DPLL [2], although a simplified one at that.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dra7-apll-clock"
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
|
||||
- reg : address and length of the register set for controlling the APLL.
|
||||
It contains the information of registers in the following order:
|
||||
"control" - contains the control register base address
|
||||
"idlest" - contains the idlest register base address
|
||||
|
||||
Examples:
|
||||
apll_pcie_ck: apll_pcie_ck@4a008200 {
|
||||
#clock-cells = <0>;
|
||||
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
|
||||
reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
|
||||
compatible = "ti,dra7-apll-clock";
|
||||
};
|
||||
39
Documentation/devicetree/bindings/clock/ti/autoidle.txt
Normal file
39
Documentation/devicetree/bindings/clock/ti/autoidle.txt
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
Binding for Texas Instruments autoidle clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a register mapped
|
||||
clock which can be put to idle automatically by hardware based on the usage
|
||||
and a configuration bit setting. Autoidle clock is never an individual
|
||||
clock, it is always a derivative of some basic clock like a gate, divider,
|
||||
or fixed-factor.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- reg : offset for the register controlling the autoidle
|
||||
- ti,autoidle-shift : bit shift of the autoidle enable bit
|
||||
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
|
||||
|
||||
Examples:
|
||||
dpll_core_m4_ck: dpll_core_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d38>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&dpll_usb_ck>;
|
||||
ti,clock-div = <1>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x01b4>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
24
Documentation/devicetree/bindings/clock/ti/clockdomain.txt
Normal file
24
Documentation/devicetree/bindings/clock/ti/clockdomain.txt
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
Binding for Texas Instruments clockdomain.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1] in consumer role.
|
||||
Every clock on TI SoC belongs to one clockdomain, but software
|
||||
only needs this information for specific clocks which require
|
||||
their parent clockdomain to be controlled when the clock is
|
||||
enabled/disabled. This binding doesn't define a new clock
|
||||
binding type, it is used to group existing clock nodes under
|
||||
hardware hierarchy.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,clockdomain"
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of clocks within this domain
|
||||
|
||||
Examples:
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
|
||||
};
|
||||
54
Documentation/devicetree/bindings/clock/ti/composite.txt
Normal file
54
Documentation/devicetree/bindings/clock/ti/composite.txt
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
Binding for TI composite clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped composite clock with multiple different sub-types;
|
||||
|
||||
a multiplexer clock with multiple input clock signals or parents, one
|
||||
of which can be selected as output, this behaves exactly as [2]
|
||||
|
||||
an adjustable clock rate divider, this behaves exactly as [3]
|
||||
|
||||
a gating function which can be used to enable and disable the output
|
||||
clock, this behaves exactly as [4]
|
||||
|
||||
The binding must provide a list of the component clocks that shall be
|
||||
merged to this clock. The component clocks shall be of one of the
|
||||
"ti,*composite*-clock" types.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/mux.txt
|
||||
[3] Documentation/devicetree/bindings/clock/ti/divider.txt
|
||||
[4] Documentation/devicetree/bindings/clock/ti/gate.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be: "ti,composite-clock"
|
||||
- clocks : link phandles of component clocks
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
Examples:
|
||||
|
||||
usb_l4_gate_ick: usb_l4_gate_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0a10>;
|
||||
};
|
||||
|
||||
usb_l4_div_ick: usb_l4_div_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <1>;
|
||||
reg = <0x0a40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
usb_l4_ick: usb_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
|
||||
};
|
||||
114
Documentation/devicetree/bindings/clock/ti/divider.txt
Normal file
114
Documentation/devicetree/bindings/clock/ti/divider.txt
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
Binding for TI divider clock
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped adjustable clock rate divider that does not gate and has
|
||||
only one input clock or parent. By default the value programmed into
|
||||
the register is one less than the actual divisor value. E.g:
|
||||
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 3
|
||||
|
||||
This assumption may be modified by the following optional properties:
|
||||
|
||||
ti,index-starts-at-one - valid divisor values start at 1, not the default
|
||||
of 0. E.g:
|
||||
register value actual divisor value
|
||||
1 1
|
||||
2 2
|
||||
3 3
|
||||
|
||||
ti,index-power-of-two - valid divisor values are powers of two. E.g:
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 4
|
||||
|
||||
Additionally an array of valid dividers may be supplied like so:
|
||||
|
||||
ti,dividers = <4>, <8>, <0>, <16>;
|
||||
|
||||
Which will map the resulting values to a divisor table by their index:
|
||||
register value actual divisor value
|
||||
0 4
|
||||
1 8
|
||||
2 <invalid divisor, skipped>
|
||||
3 16
|
||||
|
||||
Any zero value in this array means the corresponding bit-value is invalid
|
||||
and must not be used.
|
||||
|
||||
The binding must also provide the register to control the divider and
|
||||
unless the divider array is provided, min and max dividers. Optionally
|
||||
the number of bits to shift that mask, if necessary. If the shift value
|
||||
is missing it is the same as supplying a zero shift.
|
||||
|
||||
This binding can also optionally provide support to the hardware autoidle
|
||||
feature, see [2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : offset for register controlling adjustable divider
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,dividers : array of integers defining divisors
|
||||
- ti,bit-shift : number of bits to shift the divider value, defaults to 0
|
||||
- ti,min-div : min divisor for dividing the input clock rate, only
|
||||
needed if the first divisor is offset from the default value (1)
|
||||
- ti,max-div : max divisor for dividing the input clock rate, only needed
|
||||
if ti,dividers is not defined.
|
||||
- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
|
||||
only valid if ti,dividers is not defined.
|
||||
- ti,index-power-of-two : valid divisor programming must be a power of two,
|
||||
only valid if ti,dividers is not defined.
|
||||
- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
|
||||
see [2]
|
||||
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
|
||||
see [2]
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent
|
||||
|
||||
Examples:
|
||||
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_usb_ck>;
|
||||
ti,max-div = <127>;
|
||||
reg = <0x190>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
aess_fclk: aess_fclk@4a004528 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&abe_clk>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x528>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0134>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
75
Documentation/devicetree/bindings/clock/ti/dpll.txt
Normal file
75
Documentation/devicetree/bindings/clock/ti/dpll.txt
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
Binding for Texas Instruments DPLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped DPLL with usually two selectable input clocks
|
||||
(reference clock and bypass clock), with digital phase locked
|
||||
loop logic for multiplying the input clock to a desired output
|
||||
clock. This clock also typically supports different operation
|
||||
modes (locked, low power stop etc.) This binding has several
|
||||
sub-types, which effectively result in slightly different setup
|
||||
for the actual DPLL clock.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
"ti,omap3-dpll-clock",
|
||||
"ti,omap3-dpll-core-clock",
|
||||
"ti,omap3-dpll-per-clock",
|
||||
"ti,omap3-dpll-per-j-type-clock",
|
||||
"ti,omap4-dpll-clock",
|
||||
"ti,omap4-dpll-x2-clock",
|
||||
"ti,omap4-dpll-core-clock",
|
||||
"ti,omap4-dpll-m4xen-clock",
|
||||
"ti,omap4-dpll-j-type-clock",
|
||||
"ti,am3-dpll-no-gate-clock",
|
||||
"ti,am3-dpll-j-type-clock",
|
||||
"ti,am3-dpll-no-gate-j-type-clock",
|
||||
"ti,am3-dpll-clock",
|
||||
"ti,am3-dpll-core-clock",
|
||||
"ti,am3-dpll-x2-clock",
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks, first entry lists reference clock
|
||||
and second entry bypass clock
|
||||
- reg : offsets for the register set for controlling the DPLL.
|
||||
Registers are listed in following order:
|
||||
"control" - contains the control register base address
|
||||
"idlest" - contains the idle status register base address
|
||||
"mult-div1" - contains the multiplier / divider register base address
|
||||
"autoidle" - contains the autoidle register base address (optional)
|
||||
ti,am3-* dpll types do not have autoidle register
|
||||
|
||||
Optional properties:
|
||||
- DPLL mode setting - defining any one or more of the following overrides
|
||||
default setting.
|
||||
- ti,low-power-stop : DPLL supports low power stop mode, gating output
|
||||
- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
|
||||
- ti,lock : DPLL locks in programmed rate
|
||||
|
||||
Examples:
|
||||
dpll_core_ck: dpll_core_ck@44e00490 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-core-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x490>, <0x45c>, <0x488>, <0x468>;
|
||||
};
|
||||
|
||||
dpll2_ck: dpll2_ck@48004004 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-clock";
|
||||
clocks = <&sys_ck>, <&dpll2_fck>;
|
||||
ti,low-power-stop;
|
||||
ti,low-power-bypass;
|
||||
ti,lock;
|
||||
reg = <0x4>, <0x24>, <0x34>, <0x40>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck@44e00490 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-core-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x90>, <0x5c>, <0x68>;
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
Binding for TI fixed factor rate clock sources.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1], and also uses the autoidle
|
||||
support from TI autoidle clock [2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,fixed-factor-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- ti,clock-div: fixed divider.
|
||||
- ti,clock-mult: fixed multiplier.
|
||||
- clocks: parent clock.
|
||||
|
||||
Optional properties:
|
||||
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
|
||||
see [2]
|
||||
- reg: offset for the autoidle register of this clock, see [2]
|
||||
- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
|
||||
- ti,set-rate-parent: clk_set_rate is propagated to parent
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
ti,clock-div = <2>;
|
||||
ti,clock-mult = <1>;
|
||||
};
|
||||
|
||||
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&dpll_usb_ck>;
|
||||
ti,clock-div = <1>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x01b4>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
85
Documentation/devicetree/bindings/clock/ti/gate.txt
Normal file
85
Documentation/devicetree/bindings/clock/ti/gate.txt
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
Binding for Texas Instruments gate clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. This clock is
|
||||
quite much similar to the basic gate-clock [2], however,
|
||||
it supports a number of additional features. If no register
|
||||
is provided for this clock, the code assumes that a clockdomain
|
||||
will be controlled instead and the corresponding hw-ops for
|
||||
that is used.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gate-clock.txt
|
||||
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
"ti,gate-clock" - basic gate clock
|
||||
"ti,wait-gate-clock" - gate clock which waits until clock is active before
|
||||
returning from clk_enable()
|
||||
"ti,dss-gate-clock" - gate clock with DSS specific hardware handling
|
||||
"ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
|
||||
"ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
|
||||
clock directly from a clockdomain, see [3] how
|
||||
to map clockdomains properly
|
||||
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
|
||||
required for a hardware errata
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : offset for register controlling adjustable gate, not needed for
|
||||
ti,clkdm-gate-clock type
|
||||
|
||||
Optional properties:
|
||||
- ti,bit-shift : bit shift for programming the clock gate, invalid for
|
||||
ti,clkdm-gate-clock type
|
||||
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
|
||||
gates the clock and clearing the bit ungates the clock.
|
||||
|
||||
Examples:
|
||||
mmchs2_fck: mmchs2_fck@48004a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x48004a00 0x4>;
|
||||
ti,bit-shift = <25>;
|
||||
};
|
||||
|
||||
uart4_fck_am35xx: uart4_fck_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_48m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
reg = <0x48004e00 0x4>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
emac_ick: emac_ick@4800259c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x4800259c 0x4>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
emu_src_ck: emu_src_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,clkdm-gate-clock";
|
||||
clocks = <&emu_src_mux_ck>;
|
||||
};
|
||||
|
||||
dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
reg = <0x48004d00 0x4>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
54
Documentation/devicetree/bindings/clock/ti/interface.txt
Normal file
54
Documentation/devicetree/bindings/clock/ti/interface.txt
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
Binding for Texas Instruments interface clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. This clock is
|
||||
quite much similar to the basic gate-clock [2], however,
|
||||
it supports a number of additional features, including
|
||||
companion clock finding (match corresponding functional gate
|
||||
clock) and hardware autoidle enable / disable.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gate-clock.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
"ti,omap3-interface-clock" - basic OMAP3 interface clock
|
||||
"ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
|
||||
capability for waiting clock to be ready
|
||||
"ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
|
||||
handling
|
||||
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
|
||||
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
|
||||
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : base address for the control register
|
||||
|
||||
Optional properties:
|
||||
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
|
||||
|
||||
Examples:
|
||||
aes1_ick: aes1_ick@48004a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x48004a14 0x4>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
cam_ick: cam_ick@48004f10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x48004f10 0x4>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x48004a10 0x4>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
76
Documentation/devicetree/bindings/clock/ti/mux.txt
Normal file
76
Documentation/devicetree/bindings/clock/ti/mux.txt
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
Binding for TI mux clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped multiplexer with multiple input clock signals or
|
||||
parents, one of which can be selected as output. This clock does not
|
||||
gate or adjust the parent rate via a divider or multiplier.
|
||||
|
||||
By default the "clocks" property lists the parents in the same order
|
||||
as they are programmed into the regster. E.g:
|
||||
|
||||
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
|
||||
|
||||
results in programming the register as follows:
|
||||
|
||||
register value selected parent clock
|
||||
0 foo_clock
|
||||
1 bar_clock
|
||||
2 baz_clock
|
||||
|
||||
Some clock controller IPs do not allow a value of zero to be programmed
|
||||
into the register, instead indexing begins at 1. The optional property
|
||||
"index-starts-at-one" modified the scheme as follows:
|
||||
|
||||
register value selected clock parent
|
||||
1 foo_clock
|
||||
2 bar_clock
|
||||
3 baz_clock
|
||||
|
||||
The binding must provide the register to control the mux. Optionally
|
||||
the number of bits to shift the control field in the register can be
|
||||
supplied. If the shift value is missing it is the same as supplying
|
||||
a zero shift.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks
|
||||
- reg : register offset for register controlling adjustable mux
|
||||
|
||||
Optional properties:
|
||||
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
|
||||
0 if not present
|
||||
- ti,index-starts-at-one : valid input select programming starts at 1, not
|
||||
zero
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
|
||||
not supported by the composite-mux-clock subtype
|
||||
|
||||
Examples:
|
||||
|
||||
sys_clkin_ck: sys_clkin_ck@4a306110 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
|
||||
reg = <0x0110>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x0108>;
|
||||
};
|
||||
|
||||
mcbsp5_mux_fck: mcbsp5_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&core_96m_fck>, <&mcbsp_clks>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x02d8>;
|
||||
};
|
||||
664
arch/arm/boot/dts/am33xx-clocks.dtsi
Normal file
664
arch/arm/boot/dts/am33xx-clocks.dtsi
Normal file
|
|
@ -0,0 +1,664 @@
|
|||
/*
|
||||
* Device Tree Source for AM33xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
adc_tsc_fck: adc_tsc_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan0_fck: dcan0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan1_fck: dcan1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp0_fck: mcasp0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp1_fck: mcasp1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex0_fck: smartreflex0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex1_fck: smartreflex1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sha0_fck: sha0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes0_fck: aes0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
rng_fck: rng_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&ehrpwm0_gate_tbclk>;
|
||||
};
|
||||
|
||||
ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&ehrpwm1_gate_tbclk>;
|
||||
};
|
||||
|
||||
ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <2>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&ehrpwm2_gate_tbclk>;
|
||||
};
|
||||
};
|
||||
&prcm_clocks {
|
||||
clk_32768_ck: clk_32768_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_rc32k_ck: clk_rc32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
virt_19200000_ck: virt_19200000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
virt_24000000_ck: virt_24000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
virt_25000000_ck: virt_25000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
virt_26000000_ck: virt_26000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
tclkin_ck: tclkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-core-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0490>, <0x045c>, <0x0468>;
|
||||
};
|
||||
|
||||
dpll_core_x2_ck: dpll_core_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_core_ck>;
|
||||
};
|
||||
|
||||
dpll_core_m4_ck: dpll_core_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0480>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_m5_ck: dpll_core_m5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0484>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_m6_ck: dpll_core_m6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04d8>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_mpu_ck: dpll_mpu_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0488>, <0x0420>, <0x042c>;
|
||||
};
|
||||
|
||||
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a8>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0494>, <0x0434>, <0x0440>;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a0>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_ddr_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
dpll_disp_ck: dpll_disp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0498>, <0x0448>, <0x0454>;
|
||||
};
|
||||
|
||||
dpll_disp_m2_ck: dpll_disp_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_disp_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a4>;
|
||||
ti,index-starts-at-one;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-j-type-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x048c>, <0x0470>, <0x049c>;
|
||||
};
|
||||
|
||||
dpll_per_m2_ck: dpll_per_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04ac>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
cefuse_fck: cefuse_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0a20>;
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
clkdiv32k_ck: clkdiv32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_24mhz>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <732>;
|
||||
};
|
||||
|
||||
clkdiv32k_ick: clkdiv32k_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x014c>;
|
||||
};
|
||||
|
||||
l3_gclk: l3_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pruss_ocp_gclk: pruss_ocp_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x0530>;
|
||||
};
|
||||
|
||||
mmu_fck: mmu_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0914>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
|
||||
reg = <0x0528>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0508>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x050c>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0510>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0518>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x051c>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0504>;
|
||||
};
|
||||
|
||||
usbotg_fck: usbotg_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x047c>;
|
||||
};
|
||||
|
||||
dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
ieee5000_fck: ieee5000_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x00e4>;
|
||||
};
|
||||
|
||||
wdt1_fck: wdt1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0538>;
|
||||
};
|
||||
|
||||
l4_rtc_gclk: l4_rtc_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
l4hs_gclk: l4hs_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l3s_gclk: l3s_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4fw_gclk: l4fw_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4ls_gclk: l4ls_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sysclk_div_ck: sysclk_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
|
||||
reg = <0x0520>;
|
||||
};
|
||||
|
||||
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x053c>;
|
||||
};
|
||||
|
||||
gpio0_dbclk: gpio0_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&gpio0_dbclk_mux_ck>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x0408>;
|
||||
};
|
||||
|
||||
gpio1_dbclk: gpio1_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x00ac>;
|
||||
};
|
||||
|
||||
gpio2_dbclk: gpio2_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x00b0>;
|
||||
};
|
||||
|
||||
gpio3_dbclk: gpio3_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x00b4>;
|
||||
};
|
||||
|
||||
lcd_gclk: lcd_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
||||
reg = <0x0534>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
mmc_clk: mmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x052c>;
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: gfx_fck_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&gfx_fclk_clksel_ck>;
|
||||
reg = <0x052c>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
sysclkout_pre_ck: sysclkout_pre_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
|
||||
clkout2_div_ck: clkout2_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sysclkout_pre_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,max-div = <8>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
|
||||
dbg_sysclk_ck: dbg_sysclk_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
ti,bit-shift = <19>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
dbg_clka_ck: dbg_clka_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
ti,bit-shift = <30>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
|
||||
ti,bit-shift = <20>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
stm_clk_div_ck: stm_clk_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&stm_pmd_clock_mux_ck>;
|
||||
ti,bit-shift = <27>;
|
||||
ti,max-div = <64>;
|
||||
reg = <0x0414>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
trace_clk_div_ck: trace_clk_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&trace_pmd_clk_mux_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
ti,max-div = <64>;
|
||||
reg = <0x0414>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
clkout2_ck: clkout2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkout2_div_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
};
|
||||
|
||||
&prcm_clockdomains {
|
||||
clk_24mhz_clkdm: clk_24mhz_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
};
|
||||
};
|
||||
|
|
@ -102,6 +102,32 @@
|
|||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
prcm: prcm@44e00000 {
|
||||
compatible = "ti,am3-prcm";
|
||||
reg = <0x44e00000 0x4000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@44e10000 {
|
||||
compatible = "ti,am3-scrm";
|
||||
reg = <0x44e10000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@48200000 {
|
||||
compatible = "ti,omap2-intc";
|
||||
interrupt-controller;
|
||||
|
|
@ -794,3 +820,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "am33xx-clocks.dtsi"
|
||||
|
|
|
|||
|
|
@ -61,3 +61,6 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "am35xx-clocks.dtsi"
|
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
|
||||
|
|
|
|||
128
arch/arm/boot/dts/am35xx-clocks.dtsi
Normal file
128
arch/arm/boot/dts/am35xx-clocks.dtsi
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP3 clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
emac_ick: emac_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
emac_fck: emac_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&rmii_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
|
||||
vpfe_ick: vpfe_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
vpfe_fck: vpfe_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&pclk_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <10>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <8>;
|
||||
};
|
||||
|
||||
hecc_ck: hecc_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
};
|
||||
&cm_clocks {
|
||||
ipss_ick: ipss_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
rmii_ck: rmii_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
pclk_ck: pclk_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
uart4_ick_am35xx: uart4_ick_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
uart4_fck_am35xx: uart4_fck_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_48m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
|
||||
<&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
|
||||
<&hecc_ck>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
|
||||
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
|
||||
};
|
||||
};
|
||||
|
|
@ -67,6 +67,32 @@
|
|||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
prcm: prcm@44df0000 {
|
||||
compatible = "ti,am4-prcm";
|
||||
reg = <0x44df0000 0x11000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@44e10000 {
|
||||
compatible = "ti,am4-scrm";
|
||||
reg = <0x44e10000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
|
||||
|
|
@ -665,3 +691,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "am43xx-clocks.dtsi"
|
||||
|
|
|
|||
656
arch/arm/boot/dts/am43xx-clocks.dtsi
Normal file
656
arch/arm/boot/dts/am43xx-clocks.dtsi
Normal file
|
|
@ -0,0 +1,656 @@
|
|||
/*
|
||||
* Device Tree Source for AM43xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
adc_tsc_fck: adc_tsc_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan0_fck: dcan0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan1_fck: dcan1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp0_fck: mcasp0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp1_fck: mcasp1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex0_fck: smartreflex0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex1_fck: smartreflex1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sha0_fck: sha0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes0_fck: aes0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
};
|
||||
&prcm_clocks {
|
||||
clk_32768_ck: clk_32768_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_rc32k_ck: clk_rc32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
virt_19200000_ck: virt_19200000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
virt_24000000_ck: virt_24000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
virt_25000000_ck: virt_25000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
virt_26000000_ck: virt_26000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
tclkin_ck: tclkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-core-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2d20>, <0x2d24>, <0x2d2c>;
|
||||
};
|
||||
|
||||
dpll_core_x2_ck: dpll_core_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_core_ck>;
|
||||
};
|
||||
|
||||
dpll_core_m4_ck: dpll_core_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d38>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_m5_ck: dpll_core_m5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d3c>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_m6_ck: dpll_core_m6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d40>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_mpu_ck: dpll_mpu_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2d60>, <0x2d64>, <0x2d6c>;
|
||||
};
|
||||
|
||||
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d70>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2da0>, <0x2da4>, <0x2dac>;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2db0>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_disp_ck: dpll_disp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2e20>, <0x2e24>, <0x2e2c>;
|
||||
};
|
||||
|
||||
dpll_disp_m2_ck: dpll_disp_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_disp_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e30>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-j-type-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2de0>, <0x2de4>, <0x2dec>;
|
||||
};
|
||||
|
||||
dpll_per_m2_ck: dpll_per_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,max-div = <127>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2df0>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
clkdiv32k_ck: clkdiv32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_24mhz>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <732>;
|
||||
};
|
||||
|
||||
clkdiv32k_ick: clkdiv32k_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a38>;
|
||||
};
|
||||
|
||||
sysclk_div: sysclk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pruss_ocp_gclk: pruss_ocp_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x4248>;
|
||||
};
|
||||
|
||||
clk_32k_tpm_ck: clk_32k_tpm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4200>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4204>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4208>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x420c>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4210>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4214>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4218>;
|
||||
};
|
||||
|
||||
wdt1_fck: wdt1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x422c>;
|
||||
};
|
||||
|
||||
l3_gclk: l3_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sysclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
l4hs_gclk: l4hs_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l3s_gclk: l3s_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4ls_gclk: l4ls_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x4238>;
|
||||
};
|
||||
|
||||
clk_32k_mosc_ck: clk_32k_mosc_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4240>;
|
||||
};
|
||||
|
||||
gpio0_dbclk: gpio0_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&gpio0_dbclk_mux_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2b68>;
|
||||
};
|
||||
|
||||
gpio1_dbclk: gpio1_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c78>;
|
||||
};
|
||||
|
||||
gpio2_dbclk: gpio2_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c80>;
|
||||
};
|
||||
|
||||
gpio3_dbclk: gpio3_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c88>;
|
||||
};
|
||||
|
||||
gpio4_dbclk: gpio4_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c90>;
|
||||
};
|
||||
|
||||
gpio5_dbclk: gpio5_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c98>;
|
||||
};
|
||||
|
||||
mmc_clk: mmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x423c>;
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: gfx_fck_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&gfx_fclk_clksel_ck>;
|
||||
reg = <0x423c>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
disp_clk: disp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
||||
reg = <0x4244>;
|
||||
};
|
||||
|
||||
dpll_extdev_ck: dpll_extdev_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2e60>, <0x2e64>, <0x2e6c>;
|
||||
};
|
||||
|
||||
dpll_extdev_m2_ck: dpll_extdev_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_extdev_ck>;
|
||||
ti,max-div = <127>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e70>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
mux_synctimer32k_ck: mux_synctimer32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4230>;
|
||||
};
|
||||
|
||||
synctimer_32kclk: synctimer_32kclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&mux_synctimer32k_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a30>;
|
||||
};
|
||||
|
||||
timer8_fck: timer8_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x421c>;
|
||||
};
|
||||
|
||||
timer9_fck: timer9_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4220>;
|
||||
};
|
||||
|
||||
timer10_fck: timer10_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4224>;
|
||||
};
|
||||
|
||||
timer11_fck: timer11_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4228>;
|
||||
};
|
||||
|
||||
cpsw_50m_clkdiv: cpsw_50m_clkdiv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_5m_clkdiv: cpsw_5m_clkdiv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpsw_50m_clkdiv>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <10>;
|
||||
};
|
||||
|
||||
dpll_ddr_x2_ck: dpll_ddr_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
};
|
||||
|
||||
dpll_ddr_m4_ck: dpll_ddr_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2db8>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_per_clkdcoldo: dpll_per_clkdcoldo {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dll_aging_clk_div: dll_aging_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
reg = <0x4250>;
|
||||
ti,dividers = <8>, <16>, <32>;
|
||||
};
|
||||
|
||||
div_core_25m_ck: div_core_25m_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sysclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
func_12m_clk: func_12m_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <16>;
|
||||
};
|
||||
|
||||
vtp_clk_div: vtp_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
usbphy_32khz_clkmux: usbphy_32khz_clkmux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4260>;
|
||||
};
|
||||
};
|
||||
|
|
@ -104,6 +104,45 @@
|
|||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
prm: prm@4ae06000 {
|
||||
compatible = "ti,dra7-prm";
|
||||
reg = <0x4ae06000 0x3000>;
|
||||
|
||||
prm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm_core_aon: cm_core_aon@4a005000 {
|
||||
compatible = "ti,dra7-cm-core-aon";
|
||||
reg = <0x4a005000 0x2000>;
|
||||
|
||||
cm_core_aon_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_aon_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm_core: cm_core@4a008000 {
|
||||
compatible = "ti,dra7-cm-core";
|
||||
reg = <0x4a008000 0x3000>;
|
||||
|
||||
cm_core_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
counter32k: counter@4ae04000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x4ae04000 0x40>;
|
||||
|
|
@ -584,3 +623,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "dra7xx-clocks.dtsi"
|
||||
|
|
|
|||
2015
arch/arm/boot/dts/dra7xx-clocks.dtsi
Normal file
2015
arch/arm/boot/dts/dra7xx-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -89,6 +89,45 @@
|
|||
interrupts = <0>;
|
||||
};
|
||||
|
||||
prm: prm@48306000 {
|
||||
compatible = "ti,omap3-prm";
|
||||
reg = <0x48306000 0x4000>;
|
||||
|
||||
prm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm: cm@48004000 {
|
||||
compatible = "ti,omap3-cm";
|
||||
reg = <0x48004000 0x4000>;
|
||||
|
||||
cm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@48002000 {
|
||||
compatible = "ti,omap3-scrm";
|
||||
reg = <0x48002000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
counter32k: counter@48320000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x48320000 0x20>;
|
||||
|
|
@ -632,3 +671,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap3xxx-clocks.dtsi"
|
||||
|
|
|
|||
208
arch/arm/boot/dts/omap3430es1-clocks.dtsi
Normal file
208
arch/arm/boot/dts/omap3430es1-clocks.dtsi
Normal file
|
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP3430 ES1 clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
gfx_l3_ck: gfx_l3_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0b10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
gfx_l3_fck: gfx_l3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&l3_ick>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0b40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
gfx_l3_ick: gfx_l3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&gfx_l3_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
gfx_cg1_ck: gfx_cg1_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&gfx_l3_fck>;
|
||||
reg = <0x0b00>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
gfx_cg2_ck: gfx_cg2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&gfx_l3_fck>;
|
||||
reg = <0x0b00>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
d2d_26m_fck: d2d_26m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
fshostusb_fck: fshostusb_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_48m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <5>;
|
||||
};
|
||||
|
||||
ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0a00>;
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
|
||||
ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
|
||||
};
|
||||
|
||||
ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&ssi_ssr_fck_3430es1>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
fac_ick: fac_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <8>;
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ssi_ick_3430es1: ssi_ick_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usb_l4_gate_ick: usb_l4_gate_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0a10>;
|
||||
};
|
||||
|
||||
usb_l4_div_ick: usb_l4_div_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <1>;
|
||||
reg = <0x0a40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
usb_l4_ick: usb_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
|
||||
};
|
||||
|
||||
dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0e00>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dss_ick_3430es1: dss_ick_3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x0e10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
|
||||
};
|
||||
|
||||
gfx_3430es1_clkdm: gfx_3430es1_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
|
||||
};
|
||||
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
|
||||
<&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
|
||||
};
|
||||
|
||||
d2d_clkdm: d2d_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&d2d_26m_fck>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
|
||||
};
|
||||
};
|
||||
268
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
Normal file
268
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
Normal file
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP34XX/OMAP36XX clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
security_l4_ick2: security_l4_ick2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes1_ick: aes1_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0a14>;
|
||||
};
|
||||
|
||||
rng_ick: rng_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
sha11_ick: sha11_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
des1_ick: des1_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
cam_mclk: cam_mclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll4_m5x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0f00>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
cam_ick: cam_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x0f10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
csi2_96m_fck: csi2_96m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0f00>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
security_l3_ick: security_l3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l3_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pka_ick: pka_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l3_ick>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
icr_ick: icr_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <29>;
|
||||
};
|
||||
|
||||
des2_ick: des2_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <26>;
|
||||
};
|
||||
|
||||
mspro_ick: mspro_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
mailboxes_ick: mailboxes_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sr1_fck: sr1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <6>;
|
||||
};
|
||||
|
||||
sr2_fck: sr2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
sr_l4_ick: sr_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll2_fck: dpll2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <19>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0040>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll2_ck: dpll2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-clock";
|
||||
clocks = <&sys_ck>, <&dpll2_fck>;
|
||||
reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
|
||||
ti,low-power-stop;
|
||||
ti,lock;
|
||||
ti,low-power-bypass;
|
||||
};
|
||||
|
||||
dpll2_m2_ck: dpll2_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0044>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
iva2_ck: iva2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&dpll2_m2_ck>;
|
||||
reg = <0x0000>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
modem_fck: modem_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <31>;
|
||||
};
|
||||
|
||||
sad2d_ick: sad2d_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
mad2d_ick: mad2d_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
mspro_fck: mspro_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
cam_clkdm: cam_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cam_ick>, <&csi2_96m_fck>;
|
||||
};
|
||||
|
||||
iva2_clkdm: iva2_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&iva2_ck>;
|
||||
};
|
||||
|
||||
dpll2_clkdm: dpll2_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll2_ck>;
|
||||
};
|
||||
|
||||
wkup_clkdm: wkup_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
|
||||
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
|
||||
<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
|
||||
};
|
||||
|
||||
d2d_clkdm: d2d_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
|
||||
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
|
||||
<&mspro_fck>;
|
||||
};
|
||||
};
|
||||
|
|
@ -39,3 +39,7 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap34xx-omap36xx-clocks.dtsi"
|
||||
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
|
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
|
||||
|
|
|
|||
242
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
Normal file
242
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
Normal file
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&prm_clocks {
|
||||
corex2_d3_fck: corex2_d3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <3>;
|
||||
};
|
||||
|
||||
corex2_d5_fck: corex2_d5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <5>;
|
||||
};
|
||||
};
|
||||
&cm_clocks {
|
||||
dpll5_ck: dpll5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
|
||||
ti,low-power-stop;
|
||||
ti,lock;
|
||||
};
|
||||
|
||||
dpll5_m2_ck: dpll5_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll5_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0d50>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
sgx_gate_fck: sgx_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0b00>;
|
||||
};
|
||||
|
||||
core_d3_ck: core_d3_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <3>;
|
||||
};
|
||||
|
||||
core_d4_ck: core_d4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
core_d6_ck: core_d6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <6>;
|
||||
};
|
||||
|
||||
omap_192m_alwon_fck: omap_192m_alwon_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll4_m2x2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
core_d2_ck: core_d2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
sgx_mux_fck: sgx_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
|
||||
reg = <0x0b40>;
|
||||
};
|
||||
|
||||
sgx_fck: sgx_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
|
||||
};
|
||||
|
||||
sgx_ick: sgx_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0b10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
cpefuse_fck: cpefuse_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ts_fck: ts_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&omap_32k_fck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
usbtll_fck: usbtll_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
usbtll_ick: usbtll_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
mmchs3_ick: mmchs3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
|
||||
mmchs3_fck: mmchs3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
|
||||
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0e00>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dss_ick_3430es2: dss_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dss-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x0e10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usbhost_120m_fck: usbhost_120m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
reg = <0x1400>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
usbhost_48m_fck: usbhost_48m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&omap_48m_fck>;
|
||||
reg = <0x1400>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usbhost_ick: usbhost_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dss-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x1410>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
dpll5_clkdm: dpll5_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll5_ck>;
|
||||
};
|
||||
|
||||
sgx_clkdm: sgx_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sgx_ick>;
|
||||
};
|
||||
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
|
||||
<&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
|
||||
};
|
||||
|
||||
usbhost_clkdm: usbhost_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
|
||||
<&usbhost_ick>;
|
||||
};
|
||||
};
|
||||
90
arch/arm/boot/dts/omap36xx-clocks.dtsi
Normal file
90
arch/arm/boot/dts/omap36xx-clocks.dtsi
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP36xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
dpll4_ck: dpll4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-per-j-type-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
|
||||
};
|
||||
|
||||
dpll4_m5x2_ck: dpll4_m5x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m5x2_mul_ck>;
|
||||
ti,bit-shift = <0x1e>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-rate-parent;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m2x2_ck: dpll4_m2x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll3_m3x2_ck: dpll3_m3x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll3_m3x2_mul_ck>;
|
||||
ti,bit-shift = <0xc>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m3x2_ck: dpll4_m3x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m3x2_mul_ck>;
|
||||
ti,bit-shift = <0x1c>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m6x2_ck: dpll4_m6x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m6x2_mul_ck>;
|
||||
ti,bit-shift = <0x1f>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
uart4_fck: uart4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&per_48m_fck>;
|
||||
reg = <0x1000>;
|
||||
ti,bit-shift = <18>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
dpll4_clkdm: dpll4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll4_ck>;
|
||||
};
|
||||
|
||||
per_clkdm: per_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
|
||||
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
|
||||
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
|
||||
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
|
||||
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
|
||||
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
|
||||
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
|
||||
<&mcbsp4_ick>, <&uart4_fck>;
|
||||
};
|
||||
};
|
||||
198
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
Normal file
198
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP34xx/OMAP36xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0a00>;
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
|
||||
ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
|
||||
};
|
||||
|
||||
ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&ssi_ssr_fck_3430es2>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-hsotgusb-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ssi_ick_3430es2: ssi_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usim_gate_fck: usim_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
ti,bit-shift = <9>;
|
||||
reg = <0x0c00>;
|
||||
};
|
||||
|
||||
sys_d2_ck: sys_d2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
omap_96m_d2_fck: omap_96m_d2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
omap_96m_d4_fck: omap_96m_d4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
omap_96m_d8_fck: omap_96m_d8_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
omap_96m_d10_fck: omap_96m_d10_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <10>;
|
||||
};
|
||||
|
||||
dpll5_m2_d4_ck: dpll5_m2_d4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll5_m2_d8_ck: dpll5_m2_d8_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
dpll5_m2_d16_ck: dpll5_m2_d16_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <16>;
|
||||
};
|
||||
|
||||
dpll5_m2_d20_ck: dpll5_m2_d20_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <20>;
|
||||
};
|
||||
|
||||
usim_mux_fck: usim_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0c40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
usim_fck: usim_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
|
||||
};
|
||||
|
||||
usim_ick: usim_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&wkup_l4_ick>;
|
||||
reg = <0x0c10>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
|
||||
};
|
||||
|
||||
wkup_clkdm: wkup_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
|
||||
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
|
||||
<&gpt1_ick>, <&usim_ick>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
|
||||
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&ssi_ick_3430es2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -51,3 +51,8 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap36xx-clocks.dtsi"
|
||||
/include/ "omap34xx-omap36xx-clocks.dtsi"
|
||||
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
|
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
|
||||
|
|
|
|||
1660
arch/arm/boot/dts/omap3xxx-clocks.dtsi
Normal file
1660
arch/arm/boot/dts/omap3xxx-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -107,6 +107,58 @@
|
|||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
cm1: cm1@4a004000 {
|
||||
compatible = "ti,omap4-cm1";
|
||||
reg = <0x4a004000 0x2000>;
|
||||
|
||||
cm1_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm1_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
prm: prm@4a306000 {
|
||||
compatible = "ti,omap4-prm";
|
||||
reg = <0x4a306000 0x3000>;
|
||||
|
||||
prm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm2: cm2@4a008000 {
|
||||
compatible = "ti,omap4-cm2";
|
||||
reg = <0x4a008000 0x3000>;
|
||||
|
||||
cm2_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm2_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@4a30a000 {
|
||||
compatible = "ti,omap4-scrm";
|
||||
reg = <0x4a30a000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
counter32k: counter@4a304000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x4a304000 0x20>;
|
||||
|
|
@ -707,3 +759,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap44xx-clocks.dtsi"
|
||||
|
|
|
|||
18
arch/arm/boot/dts/omap443x-clocks.dtsi
Normal file
18
arch/arm/boot/dts/omap443x-clocks.dtsi
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP4 clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&prm_clocks {
|
||||
bandgap_fclk: bandgap_fclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_32k_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x1888>;
|
||||
};
|
||||
};
|
||||
|
|
@ -44,3 +44,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap443x-clocks.dtsi"
|
||||
|
|
|
|||
|
|
@ -52,3 +52,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap446x-clocks.dtsi"
|
||||
|
|
|
|||
27
arch/arm/boot/dts/omap446x-clocks.dtsi
Normal file
27
arch/arm/boot/dts/omap446x-clocks.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP4 clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&prm_clocks {
|
||||
div_ts_ck: div_ts_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&l4_wkup_clk_mux_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x1888>;
|
||||
ti,dividers = <8>, <16>, <32>;
|
||||
};
|
||||
|
||||
bandgap_ts_fclk: bandgap_ts_fclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&div_ts_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x1888>;
|
||||
};
|
||||
};
|
||||
1651
arch/arm/boot/dts/omap44xx-clocks.dtsi
Normal file
1651
arch/arm/boot/dts/omap44xx-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -117,6 +117,58 @@
|
|||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
prm: prm@4ae06000 {
|
||||
compatible = "ti,omap5-prm";
|
||||
reg = <0x4ae06000 0x3000>;
|
||||
|
||||
prm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm_core_aon: cm_core_aon@4a004000 {
|
||||
compatible = "ti,omap5-cm-core-aon";
|
||||
reg = <0x4a004000 0x2000>;
|
||||
|
||||
cm_core_aon_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_aon_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@4ae0a000 {
|
||||
compatible = "ti,omap5-scrm";
|
||||
reg = <0x4ae0a000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm_core: cm_core@4a008000 {
|
||||
compatible = "ti,omap5-cm-core";
|
||||
reg = <0x4a008000 0x3000>;
|
||||
|
||||
cm_core_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_core_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
counter32k: counter@4ae04000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x4ae04000 0x40>;
|
||||
|
|
@ -751,3 +803,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap54xx-clocks.dtsi"
|
||||
|
|
|
|||
1399
arch/arm/boot/dts/omap54xx-clocks.dtsi
Normal file
1399
arch/arm/boot/dts/omap54xx-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -76,6 +76,16 @@ config SOC_AM43XX
|
|||
select ARM_GIC
|
||||
select MACH_OMAP_GENERIC
|
||||
|
||||
config SOC_DRA7XX
|
||||
bool "TI DRA7XX"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_OMAP2PLUS
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select HAVE_SMP
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
|
||||
config ARCH_OMAP2PLUS
|
||||
bool
|
||||
select ARCH_HAS_BANDGAP
|
||||
|
|
@ -128,14 +138,6 @@ config SOC_HAS_REALTIME_COUNTER
|
|||
depends on SOC_OMAP5 || SOC_DRA7XX
|
||||
default y
|
||||
|
||||
config SOC_DRA7XX
|
||||
bool "TI DRA7XX"
|
||||
select ARM_ARCH_TIMER
|
||||
select CPU_V7
|
||||
select ARM_GIC
|
||||
select HAVE_SMP
|
||||
select COMMON_CLK
|
||||
|
||||
comment "OMAP Core Type"
|
||||
depends on ARCH_OMAP2
|
||||
|
||||
|
|
|
|||
|
|
@ -130,6 +130,7 @@ obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
|
|||
obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common)
|
||||
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
|
||||
obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
|
||||
|
||||
# OMAP powerdomain framework
|
||||
powerdomain-common += powerdomain.o powerdomain-common.o
|
||||
|
|
@ -184,12 +185,14 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
|
|||
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
|
||||
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
|
||||
obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
|
||||
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
|
||||
obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
|
||||
obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o
|
||||
|
||||
# OMAP2 clock rate set data (old "OPP" data)
|
||||
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
|
|||
{
|
||||
u32 v;
|
||||
|
||||
v = __raw_readl(clk->clksel_reg);
|
||||
v = omap2_clk_readl(clk, clk->clksel_reg);
|
||||
v &= ~clk->clksel_mask;
|
||||
v |= field_val << __ffs(clk->clksel_mask);
|
||||
__raw_writel(v, clk->clksel_reg);
|
||||
omap2_clk_writel(v, clk, clk->clksel_reg);
|
||||
|
||||
v = __raw_readl(clk->clksel_reg); /* OCP barrier */
|
||||
v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
|
|||
if (!clk->clksel || !clk->clksel_mask)
|
||||
return 0;
|
||||
|
||||
v = __raw_readl(clk->clksel_reg);
|
||||
v = omap2_clk_readl(clk, clk->clksel_reg);
|
||||
v &= clk->clksel_mask;
|
||||
v >>= __ffs(clk->clksel_mask);
|
||||
|
||||
|
|
@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
|
|||
WARN((!clk->clksel || !clk->clksel_mask),
|
||||
"clock: %s: attempt to call on a non-clksel clock", clk_name);
|
||||
|
||||
r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
|
||||
r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;
|
||||
r >>= __ffs(clk->clksel_mask);
|
||||
|
||||
for (clks = clk->clksel; clks->parent && !found; clks++) {
|
||||
|
|
|
|||
|
|
@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
|
|||
if (!dd)
|
||||
return -EINVAL;
|
||||
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v = omap2_clk_readl(clk, dd->control_reg);
|
||||
v &= dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
|
||||
|
|
@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
|
|||
return 0;
|
||||
|
||||
/* Return bypass rate if DPLL is bypassed */
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v = omap2_clk_readl(clk, dd->control_reg);
|
||||
v &= dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
|
||||
|
|
@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
|
|||
return __clk_get_rate(dd->clk_bypass);
|
||||
}
|
||||
|
||||
v = __raw_readl(dd->mult_div1_reg);
|
||||
v = omap2_clk_readl(clk, dd->mult_div1_reg);
|
||||
dpll_mult = v & dd->mult_mask;
|
||||
dpll_mult >>= __ffs(dd->mult_mask);
|
||||
dpll_div = v & dd->div1_mask;
|
||||
|
|
|
|||
|
|
@ -25,25 +25,29 @@
|
|||
/* XXX */
|
||||
void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
|
||||
{
|
||||
u32 v, r;
|
||||
u32 v;
|
||||
void __iomem *r;
|
||||
|
||||
r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
|
||||
r = (__force void __iomem *)
|
||||
((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
|
||||
|
||||
v = __raw_readl((__force void __iomem *)r);
|
||||
v = omap2_clk_readl(clk, r);
|
||||
v |= (1 << clk->enable_bit);
|
||||
__raw_writel(v, (__force void __iomem *)r);
|
||||
omap2_clk_writel(v, clk, r);
|
||||
}
|
||||
|
||||
/* XXX */
|
||||
void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
|
||||
{
|
||||
u32 v, r;
|
||||
u32 v;
|
||||
void __iomem *r;
|
||||
|
||||
r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
|
||||
r = (__force void __iomem *)
|
||||
((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
|
||||
|
||||
v = __raw_readl((__force void __iomem *)r);
|
||||
v = omap2_clk_readl(clk, r);
|
||||
v &= ~(1 << clk->enable_bit);
|
||||
__raw_writel(v, (__force void __iomem *)r);
|
||||
omap2_clk_writel(v, clk, r);
|
||||
}
|
||||
|
||||
/* Public data */
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#include <linux/clk-private.h>
|
||||
#include <asm/cpu.h>
|
||||
|
||||
|
||||
#include <trace/events/power.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
|
@ -56,6 +55,31 @@ u16 cpu_mask;
|
|||
static bool clkdm_control = true;
|
||||
|
||||
static LIST_HEAD(clk_hw_omap_clocks);
|
||||
void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
|
||||
|
||||
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
|
||||
{
|
||||
if (clk->flags & MEMMAP_ADDRESSING) {
|
||||
struct clk_omap_reg *r = (struct clk_omap_reg *)®
|
||||
writel_relaxed(val, clk_memmaps[r->index] + r->offset);
|
||||
} else {
|
||||
writel_relaxed(val, reg);
|
||||
}
|
||||
}
|
||||
|
||||
u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (clk->flags & MEMMAP_ADDRESSING) {
|
||||
struct clk_omap_reg *r = (struct clk_omap_reg *)®
|
||||
val = readl_relaxed(clk_memmaps[r->index] + r->offset);
|
||||
} else {
|
||||
val = readl_relaxed(reg);
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
* Used for clocks that have the same value as the parent clock,
|
||||
|
|
@ -87,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
|
|||
|
||||
/**
|
||||
* _wait_idlest_generic - wait for a module to leave the idle state
|
||||
* @clk: module clock to wait for (needed for register offsets)
|
||||
* @reg: virtual address of module IDLEST register
|
||||
* @mask: value to mask against to determine if the module is active
|
||||
* @idlest: idle state indicator (0 or 1) for the clock
|
||||
|
|
@ -98,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
|
|||
* elapsed. XXX Deprecated - should be moved into drivers for the
|
||||
* individual IP block that the IDLEST register exists in.
|
||||
*/
|
||||
static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
|
||||
const char *name)
|
||||
static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
|
||||
u32 mask, u8 idlest, const char *name)
|
||||
{
|
||||
int i = 0, ena = 0;
|
||||
|
||||
ena = (idlest) ? 0 : mask;
|
||||
|
||||
omap_test_timeout(((__raw_readl(reg) & mask) == ena),
|
||||
omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
|
||||
MAX_MODULE_ENABLE_WAIT, i);
|
||||
|
||||
if (i < MAX_MODULE_ENABLE_WAIT)
|
||||
|
|
@ -138,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
|
|||
/* Not all modules have multiple clocks that their IDLEST depends on */
|
||||
if (clk->ops->find_companion) {
|
||||
clk->ops->find_companion(clk, &companion_reg, &other_bit);
|
||||
if (!(__raw_readl(companion_reg) & (1 << other_bit)))
|
||||
if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -146,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
|
|||
r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
|
||||
if (r) {
|
||||
/* IDLEST register not in the CM module */
|
||||
_wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
|
||||
__clk_get_name(clk->hw.clk));
|
||||
_wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
|
||||
idlest_val, __clk_get_name(clk->hw.clk));
|
||||
} else {
|
||||
cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
|
||||
};
|
||||
|
|
@ -309,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
|
|||
}
|
||||
|
||||
/* FIXME should not have INVERT_ENABLE bit here */
|
||||
v = __raw_readl(clk->enable_reg);
|
||||
v = omap2_clk_readl(clk, clk->enable_reg);
|
||||
if (clk->flags & INVERT_ENABLE)
|
||||
v &= ~(1 << clk->enable_bit);
|
||||
else
|
||||
v |= (1 << clk->enable_bit);
|
||||
__raw_writel(v, clk->enable_reg);
|
||||
v = __raw_readl(clk->enable_reg); /* OCP barrier */
|
||||
omap2_clk_writel(v, clk, clk->enable_reg);
|
||||
v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
|
||||
|
||||
if (clk->ops && clk->ops->find_idlest)
|
||||
_omap2_module_wait_ready(clk);
|
||||
|
|
@ -353,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
|
|||
return;
|
||||
}
|
||||
|
||||
v = __raw_readl(clk->enable_reg);
|
||||
v = omap2_clk_readl(clk, clk->enable_reg);
|
||||
if (clk->flags & INVERT_ENABLE)
|
||||
v |= (1 << clk->enable_bit);
|
||||
else
|
||||
v &= ~(1 << clk->enable_bit);
|
||||
__raw_writel(v, clk->enable_reg);
|
||||
omap2_clk_writel(v, clk, clk->enable_reg);
|
||||
/* No OCP barrier needed here since it is a disable operation */
|
||||
|
||||
if (clkdm_control && clk->clkdm)
|
||||
|
|
@ -454,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
|
|||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
u32 v;
|
||||
|
||||
v = __raw_readl(clk->enable_reg);
|
||||
v = omap2_clk_readl(clk, clk->enable_reg);
|
||||
|
||||
if (clk->flags & INVERT_ENABLE)
|
||||
v ^= BIT(clk->enable_bit);
|
||||
|
|
@ -520,6 +545,9 @@ int omap2_clk_enable_autoidle_all(void)
|
|||
list_for_each_entry(c, &clk_hw_omap_clocks, node)
|
||||
if (c->ops && c->ops->allow_idle)
|
||||
c->ops->allow_idle(c);
|
||||
|
||||
of_ti_clk_allow_autoidle_all();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -539,6 +567,9 @@ int omap2_clk_disable_autoidle_all(void)
|
|||
list_for_each_entry(c, &clk_hw_omap_clocks, node)
|
||||
if (c->ops && c->ops->deny_idle)
|
||||
c->ops->deny_idle(c);
|
||||
|
||||
of_ti_clk_deny_autoidle_all();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
struct omap_clk {
|
||||
u16 cpu;
|
||||
|
|
@ -37,7 +38,6 @@ struct omap_clk {
|
|||
}
|
||||
|
||||
struct clockdomain;
|
||||
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
|
||||
|
||||
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
|
||||
static struct clk _name = { \
|
||||
|
|
@ -178,141 +178,6 @@ struct clksel {
|
|||
const struct clksel_rate *rates;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dpll_data - DPLL registers and integration data
|
||||
* @mult_div1_reg: register containing the DPLL M and N bitfields
|
||||
* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
|
||||
* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
|
||||
* @clk_bypass: struct clk pointer to the clock's bypass clock input
|
||||
* @clk_ref: struct clk pointer to the clock's reference clock input
|
||||
* @control_reg: register containing the DPLL mode bitfield
|
||||
* @enable_mask: mask of the DPLL mode bitfield in @control_reg
|
||||
* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
|
||||
* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
|
||||
* @last_rounded_m4xen: cache of the last M4X result of
|
||||
* omap4_dpll_regm4xen_round_rate()
|
||||
* @last_rounded_lpmode: cache of the last lpmode result of
|
||||
* omap4_dpll_lpmode_recalc()
|
||||
* @max_multiplier: maximum valid non-bypass multiplier value (actual)
|
||||
* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
|
||||
* @min_divider: minimum valid non-bypass divider value (actual)
|
||||
* @max_divider: maximum valid non-bypass divider value (actual)
|
||||
* @modes: possible values of @enable_mask
|
||||
* @autoidle_reg: register containing the DPLL autoidle mode bitfield
|
||||
* @idlest_reg: register containing the DPLL idle status bitfield
|
||||
* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
|
||||
* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
|
||||
* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
|
||||
* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
|
||||
* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
|
||||
* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
|
||||
* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
|
||||
* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
|
||||
* @flags: DPLL type/features (see below)
|
||||
*
|
||||
* Possible values for @flags:
|
||||
* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
|
||||
*
|
||||
* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
|
||||
*
|
||||
* XXX Some DPLLs have multiple bypass inputs, so it's not technically
|
||||
* correct to only have one @clk_bypass pointer.
|
||||
*
|
||||
* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
|
||||
* @last_rounded_n) should be separated from the runtime-fixed fields
|
||||
* and placed into a different structure, so that the runtime-fixed data
|
||||
* can be placed into read-only space.
|
||||
*/
|
||||
struct dpll_data {
|
||||
void __iomem *mult_div1_reg;
|
||||
u32 mult_mask;
|
||||
u32 div1_mask;
|
||||
struct clk *clk_bypass;
|
||||
struct clk *clk_ref;
|
||||
void __iomem *control_reg;
|
||||
u32 enable_mask;
|
||||
unsigned long last_rounded_rate;
|
||||
u16 last_rounded_m;
|
||||
u8 last_rounded_m4xen;
|
||||
u8 last_rounded_lpmode;
|
||||
u16 max_multiplier;
|
||||
u8 last_rounded_n;
|
||||
u8 min_divider;
|
||||
u16 max_divider;
|
||||
u8 modes;
|
||||
void __iomem *autoidle_reg;
|
||||
void __iomem *idlest_reg;
|
||||
u32 autoidle_mask;
|
||||
u32 freqsel_mask;
|
||||
u32 idlest_mask;
|
||||
u32 dco_mask;
|
||||
u32 sddiv_mask;
|
||||
u32 lpmode_mask;
|
||||
u32 m4xen_mask;
|
||||
u8 auto_recal_bit;
|
||||
u8 recal_en_bit;
|
||||
u8 recal_st_bit;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct clk.flags possibilities
|
||||
*
|
||||
* XXX document the rest of the clock flags here
|
||||
*
|
||||
* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
|
||||
* bits share the same register. This flag allows the
|
||||
* omap4_dpllmx*() code to determine which GATE_CTRL bit field
|
||||
* should be used. This is a temporary solution - a better approach
|
||||
* would be to associate clock type-specific data with the clock,
|
||||
* similar to the struct dpll_data approach.
|
||||
*/
|
||||
#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
|
||||
#define CLOCK_IDLE_CONTROL (1 << 1)
|
||||
#define CLOCK_NO_IDLE_PARENT (1 << 2)
|
||||
#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
|
||||
#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
|
||||
#define CLOCK_CLKOUTX2 (1 << 5)
|
||||
|
||||
/**
|
||||
* struct clk_hw_omap - OMAP struct clk
|
||||
* @node: list_head connecting this clock into the full clock list
|
||||
* @enable_reg: register to write to enable the clock (see @enable_bit)
|
||||
* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
|
||||
* @flags: see "struct clk.flags possibilities" above
|
||||
* @clksel_reg: for clksel clks, register va containing src/divisor select
|
||||
* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
|
||||
* @clksel: for clksel clks, pointer to struct clksel for this clock
|
||||
* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
|
||||
* @clkdm_name: clockdomain name that this clock is contained in
|
||||
* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
|
||||
* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
|
||||
* @src_offset: bitshift for source selection bitfield (OMAP1 only)
|
||||
*
|
||||
* XXX @rate_offset, @src_offset should probably be removed and OMAP1
|
||||
* clock code converted to use clksel.
|
||||
*
|
||||
*/
|
||||
|
||||
struct clk_hw_omap_ops;
|
||||
|
||||
struct clk_hw_omap {
|
||||
struct clk_hw hw;
|
||||
struct list_head node;
|
||||
unsigned long fixed_rate;
|
||||
u8 fixed_div;
|
||||
void __iomem *enable_reg;
|
||||
u8 enable_bit;
|
||||
u8 flags;
|
||||
void __iomem *clksel_reg;
|
||||
u32 clksel_mask;
|
||||
const struct clksel *clksel;
|
||||
struct dpll_data *dpll_data;
|
||||
const char *clkdm_name;
|
||||
struct clockdomain *clkdm;
|
||||
const struct clk_hw_omap_ops *ops;
|
||||
};
|
||||
|
||||
struct clk_hw_omap_ops {
|
||||
void (*find_idlest)(struct clk_hw_omap *oclk,
|
||||
void __iomem **idlest_reg,
|
||||
|
|
@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
|
|||
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
|
||||
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
|
||||
|
||||
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
|
||||
#define DPLL_LOW_POWER_STOP 0x1
|
||||
#define DPLL_LOW_POWER_BYPASS 0x5
|
||||
#define DPLL_LOCKED 0x7
|
||||
|
||||
/* DPLL Type and DCO Selection Flags */
|
||||
#define DPLL_J_TYPE 0x1
|
||||
|
||||
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
|
||||
int omap3_noncore_dpll_enable(struct clk_hw *hw);
|
||||
void omap3_noncore_dpll_disable(struct clk_hw *hw);
|
||||
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
|
||||
void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
|
||||
void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
|
||||
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
|
||||
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
|
||||
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
|
||||
unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
|
||||
void omap2_init_clk_clkdm(struct clk_hw *clk);
|
||||
void __init omap2_clk_disable_clkdm_control(void);
|
||||
|
||||
/* clkt_clksel.c public functions */
|
||||
|
|
@ -396,29 +238,25 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
|
|||
extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
|
||||
extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
|
||||
|
||||
u8 omap2_init_dpll_parent(struct clk_hw *hw);
|
||||
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
|
||||
|
||||
int omap2_dflt_clk_enable(struct clk_hw *hw);
|
||||
void omap2_dflt_clk_disable(struct clk_hw *hw);
|
||||
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
|
||||
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
|
||||
void __iomem **other_reg,
|
||||
u8 *other_bit);
|
||||
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit, u8 *idlest_val);
|
||||
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
|
||||
int omap2_clk_enable_autoidle_all(void);
|
||||
int omap2_clk_disable_autoidle_all(void);
|
||||
int omap2_clk_allow_idle(struct clk *clk);
|
||||
int omap2_clk_deny_idle(struct clk *clk);
|
||||
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
|
||||
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
|
||||
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
|
||||
const char *core_ck_name,
|
||||
const char *mpu_ck_name);
|
||||
|
||||
u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
|
||||
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
|
||||
|
||||
extern u16 cpu_mask;
|
||||
|
||||
extern const struct clkops clkops_omap2_dflt_wait;
|
||||
|
|
@ -433,19 +271,12 @@ extern const struct clksel_rate gfx_l3_rates[];
|
|||
extern const struct clksel_rate dsp_ick_rates[];
|
||||
extern struct clk dummy_ck;
|
||||
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
|
||||
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
|
||||
extern const struct clk_hw_omap_ops clkhwops_iclk;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_apll54;
|
||||
extern const struct clk_hw_omap_ops clkhwops_apll96;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
|
||||
|
|
@ -460,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[];
|
|||
extern const struct clksel_rate div_1_4_rates[];
|
||||
extern const struct clksel_rate div31_1to31_rates[];
|
||||
|
||||
extern void __iomem *clk_memmaps[];
|
||||
|
||||
extern int am33xx_clk_init(void);
|
||||
|
||||
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
|
|||
struct clk_divider *parent;
|
||||
struct clk_hw *parent_hw;
|
||||
u32 dummy_v, orig_v;
|
||||
struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);
|
||||
int ret;
|
||||
|
||||
/* Clear PWRDN bit of HSDIVIDER */
|
||||
|
|
@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
|
|||
|
||||
/* Restore the dividers */
|
||||
if (!ret) {
|
||||
orig_v = __raw_readl(parent->reg);
|
||||
orig_v = omap2_clk_readl(omap_clk, parent->reg);
|
||||
dummy_v = orig_v;
|
||||
|
||||
/* Write any other value different from the Read value */
|
||||
dummy_v ^= (1 << parent->shift);
|
||||
__raw_writel(dummy_v, parent->reg);
|
||||
omap2_clk_writel(dummy_v, omap_clk, parent->reg);
|
||||
|
||||
/* Write the original divider */
|
||||
__raw_writel(orig_v, parent->reg);
|
||||
omap2_clk_writel(orig_v, omap_clk, parent->reg);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -9,11 +9,8 @@
|
|||
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
|
||||
|
||||
int omap3xxx_clk_init(void);
|
||||
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
void omap3_clk_lock_dpll5(void);
|
||||
|
||||
extern struct clk *sdrc_ick_p;
|
||||
extern struct clk *arm_fck_p;
|
||||
|
|
|
|||
|
|
@ -306,7 +306,7 @@ struct omap_hwmod;
|
|||
extern int omap_dss_reset(struct omap_hwmod *);
|
||||
|
||||
/* SoC specific clock initializer */
|
||||
extern int (*omap_clk_init)(void);
|
||||
int omap_clk_init(void);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
|
||||
|
|
|
|||
|
|
@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
|
|||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v = omap2_clk_readl(clk, dd->control_reg);
|
||||
v &= ~dd->enable_mask;
|
||||
v |= clken_bits << __ffs(dd->enable_mask);
|
||||
__raw_writel(v, dd->control_reg);
|
||||
omap2_clk_writel(v, clk, dd->control_reg);
|
||||
}
|
||||
|
||||
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
|
||||
|
|
@ -69,8 +69,8 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
|
|||
|
||||
state <<= __ffs(dd->idlest_mask);
|
||||
|
||||
while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
|
||||
i < MAX_DPLL_WAIT_TRIES) {
|
||||
while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
|
||||
!= state) && i < MAX_DPLL_WAIT_TRIES) {
|
||||
i++;
|
||||
udelay(1);
|
||||
}
|
||||
|
|
@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
|
|||
state <<= __ffs(dd->idlest_mask);
|
||||
|
||||
/* Check if already locked */
|
||||
if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
|
||||
if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
|
||||
goto done;
|
||||
|
||||
ai = omap3_dpll_autoidle_read(clk);
|
||||
|
|
@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
|
|||
* only since freqsel field is no longer present on other devices.
|
||||
*/
|
||||
if (cpu_is_omap343x()) {
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v = omap2_clk_readl(clk, dd->control_reg);
|
||||
v &= ~dd->freqsel_mask;
|
||||
v |= freqsel << __ffs(dd->freqsel_mask);
|
||||
__raw_writel(v, dd->control_reg);
|
||||
omap2_clk_writel(v, clk, dd->control_reg);
|
||||
}
|
||||
|
||||
/* Set DPLL multiplier, divider */
|
||||
v = __raw_readl(dd->mult_div1_reg);
|
||||
v = omap2_clk_readl(clk, dd->mult_div1_reg);
|
||||
v &= ~(dd->mult_mask | dd->div1_mask);
|
||||
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
|
||||
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
|
||||
|
|
@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
|
|||
v |= sd_div << __ffs(dd->sddiv_mask);
|
||||
}
|
||||
|
||||
__raw_writel(v, dd->mult_div1_reg);
|
||||
omap2_clk_writel(v, clk, dd->mult_div1_reg);
|
||||
|
||||
/* Set 4X multiplier and low-power mode */
|
||||
if (dd->m4xen_mask || dd->lpmode_mask) {
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v = omap2_clk_readl(clk, dd->control_reg);
|
||||
|
||||
if (dd->m4xen_mask) {
|
||||
if (dd->last_rounded_m4xen)
|
||||
|
|
@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
|
|||
v &= ~dd->lpmode_mask;
|
||||
}
|
||||
|
||||
__raw_writel(v, dd->control_reg);
|
||||
omap2_clk_writel(v, clk, dd->control_reg);
|
||||
}
|
||||
|
||||
/* We let the clock framework set the other output dividers later */
|
||||
|
|
@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
|
|||
if (!dd->autoidle_reg)
|
||||
return -EINVAL;
|
||||
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v = omap2_clk_readl(clk, dd->autoidle_reg);
|
||||
v &= dd->autoidle_mask;
|
||||
v >>= __ffs(dd->autoidle_mask);
|
||||
|
||||
|
|
@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
|
|||
* by writing 0x5 instead of 0x1. Add some mechanism to
|
||||
* optionally enter this mode.
|
||||
*/
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v = omap2_clk_readl(clk, dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
|
||||
__raw_writel(v, dd->autoidle_reg);
|
||||
omap2_clk_writel(v, clk, dd->autoidle_reg);
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -614,10 +614,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
|
|||
if (!dd->autoidle_reg)
|
||||
return;
|
||||
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v = omap2_clk_readl(clk, dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
|
||||
__raw_writel(v, dd->autoidle_reg);
|
||||
omap2_clk_writel(v, clk, dd->autoidle_reg);
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -639,6 +639,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
|||
struct clk_hw_omap *pclk = NULL;
|
||||
struct clk *parent;
|
||||
|
||||
if (!parent_rate)
|
||||
return 0;
|
||||
|
||||
/* Walk up the parents of clk, looking for a DPLL */
|
||||
do {
|
||||
do {
|
||||
|
|
@ -660,7 +663,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
|||
|
||||
WARN_ON(!dd->enable_mask);
|
||||
|
||||
v = __raw_readl(dd->control_reg) & dd->enable_mask;
|
||||
v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
|
||||
rate = parent_rate;
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
|
|||
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
|
||||
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
|
||||
|
||||
v = __raw_readl(clk->clksel_reg);
|
||||
v = omap2_clk_readl(clk, clk->clksel_reg);
|
||||
v &= mask;
|
||||
v >>= __ffs(mask);
|
||||
|
||||
|
|
@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
|
|||
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
|
||||
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
|
||||
|
||||
v = __raw_readl(clk->clksel_reg);
|
||||
v = omap2_clk_readl(clk, clk->clksel_reg);
|
||||
/* Clear the bit to allow gatectrl */
|
||||
v &= ~mask;
|
||||
__raw_writel(v, clk->clksel_reg);
|
||||
omap2_clk_writel(v, clk, clk->clksel_reg);
|
||||
}
|
||||
|
||||
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
|
||||
|
|
@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
|
|||
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
|
||||
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
|
||||
|
||||
v = __raw_readl(clk->clksel_reg);
|
||||
v = omap2_clk_readl(clk, clk->clksel_reg);
|
||||
/* Set the bit to deny gatectrl */
|
||||
v |= mask;
|
||||
__raw_writel(v, clk->clksel_reg);
|
||||
omap2_clk_writel(v, clk, clk->clksel_reg);
|
||||
}
|
||||
|
||||
const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
|
||||
|
|
@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
|
|||
rate = omap2_get_dpll_rate(clk);
|
||||
|
||||
/* regm4xen adds a multiplier of 4 to DPLL calculations */
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v = omap2_clk_readl(clk, dd->control_reg);
|
||||
if (v & OMAP4430_DPLL_REGM4XEN_MASK)
|
||||
rate *= OMAP4430_REGM4XEN_MULT;
|
||||
|
||||
|
|
|
|||
|
|
@ -55,10 +55,10 @@
|
|||
#include "prm44xx.h"
|
||||
|
||||
/*
|
||||
* omap_clk_init: points to a function that does the SoC-specific
|
||||
* omap_clk_soc_init: points to a function that does the SoC-specific
|
||||
* clock initializations
|
||||
*/
|
||||
int (*omap_clk_init)(void);
|
||||
static int (*omap_clk_soc_init)(void);
|
||||
|
||||
/*
|
||||
* The machine specific code may provide the extra mapping besides the
|
||||
|
|
@ -419,7 +419,7 @@ void __init omap2420_init_early(void)
|
|||
omap242x_clockdomains_init();
|
||||
omap2420_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_init = omap2420_clk_init;
|
||||
omap_clk_soc_init = omap2420_clk_init;
|
||||
}
|
||||
|
||||
void __init omap2420_init_late(void)
|
||||
|
|
@ -448,7 +448,7 @@ void __init omap2430_init_early(void)
|
|||
omap243x_clockdomains_init();
|
||||
omap2430_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_init = omap2430_clk_init;
|
||||
omap_clk_soc_init = omap2430_clk_init;
|
||||
}
|
||||
|
||||
void __init omap2430_init_late(void)
|
||||
|
|
@ -482,27 +482,35 @@ void __init omap3_init_early(void)
|
|||
omap3xxx_clockdomains_init();
|
||||
omap3xxx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_init = omap3xxx_clk_init;
|
||||
omap_clk_soc_init = omap3xxx_clk_init;
|
||||
}
|
||||
|
||||
void __init omap3430_init_early(void)
|
||||
{
|
||||
omap3_init_early();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = omap3430_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init omap35xx_init_early(void)
|
||||
{
|
||||
omap3_init_early();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = omap3430_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init omap3630_init_early(void)
|
||||
{
|
||||
omap3_init_early();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = omap3630_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init am35xx_init_early(void)
|
||||
{
|
||||
omap3_init_early();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = am35xx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init ti81xx_init_early(void)
|
||||
|
|
@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
|
|||
omap3xxx_clockdomains_init();
|
||||
omap3xxx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_init = omap3xxx_clk_init;
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = ti81xx_dt_clk_init;
|
||||
else
|
||||
omap_clk_soc_init = omap3xxx_clk_init;
|
||||
}
|
||||
|
||||
void __init omap3_init_late(void)
|
||||
|
|
@ -581,7 +592,7 @@ void __init am33xx_init_early(void)
|
|||
am33xx_clockdomains_init();
|
||||
am33xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_init = am33xx_clk_init;
|
||||
omap_clk_soc_init = am33xx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init am33xx_init_late(void)
|
||||
|
|
@ -606,6 +617,7 @@ void __init am43xx_init_early(void)
|
|||
am43xx_clockdomains_init();
|
||||
am43xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_soc_init = am43xx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init am43xx_init_late(void)
|
||||
|
|
@ -635,7 +647,7 @@ void __init omap4430_init_early(void)
|
|||
omap44xx_clockdomains_init();
|
||||
omap44xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_init = omap4xxx_clk_init;
|
||||
omap_clk_soc_init = omap4xxx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init omap4430_init_late(void)
|
||||
|
|
@ -666,6 +678,7 @@ void __init omap5_init_early(void)
|
|||
omap54xx_clockdomains_init();
|
||||
omap54xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_soc_init = omap5xxx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init omap5_init_late(void)
|
||||
|
|
@ -691,6 +704,7 @@ void __init dra7xx_init_early(void)
|
|||
dra7xx_clockdomains_init();
|
||||
dra7xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_soc_init = dra7xx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init dra7xx_init_late(void)
|
||||
|
|
@ -710,3 +724,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
|||
_omap2_init_reprogram_sdrc();
|
||||
}
|
||||
}
|
||||
|
||||
int __init omap_clk_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!omap_clk_soc_init)
|
||||
return 0;
|
||||
|
||||
ret = of_prcm_init();
|
||||
if (!ret)
|
||||
ret = omap_clk_soc_init();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
|
|||
if (oh->clkdm) {
|
||||
return oh->clkdm;
|
||||
} else if (oh->_clk) {
|
||||
if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
|
||||
return NULL;
|
||||
clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
|
||||
return clk->clkdm;
|
||||
}
|
||||
|
|
@ -1576,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
|
|||
if (!oh->clkdm) {
|
||||
pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
|
||||
oh->name, oh->clkdm_name);
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
|
||||
|
|
@ -4231,6 +4233,7 @@ void __init omap_hwmod_init(void)
|
|||
soc_ops.assert_hardreset = _omap2_assert_hardreset;
|
||||
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
|
||||
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
|
||||
soc_ops.init_clkdm = _init_clkdm;
|
||||
} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
|
||||
soc_ops.enable_module = _omap4_enable_module;
|
||||
soc_ops.disable_module = _omap4_disable_module;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
# ifndef __ASSEMBLER__
|
||||
extern void __iomem *prm_base;
|
||||
extern void omap2_set_globals_prm(void __iomem *prm);
|
||||
int of_prcm_init(void);
|
||||
# endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,10 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "prm2xxx_3xxx.h"
|
||||
|
|
@ -30,6 +34,7 @@
|
|||
#include "prm3xxx.h"
|
||||
#include "prm44xx.h"
|
||||
#include "common.h"
|
||||
#include "clock.h"
|
||||
|
||||
/*
|
||||
* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
|
||||
|
|
@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id omap_prcm_dt_match_table[] = {
|
||||
{ .compatible = "ti,am3-prcm" },
|
||||
{ .compatible = "ti,am3-scrm" },
|
||||
{ .compatible = "ti,am4-prcm" },
|
||||
{ .compatible = "ti,am4-scrm" },
|
||||
{ .compatible = "ti,omap3-prm" },
|
||||
{ .compatible = "ti,omap3-cm" },
|
||||
{ .compatible = "ti,omap3-scrm" },
|
||||
{ .compatible = "ti,omap4-cm1" },
|
||||
{ .compatible = "ti,omap4-prm" },
|
||||
{ .compatible = "ti,omap4-cm2" },
|
||||
{ .compatible = "ti,omap4-scrm" },
|
||||
{ .compatible = "ti,omap5-prm" },
|
||||
{ .compatible = "ti,omap5-cm-core-aon" },
|
||||
{ .compatible = "ti,omap5-scrm" },
|
||||
{ .compatible = "ti,omap5-cm-core" },
|
||||
{ .compatible = "ti,dra7-prm" },
|
||||
{ .compatible = "ti,dra7-cm-core-aon" },
|
||||
{ .compatible = "ti,dra7-cm-core" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_hw_omap memmap_dummy_ck = {
|
||||
.flags = MEMMAP_ADDRESSING,
|
||||
};
|
||||
|
||||
static u32 prm_clk_readl(void __iomem *reg)
|
||||
{
|
||||
return omap2_clk_readl(&memmap_dummy_ck, reg);
|
||||
}
|
||||
|
||||
static void prm_clk_writel(u32 val, void __iomem *reg)
|
||||
{
|
||||
omap2_clk_writel(val, &memmap_dummy_ck, reg);
|
||||
}
|
||||
|
||||
static struct ti_clk_ll_ops omap_clk_ll_ops = {
|
||||
.clk_readl = prm_clk_readl,
|
||||
.clk_writel = prm_clk_writel,
|
||||
};
|
||||
|
||||
int __init of_prcm_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *mem;
|
||||
int memmap_index = 0;
|
||||
|
||||
ti_clk_ll_ops = &omap_clk_ll_ops;
|
||||
|
||||
for_each_matching_node(np, omap_prcm_dt_match_table) {
|
||||
mem = of_iomap(np, 0);
|
||||
clk_memmaps[memmap_index] = mem;
|
||||
ti_dt_clk_init_provider(np, memmap_index);
|
||||
memmap_index++;
|
||||
}
|
||||
|
||||
ti_dt_clockdomains_setup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void)
|
|||
clksrc_nr, clksrc_src, clksrc_prop) \
|
||||
void __init omap##name##_gptimer_timer_init(void) \
|
||||
{ \
|
||||
if (omap_clk_init) \
|
||||
omap_clk_init(); \
|
||||
omap_clk_init(); \
|
||||
omap_dmtimer_init(); \
|
||||
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
|
||||
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
|
||||
|
|
@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void) \
|
|||
clksrc_nr, clksrc_src, clksrc_prop) \
|
||||
void __init omap##name##_sync32k_timer_init(void) \
|
||||
{ \
|
||||
if (omap_clk_init) \
|
||||
omap_clk_init(); \
|
||||
omap_clk_init(); \
|
||||
omap_dmtimer_init(); \
|
||||
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
|
||||
/* Enable the use of clocksource="gp_timer" kernel parameter */ \
|
||||
|
|
|
|||
|
|
@ -9,45 +9,44 @@ obj-$(CONFIG_COMMON_CLK) += clk-gate.o
|
|||
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
|
||||
obj-$(CONFIG_COMMON_CLK) += clk-composite.o
|
||||
|
||||
# SoCs specific
|
||||
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
|
||||
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
|
||||
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
|
||||
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
|
||||
obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
|
||||
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
|
||||
obj-$(CONFIG_ARCH_MXS) += mxs/
|
||||
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
|
||||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
obj-$(CONFIG_ARCH_U300) += clk-u300.o
|
||||
obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
|
||||
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
|
||||
obj-$(CONFIG_PLAT_ORION) += mvebu/
|
||||
ifeq ($(CONFIG_COMMON_CLK), y)
|
||||
obj-$(CONFIG_ARCH_MMP) += mmp/
|
||||
endif
|
||||
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
|
||||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_ARCH_U8500) += ux500/
|
||||
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
|
||||
obj-$(CONFIG_ARCH_SIRF) += sirf/
|
||||
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
|
||||
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
|
||||
# hardware specific clock types
|
||||
# please keep this section sorted lexicographically by file/directory path name
|
||||
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
|
||||
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
|
||||
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
|
||||
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
|
||||
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
|
||||
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
|
||||
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
|
||||
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
|
||||
obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
|
||||
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
|
||||
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
|
||||
obj-$(CONFIG_ARCH_U300) += clk-u300.o
|
||||
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
|
||||
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
|
||||
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
|
||||
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
|
||||
obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
|
||||
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
|
||||
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
|
||||
ifeq ($(CONFIG_COMMON_CLK), y)
|
||||
obj-$(CONFIG_ARCH_MMP) += mmp/
|
||||
endif
|
||||
obj-$(CONFIG_PLAT_ORION) += mvebu/
|
||||
obj-$(CONFIG_ARCH_MXS) += mxs/
|
||||
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
|
||||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
||||
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
|
||||
obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
|
||||
|
||||
obj-$(CONFIG_X86) += x86/
|
||||
|
||||
# Chip specific
|
||||
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
|
||||
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
|
||||
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
|
||||
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
|
||||
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
|
||||
obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
|
||||
obj-$(CONFIG_ARCH_SIRF) += sirf/
|
||||
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
|
||||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/
|
||||
obj-$(CONFIG_ARCH_U8500) += ux500/
|
||||
obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
|
||||
obj-$(CONFIG_X86) += x86/
|
||||
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
|
||||
|
|
|
|||
|
|
@ -1111,11 +1111,11 @@ static const struct of_device_id si5351_dt_ids[] = {
|
|||
};
|
||||
MODULE_DEVICE_TABLE(of, si5351_dt_ids);
|
||||
|
||||
static int si5351_dt_parse(struct i2c_client *client)
|
||||
static int si5351_dt_parse(struct i2c_client *client,
|
||||
enum si5351_variant variant)
|
||||
{
|
||||
struct device_node *child, *np = client->dev.of_node;
|
||||
struct si5351_platform_data *pdata;
|
||||
const struct of_device_id *match;
|
||||
struct property *prop;
|
||||
const __be32 *p;
|
||||
int num = 0;
|
||||
|
|
@ -1124,15 +1124,10 @@ static int si5351_dt_parse(struct i2c_client *client)
|
|||
if (np == NULL)
|
||||
return 0;
|
||||
|
||||
match = of_match_node(si5351_dt_ids, np);
|
||||
if (match == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
|
||||
pdata->variant = (enum si5351_variant)match->data;
|
||||
pdata->clk_xtal = of_clk_get(np, 0);
|
||||
if (!IS_ERR(pdata->clk_xtal))
|
||||
clk_put(pdata->clk_xtal);
|
||||
|
|
@ -1163,7 +1158,7 @@ static int si5351_dt_parse(struct i2c_client *client)
|
|||
pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
|
||||
break;
|
||||
case 1:
|
||||
if (pdata->variant != SI5351_VARIANT_C) {
|
||||
if (variant != SI5351_VARIANT_C) {
|
||||
dev_err(&client->dev,
|
||||
"invalid parent %d for pll %d\n",
|
||||
val, num);
|
||||
|
|
@ -1187,7 +1182,7 @@ static int si5351_dt_parse(struct i2c_client *client)
|
|||
}
|
||||
|
||||
if (num >= 8 ||
|
||||
(pdata->variant == SI5351_VARIANT_A3 && num >= 3)) {
|
||||
(variant == SI5351_VARIANT_A3 && num >= 3)) {
|
||||
dev_err(&client->dev, "invalid clkout %d\n", num);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -1226,7 +1221,7 @@ static int si5351_dt_parse(struct i2c_client *client)
|
|||
SI5351_CLKOUT_SRC_XTAL;
|
||||
break;
|
||||
case 3:
|
||||
if (pdata->variant != SI5351_VARIANT_C) {
|
||||
if (variant != SI5351_VARIANT_C) {
|
||||
dev_err(&client->dev,
|
||||
"invalid parent %d for clkout %d\n",
|
||||
val, num);
|
||||
|
|
@ -1298,7 +1293,7 @@ static int si5351_dt_parse(struct i2c_client *client)
|
|||
return 0;
|
||||
}
|
||||
#else
|
||||
static int si5351_dt_parse(struct i2c_client *client)
|
||||
static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1307,6 +1302,7 @@ static int si5351_dt_parse(struct i2c_client *client)
|
|||
static int si5351_i2c_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
enum si5351_variant variant = (enum si5351_variant)id->driver_data;
|
||||
struct si5351_platform_data *pdata;
|
||||
struct si5351_driver_data *drvdata;
|
||||
struct clk_init_data init;
|
||||
|
|
@ -1315,7 +1311,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
|
|||
u8 num_parents, num_clocks;
|
||||
int ret, n;
|
||||
|
||||
ret = si5351_dt_parse(client);
|
||||
ret = si5351_dt_parse(client, variant);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -1331,7 +1327,7 @@ static int si5351_i2c_probe(struct i2c_client *client,
|
|||
|
||||
i2c_set_clientdata(client, drvdata);
|
||||
drvdata->client = client;
|
||||
drvdata->variant = pdata->variant;
|
||||
drvdata->variant = variant;
|
||||
drvdata->pxtal = pdata->clk_xtal;
|
||||
drvdata->pclkin = pdata->clk_clkin;
|
||||
|
||||
|
|
@ -1568,10 +1564,10 @@ static int si5351_i2c_probe(struct i2c_client *client,
|
|||
}
|
||||
|
||||
static const struct i2c_device_id si5351_i2c_ids[] = {
|
||||
{ "si5351a", 0 },
|
||||
{ "si5351a-msop", 0 },
|
||||
{ "si5351b", 0 },
|
||||
{ "si5351c", 0 },
|
||||
{ "si5351a", SI5351_VARIANT_A },
|
||||
{ "si5351a-msop", SI5351_VARIANT_A3 },
|
||||
{ "si5351b", SI5351_VARIANT_B },
|
||||
{ "si5351c", SI5351_VARIANT_C },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
|
||||
|
|
|
|||
|
|
@ -153,4 +153,18 @@
|
|||
#define SI5351_XTAL_ENABLE (1<<6)
|
||||
#define SI5351_MULTISYNTH_ENABLE (1<<4)
|
||||
|
||||
/**
|
||||
* enum si5351_variant - SiLabs Si5351 chip variant
|
||||
* @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
|
||||
* @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
|
||||
* @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
|
||||
* @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
|
||||
*/
|
||||
enum si5351_variant {
|
||||
SI5351_VARIANT_A = 1,
|
||||
SI5351_VARIANT_A3 = 2,
|
||||
SI5351_VARIANT_B = 3,
|
||||
SI5351_VARIANT_C = 4,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -575,16 +575,19 @@ struct clk_hw *__clk_get_hw(struct clk *clk)
|
|||
{
|
||||
return !clk ? NULL : clk->hw;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_get_hw);
|
||||
|
||||
u8 __clk_get_num_parents(struct clk *clk)
|
||||
{
|
||||
return !clk ? 0 : clk->num_parents;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_get_num_parents);
|
||||
|
||||
struct clk *__clk_get_parent(struct clk *clk)
|
||||
{
|
||||
return !clk ? NULL : clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_get_parent);
|
||||
|
||||
struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
|
||||
{
|
||||
|
|
@ -598,6 +601,7 @@ struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
|
|||
else
|
||||
return clk->parents[index];
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_parent_by_index);
|
||||
|
||||
unsigned int __clk_get_enable_count(struct clk *clk)
|
||||
{
|
||||
|
|
@ -629,6 +633,7 @@ unsigned long __clk_get_rate(struct clk *clk)
|
|||
out:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_get_rate);
|
||||
|
||||
unsigned long __clk_get_accuracy(struct clk *clk)
|
||||
{
|
||||
|
|
@ -685,6 +690,7 @@ bool __clk_is_enabled(struct clk *clk)
|
|||
out:
|
||||
return !!ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_is_enabled);
|
||||
|
||||
static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
|
||||
{
|
||||
|
|
@ -776,6 +782,7 @@ long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
return best;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
|
||||
|
||||
/*** clk api ***/
|
||||
|
||||
|
|
@ -2373,8 +2380,6 @@ struct of_clk_provider {
|
|||
void *data;
|
||||
};
|
||||
|
||||
extern struct of_device_id __clk_of_table[];
|
||||
|
||||
static const struct of_device_id __clk_of_table_sentinel
|
||||
__used __section(__clk_of_table_end);
|
||||
|
||||
|
|
@ -2534,7 +2539,7 @@ void __init of_clk_init(const struct of_device_id *matches)
|
|||
struct device_node *np;
|
||||
|
||||
if (!matches)
|
||||
matches = __clk_of_table;
|
||||
matches = &__clk_of_table;
|
||||
|
||||
for_each_matching_node_and_match(np, matches, &match) {
|
||||
of_clk_init_cb_t clk_init_cb = match->data;
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
|
||||
|
||||
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o
|
||||
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o
|
||||
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o
|
||||
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
|
||||
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
|
||||
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o
|
||||
clk-qcom-y += clk-regmap.o
|
||||
clk-qcom-y += clk-pll.o
|
||||
clk-qcom-y += clk-rcg.o
|
||||
clk-qcom-y += clk-rcg2.o
|
||||
clk-qcom-y += clk-branch.o
|
||||
clk-qcom-y += reset.o
|
||||
|
||||
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
|
||||
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
|
||||
|
|
|
|||
|
|
@ -375,7 +375,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
|||
break;
|
||||
default:
|
||||
break;
|
||||
};
|
||||
}
|
||||
|
||||
/* Set new configuration. */
|
||||
__raw_writel(con1, pll->con_reg + 0x4);
|
||||
|
|
|
|||
|
|
@ -875,7 +875,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
|
|||
if (!clk_data)
|
||||
return;
|
||||
|
||||
clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
|
||||
clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks)
|
||||
goto free_clkdata;
|
||||
|
||||
|
|
|
|||
11
drivers/clk/ti/Makefile
Normal file
11
drivers/clk/ti/Makefile
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
ifneq ($(CONFIG_OF),)
|
||||
obj-y += clk.o autoidle.o clockdomain.o
|
||||
clk-common = dpll.o composite.o divider.o gate.o \
|
||||
fixed-factor.o mux.o apll.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
|
||||
obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o
|
||||
obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o
|
||||
endif
|
||||
223
drivers/clk/ti/apll.c
Normal file
223
drivers/clk/ti/apll.c
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* OMAP APLL clock support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* J Keerthy <j-keerthy@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#define APLL_FORCE_LOCK 0x1
|
||||
#define APLL_AUTO_IDLE 0x2
|
||||
#define MAX_APLL_WAIT_TRIES 1000000
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
static int dra7_apll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
int r = 0, i = 0;
|
||||
struct dpll_data *ad;
|
||||
const char *clk_name;
|
||||
u8 state = 1;
|
||||
u32 v;
|
||||
|
||||
ad = clk->dpll_data;
|
||||
if (!ad)
|
||||
return -EINVAL;
|
||||
|
||||
clk_name = __clk_get_name(clk->hw.clk);
|
||||
|
||||
state <<= __ffs(ad->idlest_mask);
|
||||
|
||||
/* Check is already locked */
|
||||
v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
|
||||
|
||||
if ((v & ad->idlest_mask) == state)
|
||||
return r;
|
||||
|
||||
v = ti_clk_ll_ops->clk_readl(ad->control_reg);
|
||||
v &= ~ad->enable_mask;
|
||||
v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
|
||||
ti_clk_ll_ops->clk_writel(v, ad->control_reg);
|
||||
|
||||
state <<= __ffs(ad->idlest_mask);
|
||||
|
||||
while (1) {
|
||||
v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
|
||||
if ((v & ad->idlest_mask) == state)
|
||||
break;
|
||||
if (i > MAX_APLL_WAIT_TRIES)
|
||||
break;
|
||||
i++;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (i == MAX_APLL_WAIT_TRIES) {
|
||||
pr_warn("clock: %s failed transition to '%s'\n",
|
||||
clk_name, (state) ? "locked" : "bypassed");
|
||||
} else {
|
||||
pr_debug("clock: %s transition to '%s' in %d loops\n",
|
||||
clk_name, (state) ? "locked" : "bypassed", i);
|
||||
|
||||
r = 0;
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static void dra7_apll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
struct dpll_data *ad;
|
||||
u8 state = 1;
|
||||
u32 v;
|
||||
|
||||
ad = clk->dpll_data;
|
||||
|
||||
state <<= __ffs(ad->idlest_mask);
|
||||
|
||||
v = ti_clk_ll_ops->clk_readl(ad->control_reg);
|
||||
v &= ~ad->enable_mask;
|
||||
v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
|
||||
ti_clk_ll_ops->clk_writel(v, ad->control_reg);
|
||||
}
|
||||
|
||||
static int dra7_apll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
struct dpll_data *ad;
|
||||
u32 v;
|
||||
|
||||
ad = clk->dpll_data;
|
||||
|
||||
v = ti_clk_ll_ops->clk_readl(ad->control_reg);
|
||||
v &= ad->enable_mask;
|
||||
|
||||
v >>= __ffs(ad->enable_mask);
|
||||
|
||||
return v == APLL_AUTO_IDLE ? 0 : 1;
|
||||
}
|
||||
|
||||
static u8 dra7_init_apll_parent(struct clk_hw *hw)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops apll_ck_ops = {
|
||||
.enable = &dra7_apll_enable,
|
||||
.disable = &dra7_apll_disable,
|
||||
.is_enabled = &dra7_apll_is_enabled,
|
||||
.get_parent = &dra7_init_apll_parent,
|
||||
};
|
||||
|
||||
static void __init omap_clk_register_apll(struct clk_hw *hw,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
|
||||
struct dpll_data *ad = clk_hw->dpll_data;
|
||||
struct clk *clk;
|
||||
|
||||
ad->clk_ref = of_clk_get(node, 0);
|
||||
ad->clk_bypass = of_clk_get(node, 1);
|
||||
|
||||
if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) {
|
||||
pr_debug("clk-ref or clk-bypass for %s not ready, retry\n",
|
||||
node->name);
|
||||
if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
|
||||
return;
|
||||
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw->dpll_data);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
static void __init of_dra7_apll_setup(struct device_node *node)
|
||||
{
|
||||
struct dpll_data *ad = NULL;
|
||||
struct clk_hw_omap *clk_hw = NULL;
|
||||
struct clk_init_data *init = NULL;
|
||||
const char **parent_names = NULL;
|
||||
int i;
|
||||
|
||||
ad = kzalloc(sizeof(*ad), GFP_KERNEL);
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
init = kzalloc(sizeof(*init), GFP_KERNEL);
|
||||
if (!ad || !clk_hw || !init)
|
||||
goto cleanup;
|
||||
|
||||
clk_hw->dpll_data = ad;
|
||||
clk_hw->hw.init = init;
|
||||
clk_hw->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
init->name = node->name;
|
||||
init->ops = &apll_ck_ops;
|
||||
|
||||
init->num_parents = of_clk_get_parent_count(node);
|
||||
if (init->num_parents < 1) {
|
||||
pr_err("dra7 apll %s must have parent(s)\n", node->name);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
|
||||
if (!parent_names)
|
||||
goto cleanup;
|
||||
|
||||
for (i = 0; i < init->num_parents; i++)
|
||||
parent_names[i] = of_clk_get_parent_name(node, i);
|
||||
|
||||
init->parent_names = parent_names;
|
||||
|
||||
ad->control_reg = ti_clk_get_reg_addr(node, 0);
|
||||
ad->idlest_reg = ti_clk_get_reg_addr(node, 1);
|
||||
|
||||
if (!ad->control_reg || !ad->idlest_reg)
|
||||
goto cleanup;
|
||||
|
||||
ad->idlest_mask = 0x1;
|
||||
ad->enable_mask = 0x3;
|
||||
|
||||
omap_clk_register_apll(&clk_hw->hw, node);
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
kfree(parent_names);
|
||||
kfree(ad);
|
||||
kfree(clk_hw);
|
||||
kfree(init);
|
||||
}
|
||||
CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
|
||||
133
drivers/clk/ti/autoidle.c
Normal file
133
drivers/clk/ti/autoidle.c
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* TI clock autoidle support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
struct clk_ti_autoidle {
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
u8 flags;
|
||||
const char *name;
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
#define AUTOIDLE_LOW 0x1
|
||||
|
||||
static LIST_HEAD(autoidle_clks);
|
||||
|
||||
static void ti_allow_autoidle(struct clk_ti_autoidle *clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = ti_clk_ll_ops->clk_readl(clk->reg);
|
||||
|
||||
if (clk->flags & AUTOIDLE_LOW)
|
||||
val &= ~(1 << clk->shift);
|
||||
else
|
||||
val |= (1 << clk->shift);
|
||||
|
||||
ti_clk_ll_ops->clk_writel(val, clk->reg);
|
||||
}
|
||||
|
||||
static void ti_deny_autoidle(struct clk_ti_autoidle *clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = ti_clk_ll_ops->clk_readl(clk->reg);
|
||||
|
||||
if (clk->flags & AUTOIDLE_LOW)
|
||||
val |= (1 << clk->shift);
|
||||
else
|
||||
val &= ~(1 << clk->shift);
|
||||
|
||||
ti_clk_ll_ops->clk_writel(val, clk->reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_ti_clk_allow_autoidle_all - enable autoidle for all clocks
|
||||
*
|
||||
* Enables hardware autoidle for all registered DT clocks, which have
|
||||
* the feature.
|
||||
*/
|
||||
void of_ti_clk_allow_autoidle_all(void)
|
||||
{
|
||||
struct clk_ti_autoidle *c;
|
||||
|
||||
list_for_each_entry(c, &autoidle_clks, node)
|
||||
ti_allow_autoidle(c);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_ti_clk_deny_autoidle_all - disable autoidle for all clocks
|
||||
*
|
||||
* Disables hardware autoidle for all registered DT clocks, which have
|
||||
* the feature.
|
||||
*/
|
||||
void of_ti_clk_deny_autoidle_all(void)
|
||||
{
|
||||
struct clk_ti_autoidle *c;
|
||||
|
||||
list_for_each_entry(c, &autoidle_clks, node)
|
||||
ti_deny_autoidle(c);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_ti_clk_autoidle_setup - sets up hardware autoidle for a clock
|
||||
* @node: pointer to the clock device node
|
||||
*
|
||||
* Checks if a clock has hardware autoidle support or not (check
|
||||
* for presence of 'ti,autoidle-shift' property in the device tree
|
||||
* node) and sets up the hardware autoidle feature for the clock
|
||||
* if available. If autoidle is available, the clock is also added
|
||||
* to the autoidle list for later processing. Returns 0 on success,
|
||||
* negative error value on failure.
|
||||
*/
|
||||
int __init of_ti_clk_autoidle_setup(struct device_node *node)
|
||||
{
|
||||
u32 shift;
|
||||
struct clk_ti_autoidle *clk;
|
||||
|
||||
/* Check if this clock has autoidle support or not */
|
||||
if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
|
||||
return 0;
|
||||
|
||||
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
||||
|
||||
if (!clk)
|
||||
return -ENOMEM;
|
||||
|
||||
clk->shift = shift;
|
||||
clk->name = node->name;
|
||||
clk->reg = ti_clk_get_reg_addr(node, 0);
|
||||
|
||||
if (!clk->reg) {
|
||||
kfree(clk);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(node, "ti,invert-autoidle-bit"))
|
||||
clk->flags |= AUTOIDLE_LOW;
|
||||
|
||||
list_add(&clk->node, &autoidle_clks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
161
drivers/clk/ti/clk-33xx.c
Normal file
161
drivers/clk/ti/clk-33xx.c
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* AM33XX Clock init
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc
|
||||
* Tero Kristo (t-kristo@ti.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
static struct ti_dt_clk am33xx_clks[] = {
|
||||
DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
|
||||
DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
|
||||
DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
|
||||
DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
|
||||
DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
|
||||
DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
|
||||
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
|
||||
DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
|
||||
DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
|
||||
DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
|
||||
DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
|
||||
DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
|
||||
DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
|
||||
DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
|
||||
DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
|
||||
DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
|
||||
DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
|
||||
DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
|
||||
DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
|
||||
DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
|
||||
DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
|
||||
DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
|
||||
DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
|
||||
DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
|
||||
DT_CLK(NULL, "mmu_fck", "mmu_fck"),
|
||||
DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
|
||||
DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
|
||||
DT_CLK(NULL, "sha0_fck", "sha0_fck"),
|
||||
DT_CLK(NULL, "aes0_fck", "aes0_fck"),
|
||||
DT_CLK(NULL, "rng_fck", "rng_fck"),
|
||||
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
|
||||
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
|
||||
DT_CLK(NULL, "timer3_fck", "timer3_fck"),
|
||||
DT_CLK(NULL, "timer4_fck", "timer4_fck"),
|
||||
DT_CLK(NULL, "timer5_fck", "timer5_fck"),
|
||||
DT_CLK(NULL, "timer6_fck", "timer6_fck"),
|
||||
DT_CLK(NULL, "timer7_fck", "timer7_fck"),
|
||||
DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
|
||||
DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
|
||||
DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
|
||||
DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
|
||||
DT_CLK(NULL, "l3_gclk", "l3_gclk"),
|
||||
DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
|
||||
DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
|
||||
DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
|
||||
DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
|
||||
DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
|
||||
DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
|
||||
DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
|
||||
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
|
||||
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
|
||||
DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
|
||||
DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
|
||||
DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
|
||||
DT_CLK(NULL, "mmc_clk", "mmc_clk"),
|
||||
DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
|
||||
DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
|
||||
DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
|
||||
DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
|
||||
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
|
||||
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
|
||||
DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
|
||||
DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
|
||||
DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
|
||||
DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
|
||||
DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
|
||||
DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
|
||||
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
|
||||
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
|
||||
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static const char *enable_init_clks[] = {
|
||||
"dpll_ddr_m2_ck",
|
||||
"dpll_mpu_m2_ck",
|
||||
"l3_gclk",
|
||||
"l4hs_gclk",
|
||||
"l4fw_gclk",
|
||||
"l4ls_gclk",
|
||||
/* Required for external peripherals like, Audio codecs */
|
||||
"clkout2_ck",
|
||||
};
|
||||
|
||||
int __init am33xx_dt_clk_init(void)
|
||||
{
|
||||
struct clk *clk1, *clk2;
|
||||
|
||||
ti_dt_clocks_register(am33xx_clks);
|
||||
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
||||
omap2_clk_enable_init_clocks(enable_init_clks,
|
||||
ARRAY_SIZE(enable_init_clks));
|
||||
|
||||
/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
|
||||
* physically present, in such a case HWMOD enabling of
|
||||
* clock would be failure with default parent. And timer
|
||||
* probe thinks clock is already enabled, this leads to
|
||||
* crash upon accessing timer 3 & 6 registers in probe.
|
||||
* Fix by setting parent of both these timers to master
|
||||
* oscillator clock.
|
||||
*/
|
||||
|
||||
clk1 = clk_get_sys(NULL, "sys_clkin_ck");
|
||||
clk2 = clk_get_sys(NULL, "timer3_fck");
|
||||
clk_set_parent(clk2, clk1);
|
||||
|
||||
clk2 = clk_get_sys(NULL, "timer6_fck");
|
||||
clk_set_parent(clk2, clk1);
|
||||
/*
|
||||
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
|
||||
* the design/spec, so as a result, for example, timer which supposed
|
||||
* to get expired @60Sec, but will expire somewhere ~@40Sec, which is
|
||||
* not expected by any use-case, so change WDT1 clock source to PRCM
|
||||
* 32KHz clock.
|
||||
*/
|
||||
clk1 = clk_get_sys(NULL, "wdt1_fck");
|
||||
clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
|
||||
clk_set_parent(clk1, clk2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
401
drivers/clk/ti/clk-3xxx.c
Normal file
401
drivers/clk/ti/clk-3xxx.c
Normal file
|
|
@ -0,0 +1,401 @@
|
|||
/*
|
||||
* OMAP3 Clock init
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc
|
||||
* Tero Kristo (t-kristo@ti.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
|
||||
static struct ti_dt_clk omap3xxx_clks[] = {
|
||||
DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
|
||||
DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
|
||||
DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
|
||||
DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
|
||||
DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
|
||||
DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
|
||||
DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
|
||||
DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
|
||||
DT_CLK("twl", "fck", "osc_sys_ck"),
|
||||
DT_CLK(NULL, "sys_ck", "sys_ck"),
|
||||
DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
|
||||
DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
|
||||
DT_CLK(NULL, "sys_altclk", "sys_altclk"),
|
||||
DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
|
||||
DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
|
||||
DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
|
||||
DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
|
||||
DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
|
||||
DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
|
||||
DT_CLK(NULL, "core_ck", "core_ck"),
|
||||
DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
|
||||
DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
|
||||
DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
|
||||
DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
|
||||
DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
|
||||
DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
|
||||
DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
|
||||
DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
|
||||
DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
|
||||
DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
|
||||
DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
|
||||
DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
|
||||
DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
|
||||
DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
|
||||
DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
|
||||
DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
|
||||
DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
|
||||
DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
|
||||
DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
|
||||
DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
|
||||
DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
|
||||
DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
|
||||
DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
|
||||
DT_CLK(NULL, "corex2_fck", "corex2_fck"),
|
||||
DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
|
||||
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
|
||||
DT_CLK(NULL, "arm_fck", "arm_fck"),
|
||||
DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
|
||||
DT_CLK(NULL, "l3_ick", "l3_ick"),
|
||||
DT_CLK(NULL, "l4_ick", "l4_ick"),
|
||||
DT_CLK(NULL, "rm_ick", "rm_ick"),
|
||||
DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
|
||||
DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
|
||||
DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
|
||||
DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
|
||||
DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
|
||||
DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
|
||||
DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
|
||||
DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
|
||||
DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
|
||||
DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
|
||||
DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
|
||||
DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
|
||||
DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
|
||||
DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
|
||||
DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
|
||||
DT_CLK(NULL, "uart2_fck", "uart2_fck"),
|
||||
DT_CLK(NULL, "uart1_fck", "uart1_fck"),
|
||||
DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
|
||||
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
|
||||
DT_CLK(NULL, "hdq_fck", "hdq_fck"),
|
||||
DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
|
||||
DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
|
||||
DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
|
||||
DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
|
||||
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
|
||||
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
|
||||
DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
|
||||
DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
|
||||
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
|
||||
DT_CLK(NULL, "hdq_ick", "hdq_ick"),
|
||||
DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
|
||||
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
|
||||
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
|
||||
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
|
||||
DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
|
||||
DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
|
||||
DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
|
||||
DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
|
||||
DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
|
||||
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
|
||||
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
|
||||
DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
|
||||
DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
|
||||
DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
|
||||
DT_CLK(NULL, "uart2_ick", "uart2_ick"),
|
||||
DT_CLK(NULL, "uart1_ick", "uart1_ick"),
|
||||
DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
|
||||
DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
|
||||
DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
|
||||
DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
|
||||
DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
|
||||
DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
|
||||
DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
|
||||
DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
|
||||
DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
|
||||
DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "dummy_ck"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "dummy_ck"),
|
||||
DT_CLK(NULL, "xclk60mhsp1_ck", "dummy_ck"),
|
||||
DT_CLK(NULL, "xclk60mhsp2_ck", "dummy_ck"),
|
||||
DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
|
||||
DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
|
||||
DT_CLK(NULL, "aes2_ick", "aes2_ick"),
|
||||
DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
|
||||
DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
|
||||
DT_CLK(NULL, "sha12_ick", "sha12_ick"),
|
||||
DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
|
||||
DT_CLK("omap_wdt", "ick", "wdt2_ick"),
|
||||
DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
|
||||
DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
|
||||
DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
|
||||
DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
|
||||
DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
|
||||
DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
|
||||
DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
|
||||
DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
|
||||
DT_CLK(NULL, "uart3_fck", "uart3_fck"),
|
||||
DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
|
||||
DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
|
||||
DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
|
||||
DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
|
||||
DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
|
||||
DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
|
||||
DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
|
||||
DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
|
||||
DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
|
||||
DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
|
||||
DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
|
||||
DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
|
||||
DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
|
||||
DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
|
||||
DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
|
||||
DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
|
||||
DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
|
||||
DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
|
||||
DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
|
||||
DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
|
||||
DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
|
||||
DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
|
||||
DT_CLK(NULL, "uart3_ick", "uart3_ick"),
|
||||
DT_CLK(NULL, "uart4_ick", "uart4_ick"),
|
||||
DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
|
||||
DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
|
||||
DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
|
||||
DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
|
||||
DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
|
||||
DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
|
||||
DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
|
||||
DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
|
||||
DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
|
||||
DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
|
||||
DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
|
||||
DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
|
||||
DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
|
||||
DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
|
||||
DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
|
||||
DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
|
||||
DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
|
||||
DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
|
||||
DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
|
||||
DT_CLK(NULL, "pclk_fck", "pclk_fck"),
|
||||
DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
|
||||
DT_CLK(NULL, "atclk_fck", "atclk_fck"),
|
||||
DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
|
||||
DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
|
||||
DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
|
||||
DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
|
||||
DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
|
||||
DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
|
||||
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
|
||||
DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
|
||||
DT_CLK(NULL, "aes1_ick", "aes1_ick"),
|
||||
DT_CLK("omap_rng", "ick", "rng_ick"),
|
||||
DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
|
||||
DT_CLK(NULL, "sha11_ick", "sha11_ick"),
|
||||
DT_CLK(NULL, "des1_ick", "des1_ick"),
|
||||
DT_CLK(NULL, "cam_mclk", "cam_mclk"),
|
||||
DT_CLK(NULL, "cam_ick", "cam_ick"),
|
||||
DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
|
||||
DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
|
||||
DT_CLK(NULL, "pka_ick", "pka_ick"),
|
||||
DT_CLK(NULL, "icr_ick", "icr_ick"),
|
||||
DT_CLK("omap-aes", "ick", "aes2_ick"),
|
||||
DT_CLK("omap-sham", "ick", "sha12_ick"),
|
||||
DT_CLK(NULL, "des2_ick", "des2_ick"),
|
||||
DT_CLK(NULL, "mspro_ick", "mspro_ick"),
|
||||
DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
|
||||
DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
|
||||
DT_CLK(NULL, "sr1_fck", "sr1_fck"),
|
||||
DT_CLK(NULL, "sr2_fck", "sr2_fck"),
|
||||
DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
|
||||
DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
|
||||
DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
|
||||
DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
|
||||
DT_CLK(NULL, "iva2_ck", "iva2_ck"),
|
||||
DT_CLK(NULL, "modem_fck", "modem_fck"),
|
||||
DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
|
||||
DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
|
||||
DT_CLK(NULL, "mspro_fck", "mspro_fck"),
|
||||
DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
|
||||
DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
|
||||
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
|
||||
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
|
||||
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
|
||||
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
|
||||
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
|
||||
DT_CLK(NULL, "usim_fck", "usim_fck"),
|
||||
DT_CLK(NULL, "usim_ick", "usim_ick"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static struct ti_dt_clk omap3430es1_clks[] = {
|
||||
DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
|
||||
DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
|
||||
DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
|
||||
DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
|
||||
DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
|
||||
DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
|
||||
DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
|
||||
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
|
||||
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
|
||||
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
|
||||
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
|
||||
DT_CLK(NULL, "fac_ick", "fac_ick"),
|
||||
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
|
||||
DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
|
||||
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
|
||||
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
|
||||
DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
|
||||
DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
|
||||
DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
|
||||
DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
|
||||
DT_CLK(NULL, "sgx_fck", "sgx_fck"),
|
||||
DT_CLK(NULL, "sgx_ick", "sgx_ick"),
|
||||
DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
|
||||
DT_CLK(NULL, "ts_fck", "ts_fck"),
|
||||
DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
|
||||
DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
|
||||
DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
|
||||
DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
|
||||
DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
|
||||
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
|
||||
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
|
||||
DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
|
||||
DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
|
||||
DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
|
||||
DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static struct ti_dt_clk am35xx_clks[] = {
|
||||
DT_CLK(NULL, "ipss_ick", "ipss_ick"),
|
||||
DT_CLK(NULL, "rmii_ck", "rmii_ck"),
|
||||
DT_CLK(NULL, "pclk_ck", "pclk_ck"),
|
||||
DT_CLK(NULL, "emac_ick", "emac_ick"),
|
||||
DT_CLK(NULL, "emac_fck", "emac_fck"),
|
||||
DT_CLK("davinci_emac.0", NULL, "emac_ick"),
|
||||
DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
|
||||
DT_CLK("vpfe-capture", "master", "vpfe_ick"),
|
||||
DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
|
||||
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
|
||||
DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
|
||||
DT_CLK(NULL, "hecc_ck", "hecc_ck"),
|
||||
DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
|
||||
DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static struct ti_dt_clk omap36xx_clks[] = {
|
||||
DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
|
||||
DT_CLK(NULL, "uart4_fck", "uart4_fck"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
static const char *enable_init_clks[] = {
|
||||
"sdrc_ick",
|
||||
"gpmc_fck",
|
||||
"omapctrl_ick",
|
||||
};
|
||||
|
||||
enum {
|
||||
OMAP3_SOC_AM35XX,
|
||||
OMAP3_SOC_OMAP3430_ES1,
|
||||
OMAP3_SOC_OMAP3430_ES2_PLUS,
|
||||
OMAP3_SOC_OMAP3630,
|
||||
OMAP3_SOC_TI81XX,
|
||||
};
|
||||
|
||||
static int __init omap3xxx_dt_clk_init(int soc_type)
|
||||
{
|
||||
if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
|
||||
soc_type == OMAP3_SOC_OMAP3430_ES1 ||
|
||||
soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
|
||||
ti_dt_clocks_register(omap3xxx_clks);
|
||||
|
||||
if (soc_type == OMAP3_SOC_AM35XX)
|
||||
ti_dt_clocks_register(am35xx_clks);
|
||||
|
||||
if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
|
||||
soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
|
||||
ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
|
||||
|
||||
if (soc_type == OMAP3_SOC_OMAP3430_ES1)
|
||||
ti_dt_clocks_register(omap3430es1_clks);
|
||||
|
||||
if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
|
||||
soc_type == OMAP3_SOC_OMAP3630)
|
||||
ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
|
||||
|
||||
if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
|
||||
soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
|
||||
soc_type == OMAP3_SOC_OMAP3630)
|
||||
ti_dt_clocks_register(omap34xx_omap36xx_clks);
|
||||
|
||||
if (soc_type == OMAP3_SOC_OMAP3630)
|
||||
ti_dt_clocks_register(omap36xx_clks);
|
||||
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
||||
omap2_clk_enable_init_clocks(enable_init_clks,
|
||||
ARRAY_SIZE(enable_init_clks));
|
||||
|
||||
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
|
||||
(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
|
||||
(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
|
||||
(clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
|
||||
(clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
|
||||
|
||||
if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
|
||||
omap3_clk_lock_dpll5();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init omap3430_dt_clk_init(void)
|
||||
{
|
||||
return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
|
||||
}
|
||||
|
||||
int __init omap3630_dt_clk_init(void)
|
||||
{
|
||||
return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
|
||||
}
|
||||
|
||||
int __init am35xx_dt_clk_init(void)
|
||||
{
|
||||
return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
|
||||
}
|
||||
|
||||
int __init ti81xx_dt_clk_init(void)
|
||||
{
|
||||
return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX);
|
||||
}
|
||||
118
drivers/clk/ti/clk-43xx.c
Normal file
118
drivers/clk/ti/clk-43xx.c
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* AM43XX Clock init
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc
|
||||
* Tero Kristo (t-kristo@ti.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
static struct ti_dt_clk am43xx_clks[] = {
|
||||
DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
|
||||
DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
|
||||
DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
|
||||
DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
|
||||
DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
|
||||
DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
|
||||
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
|
||||
DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
|
||||
DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
|
||||
DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
|
||||
DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
|
||||
DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
|
||||
DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
|
||||
DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
|
||||
DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
|
||||
DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
|
||||
DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
|
||||
DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
|
||||
DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
|
||||
DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
|
||||
DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
|
||||
DT_CLK(NULL, "sha0_fck", "sha0_fck"),
|
||||
DT_CLK(NULL, "aes0_fck", "aes0_fck"),
|
||||
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
|
||||
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
|
||||
DT_CLK(NULL, "timer3_fck", "timer3_fck"),
|
||||
DT_CLK(NULL, "timer4_fck", "timer4_fck"),
|
||||
DT_CLK(NULL, "timer5_fck", "timer5_fck"),
|
||||
DT_CLK(NULL, "timer6_fck", "timer6_fck"),
|
||||
DT_CLK(NULL, "timer7_fck", "timer7_fck"),
|
||||
DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
|
||||
DT_CLK(NULL, "l3_gclk", "l3_gclk"),
|
||||
DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
|
||||
DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
|
||||
DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
|
||||
DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
|
||||
DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
|
||||
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
|
||||
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
|
||||
DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
|
||||
DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
|
||||
DT_CLK(NULL, "mmc_clk", "mmc_clk"),
|
||||
DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
|
||||
DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
|
||||
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
|
||||
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK(NULL, "sysclk_div", "sysclk_div"),
|
||||
DT_CLK(NULL, "disp_clk", "disp_clk"),
|
||||
DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
|
||||
DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
|
||||
DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
|
||||
DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
|
||||
DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
|
||||
DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
|
||||
DT_CLK(NULL, "timer8_fck", "timer8_fck"),
|
||||
DT_CLK(NULL, "timer9_fck", "timer9_fck"),
|
||||
DT_CLK(NULL, "timer10_fck", "timer10_fck"),
|
||||
DT_CLK(NULL, "timer11_fck", "timer11_fck"),
|
||||
DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
|
||||
DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
|
||||
DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
|
||||
DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
|
||||
DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
|
||||
DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
|
||||
DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
|
||||
DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
|
||||
DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
int __init am43xx_dt_clk_init(void)
|
||||
{
|
||||
ti_dt_clocks_register(am43xx_clks);
|
||||
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
||||
return 0;
|
||||
}
|
||||
316
drivers/clk/ti/clk-44xx.c
Normal file
316
drivers/clk/ti/clk-44xx.c
Normal file
|
|
@ -0,0 +1,316 @@
|
|||
/*
|
||||
* OMAP4 Clock init
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo (t-kristo@ti.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk-private.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
/*
|
||||
* OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
|
||||
* "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
|
||||
* must be set to 196.608 MHz" and hence, the DPLL locked frequency is
|
||||
* half of this value.
|
||||
*/
|
||||
#define OMAP4_DPLL_ABE_DEFFREQ 98304000
|
||||
|
||||
/*
|
||||
* OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
|
||||
* "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
|
||||
* locked frequency for the USB DPLL is 960MHz.
|
||||
*/
|
||||
#define OMAP4_DPLL_USB_DEFFREQ 960000000
|
||||
|
||||
static struct ti_dt_clk omap44xx_clks[] = {
|
||||
DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
|
||||
DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
|
||||
DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
|
||||
DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
|
||||
DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
|
||||
DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
|
||||
DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
|
||||
DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
|
||||
DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
|
||||
DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
|
||||
DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
|
||||
DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
|
||||
DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
|
||||
DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
|
||||
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
|
||||
DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
|
||||
DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
|
||||
DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
|
||||
DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
|
||||
DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
|
||||
DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
|
||||
DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
|
||||
DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
|
||||
DT_CLK(NULL, "abe_clk", "abe_clk"),
|
||||
DT_CLK(NULL, "aess_fclk", "aess_fclk"),
|
||||
DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
|
||||
DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
|
||||
DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
|
||||
DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
|
||||
DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
|
||||
DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
|
||||
DT_CLK(NULL, "div_core_ck", "div_core_ck"),
|
||||
DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
|
||||
DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
|
||||
DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
|
||||
DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
|
||||
DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
|
||||
DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
|
||||
DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
|
||||
DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
|
||||
DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
|
||||
DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
|
||||
DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
|
||||
DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
|
||||
DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
|
||||
DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
|
||||
DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
|
||||
DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
|
||||
DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
|
||||
DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
|
||||
DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
|
||||
DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
|
||||
DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
|
||||
DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
|
||||
DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
|
||||
DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
|
||||
DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
|
||||
DT_CLK("smp_twd", NULL, "mpu_periphclk"),
|
||||
DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
|
||||
DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
|
||||
DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
|
||||
DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
|
||||
DT_CLK(NULL, "aes1_fck", "aes1_fck"),
|
||||
DT_CLK(NULL, "aes2_fck", "aes2_fck"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
|
||||
DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
|
||||
DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
|
||||
DT_CLK(NULL, "dss_fck", "dss_fck"),
|
||||
DT_CLK("omapdss_dss", "ick", "dss_fck"),
|
||||
DT_CLK(NULL, "fdif_fck", "fdif_fck"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
|
||||
DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
|
||||
DT_CLK(NULL, "hsi_fck", "hsi_fck"),
|
||||
DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
|
||||
DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
|
||||
DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
|
||||
DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
|
||||
DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
|
||||
DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
|
||||
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
|
||||
DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
|
||||
DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
|
||||
DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
|
||||
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
|
||||
DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
|
||||
DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
|
||||
DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
|
||||
DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
|
||||
DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
|
||||
DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
|
||||
DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
|
||||
DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
|
||||
DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
|
||||
DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
|
||||
DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
|
||||
DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
|
||||
DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
|
||||
DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
|
||||
DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
|
||||
DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
|
||||
DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
|
||||
DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
|
||||
DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
|
||||
DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
|
||||
DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
|
||||
DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
|
||||
DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
|
||||
DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
|
||||
DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
|
||||
DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
|
||||
DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
|
||||
DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
|
||||
DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
|
||||
DT_CLK(NULL, "usim_ck", "usim_ck"),
|
||||
DT_CLK(NULL, "usim_fclk", "usim_fclk"),
|
||||
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
|
||||
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
|
||||
DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
|
||||
DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
|
||||
DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
|
||||
DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
|
||||
DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
|
||||
DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
|
||||
DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
|
||||
DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
|
||||
DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
|
||||
DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
|
||||
DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
|
||||
DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
|
||||
DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
|
||||
DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
|
||||
DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
|
||||
DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
|
||||
DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
|
||||
DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
|
||||
DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
|
||||
DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
|
||||
DT_CLK("50000000.gpmc", "fck", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart1_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart2_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart3_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart4_ick", "dummy_ck"),
|
||||
DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
|
||||
DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
|
||||
DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
|
||||
DT_CLK("omap_wdt", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
|
||||
DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
|
||||
DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
|
||||
DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
|
||||
DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
|
||||
DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
int __init omap4xxx_dt_clk_init(void)
|
||||
{
|
||||
int rc;
|
||||
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
|
||||
|
||||
ti_dt_clocks_register(omap44xx_clks);
|
||||
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
||||
/*
|
||||
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
|
||||
* domain can transition to retention state when not in use.
|
||||
*/
|
||||
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
|
||||
rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure USB DPLL!\n", __func__);
|
||||
|
||||
/*
|
||||
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
|
||||
* state when turning the ABE clock domain. Workaround this by
|
||||
* locking the ABE DPLL on boot.
|
||||
* Lock the ABE DPLL in any case to avoid issues with audio.
|
||||
*/
|
||||
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
|
||||
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
|
||||
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
|
||||
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
|
||||
if (!rc)
|
||||
rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
255
drivers/clk/ti/clk-54xx.c
Normal file
255
drivers/clk/ti/clk-54xx.c
Normal file
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* OMAP5 Clock init
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo (t-kristo@ti.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk-private.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
|
||||
|
||||
/*
|
||||
* OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
|
||||
* states it must be at 960MHz
|
||||
*/
|
||||
#define OMAP5_DPLL_USB_DEFFREQ 960000000
|
||||
|
||||
static struct ti_dt_clk omap54xx_clks[] = {
|
||||
DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
|
||||
DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
|
||||
DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
|
||||
DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
|
||||
DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
|
||||
DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
|
||||
DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
|
||||
DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
|
||||
DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
|
||||
DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
|
||||
DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
|
||||
DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
|
||||
DT_CLK(NULL, "sys_clkin", "sys_clkin"),
|
||||
DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
|
||||
DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
|
||||
DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
|
||||
DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
|
||||
DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
|
||||
DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
|
||||
DT_CLK(NULL, "abe_clk", "abe_clk"),
|
||||
DT_CLK(NULL, "abe_iclk", "abe_iclk"),
|
||||
DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
|
||||
DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
|
||||
DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
|
||||
DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
|
||||
DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
|
||||
DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
|
||||
DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
|
||||
DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
|
||||
DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
|
||||
DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
|
||||
DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
|
||||
DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
|
||||
DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
|
||||
DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
|
||||
DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
|
||||
DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
|
||||
DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
|
||||
DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
|
||||
DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
|
||||
DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
|
||||
DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
|
||||
DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
|
||||
DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
|
||||
DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
|
||||
DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
|
||||
DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
|
||||
DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
|
||||
DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
|
||||
DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
|
||||
DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
|
||||
DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
|
||||
DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
|
||||
DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
|
||||
DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
|
||||
DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
|
||||
DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
|
||||
DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
|
||||
DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
|
||||
DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
|
||||
DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
|
||||
DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
|
||||
DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
|
||||
DT_CLK(NULL, "aess_fclk", "aess_fclk"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
|
||||
DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
|
||||
DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
|
||||
DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
|
||||
DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
|
||||
DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
|
||||
DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
|
||||
DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
|
||||
DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
|
||||
DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
|
||||
DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
|
||||
DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
|
||||
DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
|
||||
DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
|
||||
DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
|
||||
DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
|
||||
DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
|
||||
DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
|
||||
DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
|
||||
DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
|
||||
DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
|
||||
DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
|
||||
DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
|
||||
DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
|
||||
DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
|
||||
DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
|
||||
DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
|
||||
DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
|
||||
DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart1_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart2_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart3_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart4_ick", "dummy_ck"),
|
||||
DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
|
||||
DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
|
||||
DT_CLK("omap_wdt", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
|
||||
DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
|
||||
DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
|
||||
DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
|
||||
DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
|
||||
DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
|
||||
DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
|
||||
DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
|
||||
DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
|
||||
DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
|
||||
DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
int __init omap5xxx_dt_clk_init(void)
|
||||
{
|
||||
int rc;
|
||||
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
|
||||
|
||||
ti_dt_clocks_register(omap54xx_clks);
|
||||
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
||||
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
|
||||
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
|
||||
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
|
||||
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
|
||||
if (!rc)
|
||||
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
|
||||
|
||||
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
|
||||
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure USB DPLL!\n", __func__);
|
||||
|
||||
usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
|
||||
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
|
||||
if (rc)
|
||||
pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
332
drivers/clk/ti/clk-7xx.c
Normal file
332
drivers/clk/ti/clk-7xx.c
Normal file
|
|
@ -0,0 +1,332 @@
|
|||
/*
|
||||
* DRA7 Clock init
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo (t-kristo@ti.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk-private.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#define DRA7_DPLL_ABE_DEFFREQ 361267200
|
||||
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
|
||||
|
||||
|
||||
static struct ti_dt_clk dra7xx_clks[] = {
|
||||
DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
|
||||
DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
|
||||
DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
|
||||
DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"),
|
||||
DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
|
||||
DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
|
||||
DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
|
||||
DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
|
||||
DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
|
||||
DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
|
||||
DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
|
||||
DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
|
||||
DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
|
||||
DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
|
||||
DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
|
||||
DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
|
||||
DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
|
||||
DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
|
||||
DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
|
||||
DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
|
||||
DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
|
||||
DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
|
||||
DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
|
||||
DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
|
||||
DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
|
||||
DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
|
||||
DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
|
||||
DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
|
||||
DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
|
||||
DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
|
||||
DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
|
||||
DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
|
||||
DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
|
||||
DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
|
||||
DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
|
||||
DT_CLK(NULL, "abe_clk", "abe_clk"),
|
||||
DT_CLK(NULL, "aess_fclk", "aess_fclk"),
|
||||
DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
|
||||
DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
|
||||
DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
|
||||
DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
|
||||
DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
|
||||
DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
|
||||
DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
|
||||
DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
|
||||
DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
|
||||
DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
|
||||
DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
|
||||
DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
|
||||
DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
|
||||
DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
|
||||
DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
|
||||
DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
|
||||
DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
|
||||
DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
|
||||
DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
|
||||
DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
|
||||
DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
|
||||
DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
|
||||
DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
|
||||
DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
|
||||
DT_CLK(NULL, "iva_dclk", "iva_dclk"),
|
||||
DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
|
||||
DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
|
||||
DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
|
||||
DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
|
||||
DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
|
||||
DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
|
||||
DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
|
||||
DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
|
||||
DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
|
||||
DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
|
||||
DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
|
||||
DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
|
||||
DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
|
||||
DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
|
||||
DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
|
||||
DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
|
||||
DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
|
||||
DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
|
||||
DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
|
||||
DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
|
||||
DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
|
||||
DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
|
||||
DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
|
||||
DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
|
||||
DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
|
||||
DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
|
||||
DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
|
||||
DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
|
||||
DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
|
||||
DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
|
||||
DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
|
||||
DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
|
||||
DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
|
||||
DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
|
||||
DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
|
||||
DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
|
||||
DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
|
||||
DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
|
||||
DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
|
||||
DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
|
||||
DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
|
||||
DT_CLK(NULL, "eve_clk", "eve_clk"),
|
||||
DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
|
||||
DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
|
||||
DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
|
||||
DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
|
||||
DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
|
||||
DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
|
||||
DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
|
||||
DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
|
||||
DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
|
||||
DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
|
||||
DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
|
||||
DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
|
||||
DT_CLK(NULL, "mlb_clk", "mlb_clk"),
|
||||
DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
|
||||
DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
|
||||
DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
|
||||
DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
|
||||
DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
|
||||
DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
|
||||
DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
|
||||
DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
|
||||
DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
|
||||
DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
|
||||
DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
|
||||
DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
|
||||
DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
|
||||
DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
|
||||
DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
|
||||
DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
|
||||
DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
|
||||
DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
|
||||
DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
|
||||
DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
|
||||
DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
|
||||
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
|
||||
DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
|
||||
DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
|
||||
DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
|
||||
DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
|
||||
DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
|
||||
DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
|
||||
DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
|
||||
DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"),
|
||||
DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
|
||||
DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
|
||||
DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
|
||||
DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
|
||||
DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
|
||||
DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
|
||||
DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
|
||||
DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
|
||||
DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
|
||||
DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
|
||||
DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
|
||||
DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
|
||||
DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
|
||||
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
|
||||
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
|
||||
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
|
||||
DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
|
||||
DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
|
||||
DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
|
||||
DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
|
||||
DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
|
||||
DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
|
||||
DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
|
||||
DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
|
||||
DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
|
||||
DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
|
||||
DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
|
||||
DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
|
||||
DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
|
||||
DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
|
||||
DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
|
||||
DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
|
||||
DT_CLK(NULL, "gpmc_ck", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
|
||||
DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart1_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart2_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart3_ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "uart4_ick", "dummy_ck"),
|
||||
DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
|
||||
DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
|
||||
DT_CLK("omap_wdt", "ick", "dummy_ck"),
|
||||
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
|
||||
DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
|
||||
DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
|
||||
DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
|
||||
DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
|
||||
DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
|
||||
DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
|
||||
DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
|
||||
DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
|
||||
DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
|
||||
DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
|
||||
DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
int __init dra7xx_dt_clk_init(void)
|
||||
{
|
||||
int rc;
|
||||
struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
|
||||
|
||||
ti_dt_clocks_register(dra7xx_clks);
|
||||
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
||||
abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
|
||||
sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
|
||||
dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
|
||||
|
||||
rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
|
||||
if (!rc)
|
||||
rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
|
||||
|
||||
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
|
||||
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
|
||||
|
||||
return rc;
|
||||
}
|
||||
167
drivers/clk/ti/clk.c
Normal file
167
drivers/clk/ti/clk.c
Normal file
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
* TI clock support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
static int ti_dt_clk_memmap_index;
|
||||
struct ti_clk_ll_ops *ti_clk_ll_ops;
|
||||
|
||||
/**
|
||||
* ti_dt_clocks_register - register DT alias clocks during boot
|
||||
* @oclks: list of clocks to register
|
||||
*
|
||||
* Register alias or non-standard DT clock entries during boot. By
|
||||
* default, DT clocks are found based on their node name. If any
|
||||
* additional con-id / dev-id -> clock mapping is required, use this
|
||||
* function to list these.
|
||||
*/
|
||||
void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
|
||||
{
|
||||
struct ti_dt_clk *c;
|
||||
struct device_node *node;
|
||||
struct clk *clk;
|
||||
struct of_phandle_args clkspec;
|
||||
|
||||
for (c = oclks; c->node_name != NULL; c++) {
|
||||
node = of_find_node_by_name(NULL, c->node_name);
|
||||
clkspec.np = node;
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
c->lk.clk = clk;
|
||||
clkdev_add(&c->lk);
|
||||
} else {
|
||||
pr_warn("failed to lookup clock node %s\n",
|
||||
c->node_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
struct clk_init_item {
|
||||
struct device_node *node;
|
||||
struct clk_hw *hw;
|
||||
ti_of_clk_init_cb_t func;
|
||||
struct list_head link;
|
||||
};
|
||||
|
||||
static LIST_HEAD(retry_list);
|
||||
|
||||
/**
|
||||
* ti_clk_retry_init - retries a failed clock init at later phase
|
||||
* @node: device not for the clock
|
||||
* @hw: partially initialized clk_hw struct for the clock
|
||||
* @func: init function to be called for the clock
|
||||
*
|
||||
* Adds a failed clock init to the retry list. The retry list is parsed
|
||||
* once all the other clocks have been initialized.
|
||||
*/
|
||||
int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
|
||||
ti_of_clk_init_cb_t func)
|
||||
{
|
||||
struct clk_init_item *retry;
|
||||
|
||||
pr_debug("%s: adding to retry list...\n", node->name);
|
||||
retry = kzalloc(sizeof(*retry), GFP_KERNEL);
|
||||
if (!retry)
|
||||
return -ENOMEM;
|
||||
|
||||
retry->node = node;
|
||||
retry->func = func;
|
||||
retry->hw = hw;
|
||||
list_add(&retry->link, &retry_list);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ti_clk_get_reg_addr - get register address for a clock register
|
||||
* @node: device node for the clock
|
||||
* @index: register index from the clock node
|
||||
*
|
||||
* Builds clock register address from device tree information. This
|
||||
* is a struct of type clk_omap_reg.
|
||||
*/
|
||||
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
|
||||
{
|
||||
struct clk_omap_reg *reg;
|
||||
u32 val;
|
||||
u32 tmp;
|
||||
|
||||
reg = (struct clk_omap_reg *)&tmp;
|
||||
reg->index = ti_dt_clk_memmap_index;
|
||||
|
||||
if (of_property_read_u32_index(node, "reg", index, &val)) {
|
||||
pr_err("%s must have reg[%d]!\n", node->name, index);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
reg->offset = val;
|
||||
|
||||
return (void __iomem *)tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* ti_dt_clk_init_provider - init master clock provider
|
||||
* @parent: master node
|
||||
* @index: internal index for clk_reg_ops
|
||||
*
|
||||
* Initializes a master clock IP block and its child clock nodes.
|
||||
* Regmap is provided for accessing the register space for the
|
||||
* IP block and all the clocks under it.
|
||||
*/
|
||||
void ti_dt_clk_init_provider(struct device_node *parent, int index)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device_node *np;
|
||||
struct device_node *clocks;
|
||||
of_clk_init_cb_t clk_init_cb;
|
||||
struct clk_init_item *retry;
|
||||
struct clk_init_item *tmp;
|
||||
|
||||
ti_dt_clk_memmap_index = index;
|
||||
|
||||
/* get clocks for this parent */
|
||||
clocks = of_get_child_by_name(parent, "clocks");
|
||||
if (!clocks) {
|
||||
pr_err("%s missing 'clocks' child node.\n", parent->name);
|
||||
return;
|
||||
}
|
||||
|
||||
for_each_child_of_node(clocks, np) {
|
||||
match = of_match_node(&__clk_of_table, np);
|
||||
if (!match)
|
||||
continue;
|
||||
clk_init_cb = (of_clk_init_cb_t)match->data;
|
||||
pr_debug("%s: initializing: %s\n", __func__, np->name);
|
||||
clk_init_cb(np);
|
||||
}
|
||||
|
||||
list_for_each_entry_safe(retry, tmp, &retry_list, link) {
|
||||
pr_debug("retry-init: %s\n", retry->node->name);
|
||||
retry->func(retry->hw, retry->node);
|
||||
list_del(&retry->link);
|
||||
kfree(retry);
|
||||
}
|
||||
}
|
||||
70
drivers/clk/ti/clockdomain.c
Normal file
70
drivers/clk/ti/clockdomain.c
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* OMAP clockdomain support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
static void __init of_ti_clockdomain_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw *clk_hw;
|
||||
const char *clkdm_name = node->name;
|
||||
int i;
|
||||
int num_clks;
|
||||
|
||||
num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
clk = of_clk_get(node, i);
|
||||
if (__clk_get_flags(clk) & CLK_IS_BASIC) {
|
||||
pr_warn("can't setup clkdm for basic clk %s\n",
|
||||
__clk_get_name(clk));
|
||||
continue;
|
||||
}
|
||||
clk_hw = __clk_get_hw(clk);
|
||||
to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
|
||||
omap2_init_clk_clkdm(clk_hw);
|
||||
}
|
||||
}
|
||||
|
||||
static struct of_device_id ti_clkdm_match_table[] __initdata = {
|
||||
{ .compatible = "ti,clockdomain" },
|
||||
{ }
|
||||
};
|
||||
|
||||
/**
|
||||
* ti_dt_clockdomains_setup - setup device tree clockdomains
|
||||
*
|
||||
* Initializes clockdomain nodes for a SoC. This parses through all the
|
||||
* nodes with compatible = "ti,clockdomain", and add the clockdomain
|
||||
* info for all the clocks listed under these. This function shall be
|
||||
* called after rest of the DT clock init has completed and all
|
||||
* clock nodes have been registered.
|
||||
*/
|
||||
void __init ti_dt_clockdomains_setup(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
for_each_matching_node(np, ti_clkdm_match_table) {
|
||||
of_ti_clockdomain_setup(np);
|
||||
}
|
||||
}
|
||||
269
drivers/clk/ti/composite.c
Normal file
269
drivers/clk/ti/composite.c
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* TI composite clock support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
|
||||
}
|
||||
|
||||
static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct clk_ops ti_composite_divider_ops = {
|
||||
.recalc_rate = &ti_composite_recalc_rate,
|
||||
.round_rate = &ti_composite_round_rate,
|
||||
.set_rate = &ti_composite_set_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops ti_composite_gate_ops = {
|
||||
.enable = &omap2_dflt_clk_enable,
|
||||
.disable = &omap2_dflt_clk_disable,
|
||||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
||||
};
|
||||
|
||||
struct component_clk {
|
||||
int num_parents;
|
||||
const char **parent_names;
|
||||
struct device_node *node;
|
||||
int type;
|
||||
struct clk_hw *hw;
|
||||
struct list_head link;
|
||||
};
|
||||
|
||||
static const char * __initconst component_clk_types[] = {
|
||||
"gate", "divider", "mux"
|
||||
};
|
||||
|
||||
static LIST_HEAD(component_clks);
|
||||
|
||||
static struct device_node *_get_component_node(struct device_node *node, int i)
|
||||
{
|
||||
int rc;
|
||||
struct of_phandle_args clkspec;
|
||||
|
||||
rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
|
||||
&clkspec);
|
||||
if (rc)
|
||||
return NULL;
|
||||
|
||||
return clkspec.np;
|
||||
}
|
||||
|
||||
static struct component_clk *_lookup_component(struct device_node *node)
|
||||
{
|
||||
struct component_clk *comp;
|
||||
|
||||
list_for_each_entry(comp, &component_clks, link) {
|
||||
if (comp->node == node)
|
||||
return comp;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct clk_hw_omap_comp {
|
||||
struct clk_hw hw;
|
||||
struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
|
||||
struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
|
||||
};
|
||||
|
||||
static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
|
||||
{
|
||||
if (!clk)
|
||||
return NULL;
|
||||
|
||||
if (!clk->comp_clks[idx])
|
||||
return NULL;
|
||||
|
||||
return clk->comp_clks[idx]->hw;
|
||||
}
|
||||
|
||||
#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
|
||||
|
||||
static void __init ti_clk_register_composite(struct clk_hw *hw,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
|
||||
struct component_clk *comp;
|
||||
int num_parents = 0;
|
||||
const char **parent_names = NULL;
|
||||
int i;
|
||||
|
||||
/* Check for presence of each component clock */
|
||||
for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
|
||||
if (!cclk->comp_nodes[i])
|
||||
continue;
|
||||
|
||||
comp = _lookup_component(cclk->comp_nodes[i]);
|
||||
if (!comp) {
|
||||
pr_debug("component %s not ready for %s, retry\n",
|
||||
cclk->comp_nodes[i]->name, node->name);
|
||||
if (!ti_clk_retry_init(node, hw,
|
||||
ti_clk_register_composite))
|
||||
return;
|
||||
|
||||
goto cleanup;
|
||||
}
|
||||
if (cclk->comp_clks[comp->type] != NULL) {
|
||||
pr_err("duplicate component types for %s (%s)!\n",
|
||||
node->name, component_clk_types[comp->type]);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cclk->comp_clks[comp->type] = comp;
|
||||
|
||||
/* Mark this node as found */
|
||||
cclk->comp_nodes[i] = NULL;
|
||||
}
|
||||
|
||||
/* All components exists, proceed with registration */
|
||||
for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
|
||||
comp = cclk->comp_clks[i];
|
||||
if (!comp)
|
||||
continue;
|
||||
if (comp->num_parents) {
|
||||
num_parents = comp->num_parents;
|
||||
parent_names = comp->parent_names;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!num_parents) {
|
||||
pr_err("%s: no parents found for %s!\n", __func__, node->name);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
clk = clk_register_composite(NULL, node->name,
|
||||
parent_names, num_parents,
|
||||
_get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
|
||||
&ti_clk_mux_ops,
|
||||
_get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
|
||||
&ti_composite_divider_ops,
|
||||
_get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
|
||||
&ti_composite_gate_ops, 0);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
|
||||
cleanup:
|
||||
/* Free component clock list entries */
|
||||
for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
|
||||
if (!cclk->comp_clks[i])
|
||||
continue;
|
||||
list_del(&cclk->comp_clks[i]->link);
|
||||
kfree(cclk->comp_clks[i]);
|
||||
}
|
||||
|
||||
kfree(cclk);
|
||||
}
|
||||
|
||||
static void __init of_ti_composite_clk_setup(struct device_node *node)
|
||||
{
|
||||
int num_clks;
|
||||
int i;
|
||||
struct clk_hw_omap_comp *cclk;
|
||||
|
||||
/* Number of component clocks to be put inside this clock */
|
||||
num_clks = of_clk_get_parent_count(node);
|
||||
|
||||
if (num_clks < 1) {
|
||||
pr_err("composite clk %s must have component(s)\n", node->name);
|
||||
return;
|
||||
}
|
||||
|
||||
cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
|
||||
if (!cclk)
|
||||
return;
|
||||
|
||||
/* Get device node pointers for each component clock */
|
||||
for (i = 0; i < num_clks; i++)
|
||||
cclk->comp_nodes[i] = _get_component_node(node, i);
|
||||
|
||||
ti_clk_register_composite(&cclk->hw, node);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
|
||||
of_ti_composite_clk_setup);
|
||||
|
||||
/**
|
||||
* ti_clk_add_component - add a component clock to the pool
|
||||
* @node: device node of the component clock
|
||||
* @hw: hardware clock definition for the component clock
|
||||
* @type: type of the component clock
|
||||
*
|
||||
* Adds a component clock to the list of available components, so that
|
||||
* it can be registered by a composite clock.
|
||||
*/
|
||||
int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
|
||||
int type)
|
||||
{
|
||||
int num_parents;
|
||||
const char **parent_names;
|
||||
struct component_clk *clk;
|
||||
int i;
|
||||
|
||||
num_parents = of_clk_get_parent_count(node);
|
||||
|
||||
if (num_parents < 1) {
|
||||
pr_err("component-clock %s must have parent(s)\n", node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
|
||||
if (!parent_names)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < num_parents; i++)
|
||||
parent_names[i] = of_clk_get_parent_name(node, i);
|
||||
|
||||
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
||||
if (!clk) {
|
||||
kfree(parent_names);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
clk->num_parents = num_parents;
|
||||
clk->parent_names = parent_names;
|
||||
clk->hw = hw;
|
||||
clk->node = node;
|
||||
clk->type = type;
|
||||
list_add(&clk->link, &component_clks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
487
drivers/clk/ti/divider.c
Normal file
487
drivers/clk/ti/divider.c
Normal file
|
|
@ -0,0 +1,487 @@
|
|||
/*
|
||||
* TI Divider Clock
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#define div_mask(d) ((1 << ((d)->width)) - 1)
|
||||
|
||||
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
|
||||
{
|
||||
unsigned int maxdiv = 0;
|
||||
const struct clk_div_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->div > maxdiv)
|
||||
maxdiv = clkt->div;
|
||||
return maxdiv;
|
||||
}
|
||||
|
||||
static unsigned int _get_maxdiv(struct clk_divider *divider)
|
||||
{
|
||||
if (divider->flags & CLK_DIVIDER_ONE_BASED)
|
||||
return div_mask(divider);
|
||||
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return 1 << div_mask(divider);
|
||||
if (divider->table)
|
||||
return _get_table_maxdiv(divider->table);
|
||||
return div_mask(divider) + 1;
|
||||
}
|
||||
|
||||
static unsigned int _get_table_div(const struct clk_div_table *table,
|
||||
unsigned int val)
|
||||
{
|
||||
const struct clk_div_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->val == val)
|
||||
return clkt->div;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
|
||||
{
|
||||
if (divider->flags & CLK_DIVIDER_ONE_BASED)
|
||||
return val;
|
||||
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return 1 << val;
|
||||
if (divider->table)
|
||||
return _get_table_div(divider->table, val);
|
||||
return val + 1;
|
||||
}
|
||||
|
||||
static unsigned int _get_table_val(const struct clk_div_table *table,
|
||||
unsigned int div)
|
||||
{
|
||||
const struct clk_div_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->div == div)
|
||||
return clkt->val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int _get_val(struct clk_divider *divider, u8 div)
|
||||
{
|
||||
if (divider->flags & CLK_DIVIDER_ONE_BASED)
|
||||
return div;
|
||||
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return __ffs(div);
|
||||
if (divider->table)
|
||||
return _get_table_val(divider->table, div);
|
||||
return div - 1;
|
||||
}
|
||||
|
||||
static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
unsigned int div, val;
|
||||
|
||||
val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
|
||||
val &= div_mask(divider);
|
||||
|
||||
div = _get_div(divider, val);
|
||||
if (!div) {
|
||||
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
|
||||
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
|
||||
__clk_get_name(hw->clk));
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
/*
|
||||
* The reverse of DIV_ROUND_UP: The maximum number which
|
||||
* divided by m is r
|
||||
*/
|
||||
#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
|
||||
|
||||
static bool _is_valid_table_div(const struct clk_div_table *table,
|
||||
unsigned int div)
|
||||
{
|
||||
const struct clk_div_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->div == div)
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
|
||||
{
|
||||
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return is_power_of_2(div);
|
||||
if (divider->table)
|
||||
return _is_valid_table_div(divider->table, div);
|
||||
return true;
|
||||
}
|
||||
|
||||
static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
int i, bestdiv = 0;
|
||||
unsigned long parent_rate, best = 0, now, maxdiv;
|
||||
unsigned long parent_rate_saved = *best_parent_rate;
|
||||
|
||||
if (!rate)
|
||||
rate = 1;
|
||||
|
||||
maxdiv = _get_maxdiv(divider);
|
||||
|
||||
if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
|
||||
parent_rate = *best_parent_rate;
|
||||
bestdiv = DIV_ROUND_UP(parent_rate, rate);
|
||||
bestdiv = bestdiv == 0 ? 1 : bestdiv;
|
||||
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
|
||||
return bestdiv;
|
||||
}
|
||||
|
||||
/*
|
||||
* The maximum divider we can use without overflowing
|
||||
* unsigned long in rate * i below
|
||||
*/
|
||||
maxdiv = min(ULONG_MAX / rate, maxdiv);
|
||||
|
||||
for (i = 1; i <= maxdiv; i++) {
|
||||
if (!_is_valid_div(divider, i))
|
||||
continue;
|
||||
if (rate * i == parent_rate_saved) {
|
||||
/*
|
||||
* It's the most ideal case if the requested rate can be
|
||||
* divided from parent clock without needing to change
|
||||
* parent rate, so return the divider immediately.
|
||||
*/
|
||||
*best_parent_rate = parent_rate_saved;
|
||||
return i;
|
||||
}
|
||||
parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
|
||||
MULT_ROUND_UP(rate, i));
|
||||
now = parent_rate / i;
|
||||
if (now <= rate && now > best) {
|
||||
bestdiv = i;
|
||||
best = now;
|
||||
*best_parent_rate = parent_rate;
|
||||
}
|
||||
}
|
||||
|
||||
if (!bestdiv) {
|
||||
bestdiv = _get_maxdiv(divider);
|
||||
*best_parent_rate =
|
||||
__clk_round_rate(__clk_get_parent(hw->clk), 1);
|
||||
}
|
||||
|
||||
return bestdiv;
|
||||
}
|
||||
|
||||
static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
int div;
|
||||
div = ti_clk_divider_bestdiv(hw, rate, prate);
|
||||
|
||||
return *prate / div;
|
||||
}
|
||||
|
||||
static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
unsigned int div, value;
|
||||
unsigned long flags = 0;
|
||||
u32 val;
|
||||
|
||||
div = parent_rate / rate;
|
||||
value = _get_val(divider, div);
|
||||
|
||||
if (value > div_mask(divider))
|
||||
value = div_mask(divider);
|
||||
|
||||
if (divider->lock)
|
||||
spin_lock_irqsave(divider->lock, flags);
|
||||
|
||||
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
|
||||
val = div_mask(divider) << (divider->shift + 16);
|
||||
} else {
|
||||
val = ti_clk_ll_ops->clk_readl(divider->reg);
|
||||
val &= ~(div_mask(divider) << divider->shift);
|
||||
}
|
||||
val |= value << divider->shift;
|
||||
ti_clk_ll_ops->clk_writel(val, divider->reg);
|
||||
|
||||
if (divider->lock)
|
||||
spin_unlock_irqrestore(divider->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops ti_clk_divider_ops = {
|
||||
.recalc_rate = ti_clk_divider_recalc_rate,
|
||||
.round_rate = ti_clk_divider_round_rate,
|
||||
.set_rate = ti_clk_divider_set_rate,
|
||||
};
|
||||
|
||||
static struct clk *_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name,
|
||||
unsigned long flags, void __iomem *reg,
|
||||
u8 shift, u8 width, u8 clk_divider_flags,
|
||||
const struct clk_div_table *table,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct clk_divider *div;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
|
||||
if (width + shift > 16) {
|
||||
pr_warn("divider value exceeds LOWORD field\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
/* allocate the divider */
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div) {
|
||||
pr_err("%s: could not allocate divider clk\n", __func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &ti_clk_divider_ops;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
|
||||
/* struct clk_divider assignments */
|
||||
div->reg = reg;
|
||||
div->shift = shift;
|
||||
div->width = width;
|
||||
div->flags = clk_divider_flags;
|
||||
div->lock = lock;
|
||||
div->hw.init = &init;
|
||||
div->table = table;
|
||||
|
||||
/* register the clock */
|
||||
clk = clk_register(dev, &div->hw);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(div);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static struct clk_div_table
|
||||
__init *ti_clk_get_div_table(struct device_node *node)
|
||||
{
|
||||
struct clk_div_table *table;
|
||||
const __be32 *divspec;
|
||||
u32 val;
|
||||
u32 num_div;
|
||||
u32 valid_div;
|
||||
int i;
|
||||
|
||||
divspec = of_get_property(node, "ti,dividers", &num_div);
|
||||
|
||||
if (!divspec)
|
||||
return NULL;
|
||||
|
||||
num_div /= 4;
|
||||
|
||||
valid_div = 0;
|
||||
|
||||
/* Determine required size for divider table */
|
||||
for (i = 0; i < num_div; i++) {
|
||||
of_property_read_u32_index(node, "ti,dividers", i, &val);
|
||||
if (val)
|
||||
valid_div++;
|
||||
}
|
||||
|
||||
if (!valid_div) {
|
||||
pr_err("no valid dividers for %s table\n", node->name);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
|
||||
|
||||
if (!table)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
valid_div = 0;
|
||||
|
||||
for (i = 0; i < num_div; i++) {
|
||||
of_property_read_u32_index(node, "ti,dividers", i, &val);
|
||||
if (val) {
|
||||
table[valid_div].div = val;
|
||||
table[valid_div].val = i;
|
||||
valid_div++;
|
||||
}
|
||||
}
|
||||
|
||||
return table;
|
||||
}
|
||||
|
||||
static int _get_divider_width(struct device_node *node,
|
||||
const struct clk_div_table *table,
|
||||
u8 flags)
|
||||
{
|
||||
u32 min_div;
|
||||
u32 max_div;
|
||||
u32 val = 0;
|
||||
u32 div;
|
||||
|
||||
if (!table) {
|
||||
/* Clk divider table not provided, determine min/max divs */
|
||||
if (of_property_read_u32(node, "ti,min-div", &min_div))
|
||||
min_div = 1;
|
||||
|
||||
if (of_property_read_u32(node, "ti,max-div", &max_div)) {
|
||||
pr_err("no max-div for %s!\n", node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Determine bit width for the field */
|
||||
if (flags & CLK_DIVIDER_ONE_BASED)
|
||||
val = 1;
|
||||
|
||||
div = min_div;
|
||||
|
||||
while (div < max_div) {
|
||||
if (flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
div <<= 1;
|
||||
else
|
||||
div++;
|
||||
val++;
|
||||
}
|
||||
} else {
|
||||
div = 0;
|
||||
|
||||
while (table[div].div) {
|
||||
val = table[div].val;
|
||||
div++;
|
||||
}
|
||||
}
|
||||
|
||||
return fls(val);
|
||||
}
|
||||
|
||||
static int __init ti_clk_divider_populate(struct device_node *node,
|
||||
void __iomem **reg, const struct clk_div_table **table,
|
||||
u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
*reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!*reg)
|
||||
return -EINVAL;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
*shift = val;
|
||||
else
|
||||
*shift = 0;
|
||||
|
||||
*flags = 0;
|
||||
*div_flags = 0;
|
||||
|
||||
if (of_property_read_bool(node, "ti,index-starts-at-one"))
|
||||
*div_flags |= CLK_DIVIDER_ONE_BASED;
|
||||
|
||||
if (of_property_read_bool(node, "ti,index-power-of-two"))
|
||||
*div_flags |= CLK_DIVIDER_POWER_OF_TWO;
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-rate-parent"))
|
||||
*flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
*table = ti_clk_get_div_table(node);
|
||||
|
||||
if (IS_ERR(*table))
|
||||
return PTR_ERR(*table);
|
||||
|
||||
*width = _get_divider_width(node, *table, *div_flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* of_ti_divider_clk_setup - Setup function for simple div rate clock
|
||||
* @node: device node for this clock
|
||||
*
|
||||
* Sets up a basic divider clock.
|
||||
*/
|
||||
static void __init of_ti_divider_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
const char *parent_name;
|
||||
void __iomem *reg;
|
||||
u8 clk_divider_flags = 0;
|
||||
u8 width = 0;
|
||||
u8 shift = 0;
|
||||
const struct clk_div_table *table = NULL;
|
||||
u32 flags = 0;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
|
||||
if (ti_clk_divider_populate(node, ®, &table, &flags,
|
||||
&clk_divider_flags, &width, &shift))
|
||||
goto cleanup;
|
||||
|
||||
clk = _register_divider(NULL, node->name, parent_name, flags, reg,
|
||||
shift, width, clk_divider_flags, table, NULL);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
of_ti_clk_autoidle_setup(node);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(table);
|
||||
}
|
||||
CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
|
||||
|
||||
static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk_divider *div;
|
||||
u32 val;
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return;
|
||||
|
||||
if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
|
||||
&div->flags, &div->width, &div->shift) < 0)
|
||||
goto cleanup;
|
||||
|
||||
if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
kfree(div->table);
|
||||
kfree(div);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
|
||||
of_ti_composite_divider_clk_setup);
|
||||
558
drivers/clk/ti/dpll.c
Normal file
558
drivers/clk/ti/dpll.c
Normal file
|
|
@ -0,0 +1,558 @@
|
|||
/*
|
||||
* OMAP DPLL clock support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define DPLL_HAS_AUTOIDLE 0x1
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
||||
defined(CONFIG_SOC_DRA7XX)
|
||||
static const struct clk_ops dpll_m4xen_ck_ops = {
|
||||
.enable = &omap3_noncore_dpll_enable,
|
||||
.disable = &omap3_noncore_dpll_disable,
|
||||
.recalc_rate = &omap4_dpll_regm4xen_recalc,
|
||||
.round_rate = &omap4_dpll_regm4xen_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct clk_ops dpll_core_ck_ops = {
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static const struct clk_ops omap3_dpll_core_ck_ops = {
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct clk_ops dpll_ck_ops = {
|
||||
.enable = &omap3_noncore_dpll_enable,
|
||||
.disable = &omap3_noncore_dpll_disable,
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
};
|
||||
|
||||
static const struct clk_ops dpll_no_gate_ck_ops = {
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static const struct clk_ops omap3_dpll_ck_ops = {
|
||||
.enable = &omap3_noncore_dpll_enable,
|
||||
.disable = &omap3_noncore_dpll_disable,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops omap3_dpll_per_ck_ops = {
|
||||
.enable = &omap3_noncore_dpll_enable,
|
||||
.disable = &omap3_noncore_dpll_disable,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.set_rate = &omap3_dpll4_set_rate,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct clk_ops dpll_x2_ck_ops = {
|
||||
.recalc_rate = &omap3_clkoutx2_recalc,
|
||||
};
|
||||
|
||||
/**
|
||||
* ti_clk_register_dpll - low level registration of a DPLL clock
|
||||
* @hw: hardware clock definition for the clock
|
||||
* @node: device node for the clock
|
||||
*
|
||||
* Finalizes DPLL registration process. In case a failure (clk-ref or
|
||||
* clk-bypass is missing), the clock is added to retry list and
|
||||
* the initialization is retried on later stage.
|
||||
*/
|
||||
static void __init ti_clk_register_dpll(struct clk_hw *hw,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
|
||||
struct dpll_data *dd = clk_hw->dpll_data;
|
||||
struct clk *clk;
|
||||
|
||||
dd->clk_ref = of_clk_get(node, 0);
|
||||
dd->clk_bypass = of_clk_get(node, 1);
|
||||
|
||||
if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
|
||||
pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
|
||||
node->name);
|
||||
if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
|
||||
return;
|
||||
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/* register the clock */
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
omap2_init_clk_hw_omap_clocks(clk);
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw->dpll_data);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
||||
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
|
||||
/**
|
||||
* ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
|
||||
* @node: device node for this clock
|
||||
* @ops: clk_ops for this clock
|
||||
* @hw_ops: clk_hw_ops for this clock
|
||||
*
|
||||
* Initializes a DPLL x 2 clock from device tree data.
|
||||
*/
|
||||
static void ti_clk_register_dpll_x2(struct device_node *node,
|
||||
const struct clk_ops *ops,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init = { NULL };
|
||||
struct clk_hw_omap *clk_hw;
|
||||
const char *name = node->name;
|
||||
const char *parent_name;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
if (!parent_name) {
|
||||
pr_err("%s must have parent\n", node->name);
|
||||
return;
|
||||
}
|
||||
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
if (!clk_hw)
|
||||
return;
|
||||
|
||||
clk_hw->ops = hw_ops;
|
||||
clk_hw->hw.init = &init;
|
||||
|
||||
init.name = name;
|
||||
init.ops = ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
/* register the clock */
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(clk_hw);
|
||||
} else {
|
||||
omap2_init_clk_hw_omap_clocks(clk);
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* of_ti_dpll_setup - Setup function for OMAP DPLL clocks
|
||||
* @node: device node containing the DPLL info
|
||||
* @ops: ops for the DPLL
|
||||
* @ddt: DPLL data template to use
|
||||
* @init_flags: flags for controlling init types
|
||||
*
|
||||
* Initializes a DPLL clock from device tree data.
|
||||
*/
|
||||
static void __init of_ti_dpll_setup(struct device_node *node,
|
||||
const struct clk_ops *ops,
|
||||
const struct dpll_data *ddt,
|
||||
u8 init_flags)
|
||||
{
|
||||
struct clk_hw_omap *clk_hw = NULL;
|
||||
struct clk_init_data *init = NULL;
|
||||
const char **parent_names = NULL;
|
||||
struct dpll_data *dd = NULL;
|
||||
int i;
|
||||
u8 dpll_mode = 0;
|
||||
|
||||
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
init = kzalloc(sizeof(*init), GFP_KERNEL);
|
||||
if (!dd || !clk_hw || !init)
|
||||
goto cleanup;
|
||||
|
||||
memcpy(dd, ddt, sizeof(*dd));
|
||||
|
||||
clk_hw->dpll_data = dd;
|
||||
clk_hw->ops = &clkhwops_omap3_dpll;
|
||||
clk_hw->hw.init = init;
|
||||
clk_hw->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
init->name = node->name;
|
||||
init->ops = ops;
|
||||
|
||||
init->num_parents = of_clk_get_parent_count(node);
|
||||
if (init->num_parents < 1) {
|
||||
pr_err("%s must have parent(s)\n", node->name);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
|
||||
if (!parent_names)
|
||||
goto cleanup;
|
||||
|
||||
for (i = 0; i < init->num_parents; i++)
|
||||
parent_names[i] = of_clk_get_parent_name(node, i);
|
||||
|
||||
init->parent_names = parent_names;
|
||||
|
||||
dd->control_reg = ti_clk_get_reg_addr(node, 0);
|
||||
dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
|
||||
dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
|
||||
|
||||
if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
|
||||
goto cleanup;
|
||||
|
||||
if (init_flags & DPLL_HAS_AUTOIDLE) {
|
||||
dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
|
||||
if (!dd->autoidle_reg)
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(node, "ti,low-power-stop"))
|
||||
dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
|
||||
|
||||
if (of_property_read_bool(node, "ti,low-power-bypass"))
|
||||
dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
|
||||
|
||||
if (of_property_read_bool(node, "ti,lock"))
|
||||
dpll_mode |= 1 << DPLL_LOCKED;
|
||||
|
||||
if (dpll_mode)
|
||||
dd->modes = dpll_mode;
|
||||
|
||||
ti_clk_register_dpll(&clk_hw->hw, node);
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
kfree(dd);
|
||||
kfree(parent_names);
|
||||
kfree(init);
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
||||
defined(CONFIG_SOC_DRA7XX)
|
||||
static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
|
||||
{
|
||||
ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
|
||||
of_ti_omap4_dpll_x2_setup);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
|
||||
{
|
||||
ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
|
||||
of_ti_am3_dpll_x2_setup);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static void __init of_ti_omap3_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.freqsel_mask = 0xf0,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
|
||||
of_ti_omap3_dpll_setup);
|
||||
|
||||
static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 16,
|
||||
.div1_mask = 0x7f << 8,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.freqsel_mask = 0xf0,
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
|
||||
of_ti_omap3_core_dpll_setup);
|
||||
|
||||
static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1 << 1,
|
||||
.enable_mask = 0x7 << 16,
|
||||
.autoidle_mask = 0x7 << 3,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.freqsel_mask = 0xf00000,
|
||||
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
|
||||
of_ti_omap3_per_dpll_setup);
|
||||
|
||||
static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1 << 1,
|
||||
.enable_mask = 0x7 << 16,
|
||||
.autoidle_mask = 0x7 << 3,
|
||||
.mult_mask = 0xfff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 4095,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.sddiv_mask = 0xff << 24,
|
||||
.dco_mask = 0xe << 20,
|
||||
.flags = DPLL_J_TYPE,
|
||||
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
|
||||
of_ti_omap3_per_jtype_dpll_setup);
|
||||
#endif
|
||||
|
||||
static void __init of_ti_omap4_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
|
||||
of_ti_omap4_dpll_setup);
|
||||
|
||||
static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
|
||||
of_ti_omap4_core_dpll_setup);
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
||||
defined(CONFIG_SOC_DRA7XX)
|
||||
static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.m4xen_mask = 0x800,
|
||||
.lpmode_mask = 1 << 10,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
|
||||
of_ti_omap4_m4xen_dpll_setup);
|
||||
|
||||
static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0xfff << 8,
|
||||
.div1_mask = 0xff,
|
||||
.max_multiplier = 4095,
|
||||
.max_divider = 256,
|
||||
.min_divider = 1,
|
||||
.sddiv_mask = 0xff << 24,
|
||||
.flags = DPLL_J_TYPE,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
|
||||
of_ti_omap4_jtype_dpll_setup);
|
||||
#endif
|
||||
|
||||
static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
|
||||
of_ti_am3_no_gate_dpll_setup);
|
||||
|
||||
static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 4095,
|
||||
.max_divider = 256,
|
||||
.min_divider = 2,
|
||||
.flags = DPLL_J_TYPE,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
|
||||
of_ti_am3_jtype_dpll_setup);
|
||||
|
||||
static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.flags = DPLL_J_TYPE,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
|
||||
"ti,am3-dpll-no-gate-j-type-clock",
|
||||
of_ti_am3_no_gate_jtype_dpll_setup);
|
||||
|
||||
static void __init of_ti_am3_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
|
||||
|
||||
static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
|
||||
{
|
||||
const struct dpll_data dd = {
|
||||
.idlest_mask = 0x1,
|
||||
.enable_mask = 0x7,
|
||||
.autoidle_mask = 0x7,
|
||||
.mult_mask = 0x7ff << 8,
|
||||
.div1_mask = 0x7f,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
};
|
||||
|
||||
of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
|
||||
of_ti_am3_core_dpll_setup);
|
||||
66
drivers/clk/ti/fixed-factor.c
Normal file
66
drivers/clk/ti/fixed-factor.c
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* TI Fixed Factor Clock
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
/**
|
||||
* of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
|
||||
* @node: device node for this clock
|
||||
*
|
||||
* Sets up a simple fixed factor clock based on device tree info.
|
||||
*/
|
||||
static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
const char *clk_name = node->name;
|
||||
const char *parent_name;
|
||||
u32 div, mult;
|
||||
u32 flags = 0;
|
||||
|
||||
if (of_property_read_u32(node, "ti,clock-div", &div)) {
|
||||
pr_err("%s must have a clock-div property\n", node->name);
|
||||
return;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
|
||||
pr_err("%s must have a clock-mult property\n", node->name);
|
||||
return;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-rate-parent"))
|
||||
flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
|
||||
mult, div);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
of_ti_clk_autoidle_setup(node);
|
||||
}
|
||||
}
|
||||
CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
|
||||
of_ti_fixed_factor_clk_setup);
|
||||
249
drivers/clk/ti/gate.c
Normal file
249
drivers/clk/ti/gate.c
Normal file
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* OMAP gate clock support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
|
||||
|
||||
static const struct clk_ops omap_gate_clkdm_clk_ops = {
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable = &omap2_clkops_enable_clkdm,
|
||||
.disable = &omap2_clkops_disable_clkdm,
|
||||
};
|
||||
|
||||
static const struct clk_ops omap_gate_clk_ops = {
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable = &omap2_dflt_clk_enable,
|
||||
.disable = &omap2_dflt_clk_disable,
|
||||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
||||
};
|
||||
|
||||
static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
|
||||
.disable = &omap2_dflt_clk_disable,
|
||||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
||||
};
|
||||
|
||||
/**
|
||||
* omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
|
||||
* from HSDivider PWRDN problem Implements Errata ID: i556.
|
||||
* @clk: DPLL output struct clk
|
||||
*
|
||||
* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
|
||||
* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
|
||||
* valueafter their respective PWRDN bits are set. Any dummy write
|
||||
* (Any other value different from the Read value) to the
|
||||
* corresponding CM_CLKSEL register will refresh the dividers.
|
||||
*/
|
||||
static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
|
||||
{
|
||||
struct clk_divider *parent;
|
||||
struct clk_hw *parent_hw;
|
||||
u32 dummy_v, orig_v;
|
||||
int ret;
|
||||
|
||||
/* Clear PWRDN bit of HSDIVIDER */
|
||||
ret = omap2_dflt_clk_enable(clk);
|
||||
|
||||
/* Parent is the x2 node, get parent of parent for the m2 div */
|
||||
parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
|
||||
parent = to_clk_divider(parent_hw);
|
||||
|
||||
/* Restore the dividers */
|
||||
if (!ret) {
|
||||
orig_v = ti_clk_ll_ops->clk_readl(parent->reg);
|
||||
dummy_v = orig_v;
|
||||
|
||||
/* Write any other value different from the Read value */
|
||||
dummy_v ^= (1 << parent->shift);
|
||||
ti_clk_ll_ops->clk_writel(dummy_v, parent->reg);
|
||||
|
||||
/* Write the original divider */
|
||||
ti_clk_ll_ops->clk_writel(orig_v, parent->reg);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __init _of_ti_gate_clk_setup(struct device_node *node,
|
||||
const struct clk_ops *ops,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init = { NULL };
|
||||
struct clk_hw_omap *clk_hw;
|
||||
const char *clk_name = node->name;
|
||||
const char *parent_name;
|
||||
u32 val;
|
||||
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
if (!clk_hw)
|
||||
return;
|
||||
|
||||
clk_hw->hw.init = &init;
|
||||
|
||||
init.name = clk_name;
|
||||
init.ops = ops;
|
||||
|
||||
if (ops != &omap_gate_clkdm_clk_ops) {
|
||||
clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!clk_hw->enable_reg)
|
||||
goto cleanup;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
clk_hw->enable_bit = val;
|
||||
}
|
||||
|
||||
clk_hw->ops = hw_ops;
|
||||
|
||||
clk_hw->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
if (of_clk_get_parent_count(node) != 1) {
|
||||
pr_err("%s must have 1 parent\n", clk_name);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-rate-parent"))
|
||||
init.flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-bit-to-disable"))
|
||||
clk_hw->flags |= INVERT_ENABLE;
|
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
static void __init
|
||||
_of_ti_composite_gate_clk_setup(struct device_node *node,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
{
|
||||
struct clk_hw_omap *gate;
|
||||
u32 val = 0;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
return;
|
||||
|
||||
gate->enable_reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!gate->enable_reg)
|
||||
goto cleanup;
|
||||
|
||||
of_property_read_u32(node, "ti,bit-shift", &val);
|
||||
|
||||
gate->enable_bit = val;
|
||||
gate->ops = hw_ops;
|
||||
gate->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
kfree(gate);
|
||||
}
|
||||
|
||||
static void __init
|
||||
of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_composite_gate_clk_setup(node, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
|
||||
of_ti_composite_no_wait_gate_clk_setup);
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
|
||||
of_ti_composite_interface_clk_setup);
|
||||
#endif
|
||||
|
||||
static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
|
||||
of_ti_composite_gate_clk_setup);
|
||||
|
||||
|
||||
static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
|
||||
of_ti_clkdm_gate_clk_setup);
|
||||
|
||||
static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
|
||||
&clkhwops_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
|
||||
of_ti_hsdiv_gate_clk_setup);
|
||||
|
||||
static void __init of_ti_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup)
|
||||
|
||||
static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
|
||||
of_ti_wait_gate_clk_setup);
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
|
||||
&clkhwops_am35xx_ipss_module_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
|
||||
of_ti_am35xx_gate_clk_setup);
|
||||
|
||||
static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
|
||||
&clkhwops_omap3430es2_dss_usbhost_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
|
||||
of_ti_dss_gate_clk_setup);
|
||||
#endif
|
||||
125
drivers/clk/ti/interface.c
Normal file
125
drivers/clk/ti/interface.c
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* OMAP interface clock support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
static const struct clk_ops ti_interface_clk_ops = {
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable = &omap2_dflt_clk_enable,
|
||||
.disable = &omap2_dflt_clk_disable,
|
||||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
||||
};
|
||||
|
||||
static void __init _of_ti_interface_clk_setup(struct device_node *node,
|
||||
const struct clk_hw_omap_ops *ops)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init = { NULL };
|
||||
struct clk_hw_omap *clk_hw;
|
||||
const char *parent_name;
|
||||
u32 val;
|
||||
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
if (!clk_hw)
|
||||
return;
|
||||
|
||||
clk_hw->hw.init = &init;
|
||||
clk_hw->ops = ops;
|
||||
clk_hw->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!clk_hw->enable_reg)
|
||||
goto cleanup;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
clk_hw->enable_bit = val;
|
||||
|
||||
init.name = node->name;
|
||||
init.ops = &ti_interface_clk_ops;
|
||||
init.flags = 0;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
if (!parent_name) {
|
||||
pr_err("%s must have a parent\n", node->name);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
init.num_parents = 1;
|
||||
init.parent_names = &parent_name;
|
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
omap2_init_clk_hw_omap_clocks(clk);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
static void __init of_ti_interface_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_interface_clk_setup(node, &clkhwops_iclk_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_interface_clk, "ti,omap3-interface-clock",
|
||||
of_ti_interface_clk_setup);
|
||||
|
||||
static void __init of_ti_no_wait_interface_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_interface_clk_setup(node, &clkhwops_iclk);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
|
||||
of_ti_no_wait_interface_clk_setup);
|
||||
|
||||
static void __init of_ti_hsotgusb_interface_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_interface_clk_setup(node,
|
||||
&clkhwops_omap3430es2_iclk_hsotgusb_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
|
||||
of_ti_hsotgusb_interface_clk_setup);
|
||||
|
||||
static void __init of_ti_dss_interface_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_interface_clk_setup(node,
|
||||
&clkhwops_omap3430es2_iclk_dss_usbhost_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_dss_interface_clk, "ti,omap3-dss-interface-clock",
|
||||
of_ti_dss_interface_clk_setup);
|
||||
|
||||
static void __init of_ti_ssi_interface_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
|
||||
of_ti_ssi_interface_clk_setup);
|
||||
|
||||
static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node)
|
||||
{
|
||||
_of_ti_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock",
|
||||
of_ti_am35xx_interface_clk_setup);
|
||||
246
drivers/clk/ti/mux.c
Normal file
246
drivers/clk/ti/mux.c
Normal file
|
|
@ -0,0 +1,246 @@
|
|||
/*
|
||||
* TI Multiplexer Clock
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
int num_parents = __clk_get_num_parents(hw->clk);
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* FIXME need a mux-specific flag to determine if val is bitwise or
|
||||
* numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
|
||||
* from 0x1 to 0x7 (index starts at one)
|
||||
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
|
||||
* val = 0x4 really means "bit 2, index starts at bit 0"
|
||||
*/
|
||||
val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
|
||||
val &= mux->mask;
|
||||
|
||||
if (mux->table) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_parents; i++)
|
||||
if (mux->table[i] == val)
|
||||
return i;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_BIT))
|
||||
val = ffs(val) - 1;
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_ONE))
|
||||
val--;
|
||||
|
||||
if (val >= num_parents)
|
||||
return -EINVAL;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
u32 val;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (mux->table) {
|
||||
index = mux->table[index];
|
||||
} else {
|
||||
if (mux->flags & CLK_MUX_INDEX_BIT)
|
||||
index = (1 << ffs(index));
|
||||
|
||||
if (mux->flags & CLK_MUX_INDEX_ONE)
|
||||
index++;
|
||||
}
|
||||
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
|
||||
if (mux->flags & CLK_MUX_HIWORD_MASK) {
|
||||
val = mux->mask << (mux->shift + 16);
|
||||
} else {
|
||||
val = ti_clk_ll_ops->clk_readl(mux->reg);
|
||||
val &= ~(mux->mask << mux->shift);
|
||||
}
|
||||
val |= index << mux->shift;
|
||||
ti_clk_ll_ops->clk_writel(val, mux->reg);
|
||||
|
||||
if (mux->lock)
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops ti_clk_mux_ops = {
|
||||
.get_parent = ti_clk_mux_get_parent,
|
||||
.set_parent = ti_clk_mux_set_parent,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
};
|
||||
|
||||
static struct clk *_register_mux(struct device *dev, const char *name,
|
||||
const char **parent_names, u8 num_parents,
|
||||
unsigned long flags, void __iomem *reg,
|
||||
u8 shift, u32 mask, u8 clk_mux_flags,
|
||||
u32 *table, spinlock_t *lock)
|
||||
{
|
||||
struct clk_mux *mux;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
/* allocate the mux */
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux) {
|
||||
pr_err("%s: could not allocate mux clk\n", __func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &ti_clk_mux_ops;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
|
||||
/* struct clk_mux assignments */
|
||||
mux->reg = reg;
|
||||
mux->shift = shift;
|
||||
mux->mask = mask;
|
||||
mux->flags = clk_mux_flags;
|
||||
mux->lock = lock;
|
||||
mux->table = table;
|
||||
mux->hw.init = &init;
|
||||
|
||||
clk = clk_register(dev, &mux->hw);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(mux);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/**
|
||||
* of_mux_clk_setup - Setup function for simple mux rate clock
|
||||
* @node: DT node for the clock
|
||||
*
|
||||
* Sets up a basic clock multiplexer.
|
||||
*/
|
||||
static void of_mux_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
void __iomem *reg;
|
||||
int num_parents;
|
||||
const char **parent_names;
|
||||
int i;
|
||||
u8 clk_mux_flags = 0;
|
||||
u32 mask = 0;
|
||||
u32 shift = 0;
|
||||
u32 flags = 0;
|
||||
|
||||
num_parents = of_clk_get_parent_count(node);
|
||||
if (num_parents < 2) {
|
||||
pr_err("mux-clock %s must have parents\n", node->name);
|
||||
return;
|
||||
}
|
||||
parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
|
||||
if (!parent_names)
|
||||
goto cleanup;
|
||||
|
||||
for (i = 0; i < num_parents; i++)
|
||||
parent_names[i] = of_clk_get_parent_name(node, i);
|
||||
|
||||
reg = ti_clk_get_reg_addr(node, 0);
|
||||
|
||||
if (!reg)
|
||||
goto cleanup;
|
||||
|
||||
of_property_read_u32(node, "ti,bit-shift", &shift);
|
||||
|
||||
if (of_property_read_bool(node, "ti,index-starts-at-one"))
|
||||
clk_mux_flags |= CLK_MUX_INDEX_ONE;
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-rate-parent"))
|
||||
flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
/* Generate bit-mask based on parent info */
|
||||
mask = num_parents;
|
||||
if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
|
||||
mask--;
|
||||
|
||||
mask = (1 << fls(mask)) - 1;
|
||||
|
||||
clk = _register_mux(NULL, node->name, parent_names, num_parents, flags,
|
||||
reg, shift, mask, clk_mux_flags, NULL, NULL);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
|
||||
cleanup:
|
||||
kfree(parent_names);
|
||||
}
|
||||
CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
|
||||
|
||||
static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk_mux *mux;
|
||||
int num_parents;
|
||||
u32 val;
|
||||
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
return;
|
||||
|
||||
mux->reg = ti_clk_get_reg_addr(node, 0);
|
||||
|
||||
if (!mux->reg)
|
||||
goto cleanup;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
mux->shift = val;
|
||||
|
||||
if (of_property_read_bool(node, "ti,index-starts-at-one"))
|
||||
mux->flags |= CLK_MUX_INDEX_ONE;
|
||||
|
||||
num_parents = of_clk_get_parent_count(node);
|
||||
|
||||
if (num_parents < 2) {
|
||||
pr_err("%s must have parents\n", node->name);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
mux->mask = num_parents - 1;
|
||||
mux->mask = (1 << fls(mux->mask)) - 1;
|
||||
|
||||
if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
kfree(mux);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
|
||||
of_ti_composite_mux_clk_setup);
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
#define EXTPCLK_CLK_SRC 40
|
||||
#define HDMI_CLK_SRC 41
|
||||
#define VSYNC_CLK_SRC 42
|
||||
#define RBCPR_CLK_SRC 43
|
||||
#define MMSS_RBCPR_CLK_SRC 43
|
||||
#define CAMSS_CCI_CCI_AHB_CLK 44
|
||||
#define CAMSS_CCI_CCI_CLK 45
|
||||
#define CAMSS_CSI0_AHB_CLK 46
|
||||
|
|
|
|||
|
|
@ -488,6 +488,8 @@ struct clk_onecell_data {
|
|||
unsigned int clk_num;
|
||||
};
|
||||
|
||||
extern struct of_device_id __clk_of_table;
|
||||
|
||||
#define CLK_OF_DECLARE(name, compat, fn) \
|
||||
static const struct of_device_id __clk_of_table_##name \
|
||||
__used __section(__clk_of_table) \
|
||||
|
|
|
|||
298
include/linux/clk/ti.h
Normal file
298
include/linux/clk/ti.h
Normal file
|
|
@ -0,0 +1,298 @@
|
|||
/*
|
||||
* TI clock drivers support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __LINUX_CLK_TI_H__
|
||||
#define __LINUX_CLK_TI_H__
|
||||
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
/**
|
||||
* struct dpll_data - DPLL registers and integration data
|
||||
* @mult_div1_reg: register containing the DPLL M and N bitfields
|
||||
* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
|
||||
* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
|
||||
* @clk_bypass: struct clk pointer to the clock's bypass clock input
|
||||
* @clk_ref: struct clk pointer to the clock's reference clock input
|
||||
* @control_reg: register containing the DPLL mode bitfield
|
||||
* @enable_mask: mask of the DPLL mode bitfield in @control_reg
|
||||
* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
|
||||
* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
|
||||
* @last_rounded_m4xen: cache of the last M4X result of
|
||||
* omap4_dpll_regm4xen_round_rate()
|
||||
* @last_rounded_lpmode: cache of the last lpmode result of
|
||||
* omap4_dpll_lpmode_recalc()
|
||||
* @max_multiplier: maximum valid non-bypass multiplier value (actual)
|
||||
* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
|
||||
* @min_divider: minimum valid non-bypass divider value (actual)
|
||||
* @max_divider: maximum valid non-bypass divider value (actual)
|
||||
* @modes: possible values of @enable_mask
|
||||
* @autoidle_reg: register containing the DPLL autoidle mode bitfield
|
||||
* @idlest_reg: register containing the DPLL idle status bitfield
|
||||
* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
|
||||
* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
|
||||
* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
|
||||
* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
|
||||
* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
|
||||
* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
|
||||
* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
|
||||
* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
|
||||
* @flags: DPLL type/features (see below)
|
||||
*
|
||||
* Possible values for @flags:
|
||||
* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
|
||||
*
|
||||
* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
|
||||
*
|
||||
* XXX Some DPLLs have multiple bypass inputs, so it's not technically
|
||||
* correct to only have one @clk_bypass pointer.
|
||||
*
|
||||
* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
|
||||
* @last_rounded_n) should be separated from the runtime-fixed fields
|
||||
* and placed into a different structure, so that the runtime-fixed data
|
||||
* can be placed into read-only space.
|
||||
*/
|
||||
struct dpll_data {
|
||||
void __iomem *mult_div1_reg;
|
||||
u32 mult_mask;
|
||||
u32 div1_mask;
|
||||
struct clk *clk_bypass;
|
||||
struct clk *clk_ref;
|
||||
void __iomem *control_reg;
|
||||
u32 enable_mask;
|
||||
unsigned long last_rounded_rate;
|
||||
u16 last_rounded_m;
|
||||
u8 last_rounded_m4xen;
|
||||
u8 last_rounded_lpmode;
|
||||
u16 max_multiplier;
|
||||
u8 last_rounded_n;
|
||||
u8 min_divider;
|
||||
u16 max_divider;
|
||||
u8 modes;
|
||||
void __iomem *autoidle_reg;
|
||||
void __iomem *idlest_reg;
|
||||
u32 autoidle_mask;
|
||||
u32 freqsel_mask;
|
||||
u32 idlest_mask;
|
||||
u32 dco_mask;
|
||||
u32 sddiv_mask;
|
||||
u32 lpmode_mask;
|
||||
u32 m4xen_mask;
|
||||
u8 auto_recal_bit;
|
||||
u8 recal_en_bit;
|
||||
u8 recal_st_bit;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
struct clk_hw_omap_ops;
|
||||
|
||||
/**
|
||||
* struct clk_hw_omap - OMAP struct clk
|
||||
* @node: list_head connecting this clock into the full clock list
|
||||
* @enable_reg: register to write to enable the clock (see @enable_bit)
|
||||
* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
|
||||
* @flags: see "struct clk.flags possibilities" above
|
||||
* @clksel_reg: for clksel clks, register va containing src/divisor select
|
||||
* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
|
||||
* @clksel: for clksel clks, pointer to struct clksel for this clock
|
||||
* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
|
||||
* @clkdm_name: clockdomain name that this clock is contained in
|
||||
* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
|
||||
* @ops: clock ops for this clock
|
||||
*/
|
||||
struct clk_hw_omap {
|
||||
struct clk_hw hw;
|
||||
struct list_head node;
|
||||
unsigned long fixed_rate;
|
||||
u8 fixed_div;
|
||||
void __iomem *enable_reg;
|
||||
u8 enable_bit;
|
||||
u8 flags;
|
||||
void __iomem *clksel_reg;
|
||||
u32 clksel_mask;
|
||||
const struct clksel *clksel;
|
||||
struct dpll_data *dpll_data;
|
||||
const char *clkdm_name;
|
||||
struct clockdomain *clkdm;
|
||||
const struct clk_hw_omap_ops *ops;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct clk_hw_omap.flags possibilities
|
||||
*
|
||||
* XXX document the rest of the clock flags here
|
||||
*
|
||||
* ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
|
||||
* with 32bit ops, by default OMAP1 uses 16bit ops.
|
||||
* CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
|
||||
* CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
|
||||
* clock is put to no-idle mode.
|
||||
* ENABLE_ON_INIT: Clock is enabled on init.
|
||||
* INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
|
||||
* disable. This inverts the behavior making '0' enable and '1' disable.
|
||||
* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
|
||||
* bits share the same register. This flag allows the
|
||||
* omap4_dpllmx*() code to determine which GATE_CTRL bit field
|
||||
* should be used. This is a temporary solution - a better approach
|
||||
* would be to associate clock type-specific data with the clock,
|
||||
* similar to the struct dpll_data approach.
|
||||
* MEMMAP_ADDRESSING: Use memmap addressing to access clock registers.
|
||||
*/
|
||||
#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
|
||||
#define CLOCK_IDLE_CONTROL (1 << 1)
|
||||
#define CLOCK_NO_IDLE_PARENT (1 << 2)
|
||||
#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
|
||||
#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
|
||||
#define CLOCK_CLKOUTX2 (1 << 5)
|
||||
#define MEMMAP_ADDRESSING (1 << 6)
|
||||
|
||||
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
|
||||
#define DPLL_LOW_POWER_STOP 0x1
|
||||
#define DPLL_LOW_POWER_BYPASS 0x5
|
||||
#define DPLL_LOCKED 0x7
|
||||
|
||||
/* DPLL Type and DCO Selection Flags */
|
||||
#define DPLL_J_TYPE 0x1
|
||||
|
||||
/* Composite clock component types */
|
||||
enum {
|
||||
CLK_COMPONENT_TYPE_GATE = 0,
|
||||
CLK_COMPONENT_TYPE_DIVIDER,
|
||||
CLK_COMPONENT_TYPE_MUX,
|
||||
CLK_COMPONENT_TYPE_MAX,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_dt_clk - OMAP DT clock alias declarations
|
||||
* @lk: clock lookup definition
|
||||
* @node_name: clock DT node to map to
|
||||
*/
|
||||
struct ti_dt_clk {
|
||||
struct clk_lookup lk;
|
||||
char *node_name;
|
||||
};
|
||||
|
||||
#define DT_CLK(dev, con, name) \
|
||||
{ \
|
||||
.lk = { \
|
||||
.dev_id = dev, \
|
||||
.con_id = con, \
|
||||
}, \
|
||||
.node_name = name, \
|
||||
}
|
||||
|
||||
/* Maximum number of clock memmaps */
|
||||
#define CLK_MAX_MEMMAPS 4
|
||||
|
||||
typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
|
||||
|
||||
/**
|
||||
* struct clk_omap_reg - OMAP register declaration
|
||||
* @offset: offset from the master IP module base address
|
||||
* @index: index of the master IP module
|
||||
*/
|
||||
struct clk_omap_reg {
|
||||
u16 offset;
|
||||
u16 index;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_clk_ll_ops - low-level register access ops for a clock
|
||||
* @clk_readl: pointer to register read function
|
||||
* @clk_writel: pointer to register write function
|
||||
*
|
||||
* Low-level register access ops are generally used by the basic clock types
|
||||
* (clk-gate, clk-mux, clk-divider etc.) to provide support for various
|
||||
* low-level hardware interfaces (direct MMIO, regmap etc.), but can also be
|
||||
* used by other hardware-specific clock drivers if needed.
|
||||
*/
|
||||
struct ti_clk_ll_ops {
|
||||
u32 (*clk_readl)(void __iomem *reg);
|
||||
void (*clk_writel)(u32 val, void __iomem *reg);
|
||||
};
|
||||
|
||||
extern struct ti_clk_ll_ops *ti_clk_ll_ops;
|
||||
|
||||
extern const struct clk_ops ti_clk_divider_ops;
|
||||
extern const struct clk_ops ti_clk_mux_ops;
|
||||
|
||||
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
|
||||
|
||||
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
|
||||
int omap3_noncore_dpll_enable(struct clk_hw *hw);
|
||||
void omap3_noncore_dpll_disable(struct clk_hw *hw);
|
||||
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
|
||||
unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
u8 omap2_init_dpll_parent(struct clk_hw *hw);
|
||||
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
|
||||
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
void omap2_init_clk_clkdm(struct clk_hw *clk);
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
|
||||
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
|
||||
int omap2_clk_disable_autoidle_all(void);
|
||||
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
|
||||
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
int omap2_dflt_clk_enable(struct clk_hw *hw);
|
||||
void omap2_dflt_clk_disable(struct clk_hw *hw);
|
||||
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
|
||||
void omap3_clk_lock_dpll5(void);
|
||||
|
||||
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
|
||||
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
|
||||
void ti_dt_clk_init_provider(struct device_node *np, int index);
|
||||
void ti_dt_clockdomains_setup(void);
|
||||
int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
|
||||
ti_of_clk_init_cb_t func);
|
||||
int of_ti_clk_autoidle_setup(struct device_node *node);
|
||||
int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
|
||||
|
||||
int omap3430_dt_clk_init(void);
|
||||
int omap3630_dt_clk_init(void);
|
||||
int am35xx_dt_clk_init(void);
|
||||
int ti81xx_dt_clk_init(void);
|
||||
int omap4xxx_dt_clk_init(void);
|
||||
int omap5xxx_dt_clk_init(void);
|
||||
int dra7xx_dt_clk_init(void);
|
||||
int am33xx_dt_clk_init(void);
|
||||
int am43xx_dt_clk_init(void);
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
void of_ti_clk_allow_autoidle_all(void);
|
||||
void of_ti_clk_deny_autoidle_all(void);
|
||||
#else
|
||||
static inline void of_ti_clk_allow_autoidle_all(void) { }
|
||||
static inline void of_ti_clk_deny_autoidle_all(void) { }
|
||||
#endif
|
||||
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
|
||||
extern const struct clk_hw_omap_ops clkhwops_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_iclk;
|
||||
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
|
||||
|
||||
#endif
|
||||
|
|
@ -7,20 +7,6 @@
|
|||
|
||||
struct clk;
|
||||
|
||||
/**
|
||||
* enum si5351_variant - SiLabs Si5351 chip variant
|
||||
* @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
|
||||
* @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
|
||||
* @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
|
||||
* @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
|
||||
*/
|
||||
enum si5351_variant {
|
||||
SI5351_VARIANT_A = 1,
|
||||
SI5351_VARIANT_A3 = 2,
|
||||
SI5351_VARIANT_B = 3,
|
||||
SI5351_VARIANT_C = 4,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum si5351_pll_src - Si5351 pll clock source
|
||||
* @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config
|
||||
|
|
@ -115,14 +101,12 @@ struct si5351_clkout_config {
|
|||
|
||||
/**
|
||||
* struct si5351_platform_data - Platform data for the Si5351 clock driver
|
||||
* @variant: Si5351 chip variant
|
||||
* @clk_xtal: xtal input clock
|
||||
* @clk_clkin: clkin input clock
|
||||
* @pll_src: array of pll source clock setting
|
||||
* @clkout: array of clkout configuration
|
||||
*/
|
||||
struct si5351_platform_data {
|
||||
enum si5351_variant variant;
|
||||
struct clk *clk_xtal;
|
||||
struct clk *clk_clkin;
|
||||
enum si5351_pll_src pll_src[2];
|
||||
|
|
|
|||
Loading…
Reference in a new issue