i2c: octeon: Enable High-Level Controller
Use High-Level Controller (HLC) when possible. The HLC can read/write up to 8 bytes and is completely optional. The most important difference of the HLC is that it only requires one interrupt for a transfer (up to 8 bytes) where the low-level read/write requires 2 interrupts plus one interrupt per transferred byte. Since the interrupts are costly using the HLC improves the performance. Also, the HLC provides improved error handling. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Jan Glauber <jglauber@cavium.com> [wsa: fixed trivial checkpatch warnings] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
David Daney
Wolfram Sang
parent
30c24b2514
commit
d1fbff8944
1 changed files with 337 additions and 10 deletions
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@ -29,13 +29,23 @@
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/* Register offsets */
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#define SW_TWSI 0x00
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#define TWSI_INT 0x10
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#define SW_TWSI_EXT 0x18
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/* Controller command patterns */
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#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
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#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
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#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
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#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
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#define SW_TWSI_SIZE_SHIFT 52
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#define SW_TWSI_ADDR_SHIFT 40
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#define SW_TWSI_IA_SHIFT 32 /* Internal address */
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/* Controller opcode word (bits 60:57) */
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#define SW_TWSI_OP_SHIFT 57
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#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
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@ -48,7 +58,7 @@
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#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
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/* Controller command and status bits */
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#define TWSI_CTL_CE 0x80
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#define TWSI_CTL_CE 0x80 /* High level controller enable */
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#define TWSI_CTL_ENAB 0x40 /* Bus enable */
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#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
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#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
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@ -87,6 +97,11 @@
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#define STAT_IDLE 0xF8
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/* TWSI_INT values */
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#define TWSI_INT_ST_INT BIT_ULL(0)
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#define TWSI_INT_TS_INT BIT_ULL(1)
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#define TWSI_INT_CORE_INT BIT_ULL(2)
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#define TWSI_INT_ST_EN BIT_ULL(4)
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#define TWSI_INT_TS_EN BIT_ULL(5)
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#define TWSI_INT_CORE_EN BIT_ULL(6)
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#define TWSI_INT_SDA_OVR BIT_ULL(8)
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#define TWSI_INT_SCL_OVR BIT_ULL(9)
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@ -101,6 +116,7 @@ struct octeon_i2c {
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int sys_freq;
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void __iomem *twsi_base;
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struct device *dev;
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bool hlc_enabled;
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};
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static void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
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@ -200,6 +216,47 @@ static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
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octeon_i2c_write_int(i2c, 0);
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}
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/*
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* Cleanup low-level state & enable high-level controller.
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*/
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static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
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{
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int try = 0;
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u64 val;
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if (i2c->hlc_enabled)
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return;
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i2c->hlc_enabled = true;
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while (1) {
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val = octeon_i2c_ctl_read(i2c);
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if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
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break;
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/* clear IFLG event */
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if (val & TWSI_CTL_IFLG)
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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if (try++ > 100) {
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pr_err("%s: giving up\n", __func__);
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break;
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}
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/* spin until any start/stop has finished */
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udelay(10);
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}
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octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
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}
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static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
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{
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if (!i2c->hlc_enabled)
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return;
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i2c->hlc_enabled = false;
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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}
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/* interrupt service routine */
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static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
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{
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@ -299,6 +356,245 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
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}
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}
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static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c)
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{
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u64 val = __raw_readq(i2c->twsi_base + SW_TWSI);
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return (val & SW_TWSI_V) == 0;
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}
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static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
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{
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octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
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}
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static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
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{
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/* clear ST/TS events, listen for neither */
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octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
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}
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/**
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* octeon_i2c_hlc_wait - wait for an HLC operation to complete
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* @i2c: The struct octeon_i2c
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*
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* Returns 0 on success, otherwise -ETIMEDOUT.
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*/
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static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
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{
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int time_left;
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octeon_i2c_hlc_int_enable(i2c);
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time_left = wait_event_timeout(i2c->queue,
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octeon_i2c_hlc_test_ready(i2c),
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i2c->adap.timeout);
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octeon_i2c_int_disable(i2c);
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if (!time_left) {
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octeon_i2c_hlc_int_clear(i2c);
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return -ETIMEDOUT;
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}
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return 0;
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}
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/* high-level-controller pure read of up to 8 bytes */
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static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
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{
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int i, j, ret = 0;
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u64 cmd;
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octeon_i2c_hlc_enable(i2c);
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octeon_i2c_hlc_int_clear(i2c);
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cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
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/* SIZE */
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cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
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/* A */
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cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
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if (msgs[0].flags & I2C_M_TEN)
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cmd |= SW_TWSI_OP_10;
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else
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cmd |= SW_TWSI_OP_7;
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octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
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ret = octeon_i2c_hlc_wait(i2c);
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if (ret)
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goto err;
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
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if ((cmd & SW_TWSI_R) == 0)
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return -EAGAIN;
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for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
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msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
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if (msgs[0].len > 4) {
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
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for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
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msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
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}
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err:
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return ret;
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}
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/* high-level-controller pure write of up to 8 bytes */
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static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
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{
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int i, j, ret = 0;
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u64 cmd;
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octeon_i2c_hlc_enable(i2c);
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octeon_i2c_hlc_int_clear(i2c);
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cmd = SW_TWSI_V | SW_TWSI_SOVR;
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/* SIZE */
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cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
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/* A */
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cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
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if (msgs[0].flags & I2C_M_TEN)
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cmd |= SW_TWSI_OP_10;
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else
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cmd |= SW_TWSI_OP_7;
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for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
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cmd |= (u64)msgs[0].buf[j] << (8 * i);
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if (msgs[0].len > 4) {
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u64 ext = 0;
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for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
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ext |= (u64)msgs[0].buf[j] << (8 * i);
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octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
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}
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octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
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ret = octeon_i2c_hlc_wait(i2c);
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if (ret)
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goto err;
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
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if ((cmd & SW_TWSI_R) == 0)
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return -EAGAIN;
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ret = octeon_i2c_check_status(i2c, false);
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err:
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return ret;
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}
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/* high-level-controller composite write+read, msg0=addr, msg1=data */
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static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
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{
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int i, j, ret = 0;
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u64 cmd;
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octeon_i2c_hlc_enable(i2c);
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cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
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/* SIZE */
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cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
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/* A */
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cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
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if (msgs[0].flags & I2C_M_TEN)
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cmd |= SW_TWSI_OP_10_IA;
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else
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cmd |= SW_TWSI_OP_7_IA;
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if (msgs[0].len == 2) {
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u64 ext = 0;
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cmd |= SW_TWSI_EIA;
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ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
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cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
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octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
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} else {
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cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
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}
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octeon_i2c_hlc_int_clear(i2c);
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octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
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ret = octeon_i2c_hlc_wait(i2c);
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if (ret)
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goto err;
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
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if ((cmd & SW_TWSI_R) == 0)
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return -EAGAIN;
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for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
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msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
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if (msgs[1].len > 4) {
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
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for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
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msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
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}
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err:
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return ret;
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}
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/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
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static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
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{
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bool set_ext = false;
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int i, j, ret = 0;
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u64 cmd, ext = 0;
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octeon_i2c_hlc_enable(i2c);
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cmd = SW_TWSI_V | SW_TWSI_SOVR;
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/* SIZE */
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cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
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/* A */
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cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
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if (msgs[0].flags & I2C_M_TEN)
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cmd |= SW_TWSI_OP_10_IA;
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else
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cmd |= SW_TWSI_OP_7_IA;
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if (msgs[0].len == 2) {
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cmd |= SW_TWSI_EIA;
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ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
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set_ext = true;
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cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
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} else {
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cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
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}
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for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
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cmd |= (u64)msgs[1].buf[j] << (8 * i);
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if (msgs[1].len > 4) {
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for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
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ext |= (u64)msgs[1].buf[j] << (8 * i);
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set_ext = true;
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}
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if (set_ext)
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octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
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octeon_i2c_hlc_int_clear(i2c);
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octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
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ret = octeon_i2c_hlc_wait(i2c);
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if (ret)
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goto err;
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
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if ((cmd & SW_TWSI_R) == 0)
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return -EAGAIN;
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ret = octeon_i2c_check_status(i2c, false);
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err:
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return ret;
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}
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/* calculate and set clock divisors */
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static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
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{
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@ -343,23 +639,29 @@ static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
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static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
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{
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u8 status;
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u8 status = 0;
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int tries;
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/* disable high level controller, enable bus access */
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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/* reset controller */
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octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
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for (tries = 10; tries; tries--) {
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for (tries = 10; tries && status != STAT_IDLE; tries--) {
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udelay(1);
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status = octeon_i2c_stat_read(i2c);
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if (status == STAT_IDLE)
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return 0;
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break;
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}
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dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
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return -EIO;
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if (status != STAT_IDLE) {
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dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
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__func__, status);
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return -EIO;
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}
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/* toggle twice to force both teardowns */
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octeon_i2c_hlc_enable(i2c);
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octeon_i2c_hlc_disable(i2c);
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return 0;
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}
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static int octeon_i2c_recovery(struct octeon_i2c *i2c)
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@ -384,6 +686,8 @@ static int octeon_i2c_start(struct octeon_i2c *i2c)
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int ret;
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u8 stat;
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octeon_i2c_hlc_disable(i2c);
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
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ret = octeon_i2c_wait(i2c);
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if (ret)
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@ -526,6 +830,28 @@ static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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struct octeon_i2c *i2c = i2c_get_adapdata(adap);
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int i, ret = 0;
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if (num == 1) {
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if (msgs[0].len > 0 && msgs[0].len <= 8) {
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if (msgs[0].flags & I2C_M_RD)
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ret = octeon_i2c_hlc_read(i2c, msgs);
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else
|
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ret = octeon_i2c_hlc_write(i2c, msgs);
|
||||
goto out;
|
||||
}
|
||||
} else if (num == 2) {
|
||||
if ((msgs[0].flags & I2C_M_RD) == 0 &&
|
||||
(msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
|
||||
msgs[0].len > 0 && msgs[0].len <= 2 &&
|
||||
msgs[1].len > 0 && msgs[1].len <= 8 &&
|
||||
msgs[0].addr == msgs[1].addr) {
|
||||
if (msgs[1].flags & I2C_M_RD)
|
||||
ret = octeon_i2c_hlc_comp_read(i2c, msgs);
|
||||
else
|
||||
ret = octeon_i2c_hlc_comp_write(i2c, msgs);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; ret == 0 && i < num; i++) {
|
||||
struct i2c_msg *pmsg = &msgs[i];
|
||||
|
||||
|
|
@ -541,7 +867,7 @@ static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
|||
pmsg->len);
|
||||
}
|
||||
octeon_i2c_stop(i2c);
|
||||
|
||||
out:
|
||||
return (ret != 0) ? ret : num;
|
||||
}
|
||||
|
||||
|
|
@ -580,6 +906,7 @@ static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
|
|||
*/
|
||||
octeon_i2c_stop(i2c);
|
||||
|
||||
octeon_i2c_hlc_disable(i2c);
|
||||
octeon_i2c_write_int(i2c, 0);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue