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unicore32: pwm: Properly remap memory-mapped registers

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Instead of writing to the timer controller registers by dereferencing a
pointer to the memory location, properly remap the memory region with a
call to ioremap_nocache() and access the registers using writel().

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Tested-by: Qin Rui <qinrui@mprc.pku.edu.cn>
This commit is contained in:
Thierry Reding 2012-09-14 16:14:25 +08:00
parent 60ce70285b
commit d1b6886502
2 changed files with 26 additions and 13 deletions
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18
arch/unicore32/include/mach/regs-ost.h
View file

@ -33,18 +33,16 @@
* Interrupt Enable Reg OST_OIER * Interrupt Enable Reg OST_OIER
*/ */
#define OST_OIER (PKUNITY_OST_BASE + 0x001C) #define OST_OIER (PKUNITY_OST_BASE + 0x001C)
/* /*
* PWM Pulse Width Control Reg OST_PWMPWCR * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
* PWCR: Pulse Width Control Reg
* DCCR: Duty Cycle Control Reg
* PCR: Period Control Reg
*/ */
#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080) #define OST_PWM_PWCR (0x00)
/* #define OST_PWM_DCCR (0x04)
* PWM Duty Cycle Control Reg OST_PWMDCCR #define OST_PWM_PCR (0x08)
*/
#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084)
/*
* PWM Period Control Reg OST_PWMPCR
*/
#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088)
/* /*
* Match detected 0 OST_OSSR_M0 * Match detected 0 OST_OSSR_M0

21
arch/unicore32/kernel/pwm.c
View file

@ -27,6 +27,8 @@ struct pwm_device {
struct list_head node; struct list_head node;
struct platform_device *pdev; struct platform_device *pdev;
void __iomem *base;
const char *label; const char *label;
struct clk *clk; struct clk *clk;
int clk_enabled; int clk_enabled;
@ -69,9 +71,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
* before writing to the registers * before writing to the registers
*/ */
clk_enable(pwm->clk); clk_enable(pwm->clk);
OST_PWMPWCR = prescale;
OST_PWMDCCR = pv - dc; writel(prescale, pwm->base + OST_PWM_PWCR);
OST_PWMPCR = pv; writel(pv - dc, pwm->base + OST_PWM_DCCR);
writel(pv, pwm->base + OST_PWM_PCR);
clk_disable(pwm->clk); clk_disable(pwm->clk);
return 0; return 0;
@ -190,10 +194,19 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev,
goto err_free_clk; goto err_free_clk;
} }
pwm->base = ioremap_nocache(r->start, resource_size(r));
if (pwm->base == NULL) {
dev_err(&pdev->dev, "failed to remap memory resource\n");
ret = -EADDRNOTAVAIL;
goto err_release_mem;
}
__add_pwm(pwm); __add_pwm(pwm);
platform_set_drvdata(pdev, pwm); platform_set_drvdata(pdev, pwm);
return pwm; return pwm;
err_release_mem:
release_mem_region(r->start, resource_size(r));
err_free_clk: err_free_clk:
clk_put(pwm->clk); clk_put(pwm->clk);
err_free: err_free:
@ -224,6 +237,8 @@ static int __devexit pwm_remove(struct platform_device *pdev)
list_del(&pwm->node); list_del(&pwm->node);
mutex_unlock(&pwm_lock); mutex_unlock(&pwm_lock);
iounmap(pwm->base);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, resource_size(r)); release_mem_region(r->start, resource_size(r));