[ARM] 4143/1: AT91: Prepare for AT91SAM9263 support
The Atmel AT91SAM9263 processor includes many more integrated
peripherals than Atmel's previous ARM9-based AT91 processors, so this
has necessitated a few changes to the core AT91 support.
These changes are:
* The system peripheral I/O region we remap has increased from
0xFFFA0000..0xFFFFFFFF to 0xFFF78000..0xFFFFFFFF.
* The increased I/O region forces changes to entry-macro.S and
debug-macro.S due to ARM's limited immediate offset addressing
modes.
* Maximum number of GPIO banks increases to 5.
* 2 MMC controllers so the board-setup code needs to specify which
controller it wishes to use when calling at91_add_device_mmc().
Original patch from Nicolas Ferre.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
9d0412680e
commit
d0760b3bc8
18 changed files with 72 additions and 62 deletions
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@ -315,7 +315,7 @@ static struct platform_device at91rm9200_mmc_device = {
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.num_resources = ARRAY_SIZE(mmc_resources),
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};
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void __init at91_add_device_mmc(struct at91_mmc_data *data)
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void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
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{
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if (!data)
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return;
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@ -361,7 +361,7 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
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platform_device_register(&at91rm9200_mmc_device);
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}
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#else
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void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
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void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
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#endif
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@ -229,7 +229,7 @@ static struct platform_device at91sam9260_mmc_device = {
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.num_resources = ARRAY_SIZE(mmc_resources),
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};
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void __init at91_add_device_mmc(struct at91_mmc_data *data)
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void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
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{
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if (!data)
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return;
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@ -275,7 +275,7 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
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platform_device_register(&at91sam9260_mmc_device);
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}
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#else
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void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
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void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
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#endif
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@ -159,7 +159,7 @@ static struct platform_device at91sam9261_mmc_device = {
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.num_resources = ARRAY_SIZE(mmc_resources),
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};
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void __init at91_add_device_mmc(struct at91_mmc_data *data)
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void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
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{
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if (!data)
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return;
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@ -192,7 +192,7 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
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platform_device_register(&at91sam9261_mmc_device);
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}
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#else
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void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
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void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
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#endif
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@ -134,7 +134,7 @@ static void __init carmeva_board_init(void)
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/* Compact Flash */
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// at91_add_device_cf(&carmeva_cf_data);
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/* MMC */
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at91_add_device_mmc(&carmeva_mmc_data);
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at91_add_device_mmc(0, &carmeva_mmc_data);
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}
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MACHINE_START(CARMEVA, "Carmeva")
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@ -130,7 +130,7 @@ static void __init csb337_board_init(void)
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/* SPI */
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at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
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/* MMC */
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at91_add_device_mmc(&csb337_mmc_data);
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at91_add_device_mmc(0, &csb337_mmc_data);
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}
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MACHINE_START(CSB337, "Cogent CSB337")
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@ -194,7 +194,7 @@ static void __init dk_board_init(void)
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#else
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/* MMC */
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at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
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at91_add_device_mmc(&dk_mmc_data);
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at91_add_device_mmc(0, &dk_mmc_data);
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#endif
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/* NAND */
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at91_add_device_nand(&dk_nand_data);
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@ -109,7 +109,7 @@ static void __init eb9200_board_init(void)
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at91_add_device_spi(NULL, 0);
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/* MMC */
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/* only supports 1 or 4 bit interface, not wired through to SPI */
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at91_add_device_mmc(&eb9200_mmc_data);
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at91_add_device_mmc(0, &eb9200_mmc_data);
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}
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MACHINE_START(ATEB9200, "Embest ATEB9200")
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@ -154,7 +154,7 @@ static void __init ek_board_init(void)
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#else
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/* MMC */
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at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
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at91_add_device_mmc(&ek_mmc_data);
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at91_add_device_mmc(0, &ek_mmc_data);
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#endif
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/* NOR Flash */
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platform_device_register(&ek_flash);
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@ -122,7 +122,7 @@ static void __init kb9202_board_init(void)
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/* USB Device */
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at91_add_device_udc(&kb9202_udc_data);
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/* MMC */
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at91_add_device_mmc(&kb9202_mmc_data);
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at91_add_device_mmc(0, &kb9202_mmc_data);
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/* I2C */
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at91_add_device_i2c();
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/* SPI */
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@ -1,5 +1,5 @@
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/*
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* linux/arch/arm/mach-at91/board-ek.c
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* linux/arch/arm/mach-at91/board-sam9260ek.c
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*
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* Copyright (C) 2005 SAN People
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* Copyright (C) 2006 Atmel
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@ -187,7 +187,7 @@ static void __init ek_board_init(void)
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/* Ethernet */
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at91_add_device_eth(&ek_macb_data);
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/* MMC */
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at91_add_device_mmc(&ek_mmc_data);
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at91_add_device_mmc(0, &ek_mmc_data);
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}
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MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
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@ -1,5 +1,5 @@
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/*
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* linux/arch/arm/mach-at91/board-ek.c
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* linux/arch/arm/mach-at91/board-sam9261ek.c
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*
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* Copyright (C) 2005 SAN People
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* Copyright (C) 2006 Atmel
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@ -243,7 +243,7 @@ static void __init ek_board_init(void)
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at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
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#else
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/* MMC */
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at91_add_device_mmc(&ek_mmc_data);
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at91_add_device_mmc(0, &ek_mmc_data);
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#endif
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}
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@ -18,7 +18,7 @@
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#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
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#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
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#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
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#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */
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#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
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#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
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#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
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#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
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@ -60,7 +60,7 @@ struct at91_mmc_data {
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u8 wp_pin; /* (SD) writeprotect detect */
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u8 vcc_pin; /* power switching (high == on) */
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};
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extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
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extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
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/* Ethernet */
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struct at91_eth_data {
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@ -76,6 +76,7 @@ extern void __init at91_add_device_eth(struct at91_eth_data *data);
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/* USB Host */
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struct at91_usbh_data {
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u8 ports; /* number of ports on root hub */
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u8 vbus_pin[]; /* port power-control pin */
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};
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extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
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@ -16,24 +16,24 @@
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.macro addruart,rx
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mrc p15, 0, \rx, c1, c0
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tst \rx, #1 @ MMU enabled?
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ldreq \rx, =AT91_BASE_SYS @ System peripherals (phys address)
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ldrne \rx, =AT91_VA_BASE_SYS @ System peripherals (virt address)
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tst \rx, #1 @ MMU enabled?
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ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
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ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
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.endm
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.macro senduart,rd,rx
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strb \rd, [\rx, #AT91_DBGU_THR] @ Write to Transmitter Holding Register
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strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register
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.endm
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.macro waituart,rd,rx
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1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
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tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
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1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
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tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
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tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
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1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
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tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
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beq 1001b
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.endm
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@ -17,10 +17,10 @@
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals
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ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
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ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number
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teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
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streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now.
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ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
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ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
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ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
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teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
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streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now.
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.endm
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@ -17,7 +17,7 @@
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#define PIN_BASE NR_AIC_IRQS
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#define MAX_GPIO_BANKS 4
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#define MAX_GPIO_BANKS 5
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/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
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@ -26,37 +26,31 @@
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#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
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#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
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#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
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#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
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#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
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#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
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#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
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#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
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#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
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#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
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#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
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#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
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#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
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#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
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#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
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#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
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#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
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#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
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#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
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#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
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#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
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#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
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#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
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#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
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#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
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#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
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#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
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#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
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#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
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#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
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@ -65,37 +59,31 @@
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#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
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#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
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#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
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#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
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#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
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#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
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#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
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#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
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#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
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#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
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#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
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#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
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#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
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#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
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#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
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#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
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#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
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#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
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#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
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#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
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#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
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#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
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#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
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#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
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#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
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#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
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#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
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#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
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#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
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#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
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@ -104,37 +92,31 @@
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#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
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#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
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#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
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#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
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#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
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#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
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#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
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#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
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#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
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#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
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#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
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#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
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#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
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#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
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#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
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#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
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#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
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#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
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#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
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#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
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#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
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#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
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#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
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#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
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#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
|
||||
#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
|
||||
#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
|
||||
#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
|
||||
|
||||
#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
|
||||
#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
|
||||
|
||||
|
|
@ -143,40 +125,67 @@
|
|||
#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
|
||||
#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
|
||||
#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
|
||||
|
||||
#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
|
||||
#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
|
||||
#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
|
||||
#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
|
||||
#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
|
||||
|
||||
#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
|
||||
#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
|
||||
#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
|
||||
#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
|
||||
#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
|
||||
|
||||
#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
|
||||
#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
|
||||
#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
|
||||
#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
|
||||
#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
|
||||
|
||||
#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
|
||||
#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
|
||||
#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
|
||||
#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
|
||||
#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
|
||||
|
||||
#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
|
||||
#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
|
||||
#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
|
||||
#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
|
||||
#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
|
||||
|
||||
#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
|
||||
#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
|
||||
|
||||
#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
|
||||
#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
|
||||
#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
|
||||
#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
|
||||
#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
|
||||
#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
|
||||
#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
|
||||
#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
|
||||
#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
|
||||
#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
|
||||
#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
|
||||
#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
|
||||
#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
|
||||
#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
|
||||
#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
|
||||
#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
|
||||
#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
|
||||
#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
|
||||
#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
|
||||
#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
|
||||
#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
|
||||
#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
|
||||
#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
|
||||
#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
|
||||
#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
|
||||
#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
|
||||
#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
|
||||
#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
|
||||
#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
|
||||
#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
|
||||
#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
|
||||
#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* setup setup routines, called from board init or driver probe() */
|
||||
extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
|
||||
|
|
|
|||
|
|
@ -28,15 +28,15 @@
|
|||
|
||||
|
||||
/*
|
||||
* Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
|
||||
* to 0xFEFA0000 .. 0xFF000000. (384Kb)
|
||||
* Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
|
||||
* to 0xFEF78000 .. 0xFF000000. (5444Kb)
|
||||
*/
|
||||
#define AT91_IO_PHYS_BASE 0xFFFA0000
|
||||
#define AT91_IO_PHYS_BASE 0xFFF78000
|
||||
#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
|
||||
#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
|
||||
|
||||
/* Convert a physical IO address to virtual IO address */
|
||||
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
|
||||
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
|
||||
|
||||
/*
|
||||
* Virtual to Physical Address mapping for IO devices.
|
||||
|
|
|
|||
|
|
@ -37,8 +37,8 @@
|
|||
* IRQ interrupt symbols are the AT91xxx_ID_* symbols
|
||||
* for IRQs handled directly through the AIC, or else the AT91_PIN_*
|
||||
* symbols in gpio.h for ones handled indirectly as GPIOs.
|
||||
* We make provision for 4 banks of GPIO.
|
||||
* We make provision for 5 banks of GPIO.
|
||||
*/
|
||||
#define NR_IRQS (NR_AIC_IRQS + (4 * 32))
|
||||
#define NR_IRQS (NR_AIC_IRQS + (5 * 32))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue