[ARM] 3052/1: add ixp2000 microcode loader
Patch from Lennert Buytenhek
This patch adds a microcode loader for the ixp2000 architecture.
The ixp2000 is an xscale-based CPU with a number of additional small
CPUs ('microengines') on die that can be programmed to do various
things. Depending on the ixp2000 model, there are between 2 and 16
microengines.
This code provides an API that allows configuring the microengines,
loading code into them, and starting and stopping them and reading
out a number of status registers, and is used by the microengine
network driver that was recently announced to netdev.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek
Russell King
parent
fadab0943d
commit
d01e8897fc
4 changed files with 540 additions and 3 deletions
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@ -1,7 +1,7 @@
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#
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# Makefile for the linux kernel.
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#
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obj-y := core.o pci.o
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obj-y := core.o pci.o uengine.o
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obj-m :=
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obj-n :=
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obj- :=
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474
arch/arm/mach-ixp2000/uengine.c
Normal file
474
arch/arm/mach-ixp2000/uengine.c
Normal file
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@ -0,0 +1,474 @@
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/*
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* Generic library functions for the microengines found on the Intel
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* IXP2000 series of network processors.
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*
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* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
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* Dedicated to Marija Kulikova.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as
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* published by the Free Software Foundation; either version 2.1 of the
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* License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <asm/hardware.h>
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#include <asm/arch/ixp2000-regs.h>
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#include <asm/arch/uengine.h>
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#include <asm/io.h>
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#define USTORE_ADDRESS 0x000
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#define USTORE_DATA_LOWER 0x004
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#define USTORE_DATA_UPPER 0x008
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#define CTX_ENABLES 0x018
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#define CC_ENABLE 0x01c
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#define CSR_CTX_POINTER 0x020
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#define INDIRECT_CTX_STS 0x040
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#define ACTIVE_CTX_STS 0x044
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#define INDIRECT_CTX_SIG_EVENTS 0x048
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#define INDIRECT_CTX_WAKEUP_EVENTS 0x050
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#define NN_PUT 0x080
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#define NN_GET 0x084
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#define TIMESTAMP_LOW 0x0c0
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#define TIMESTAMP_HIGH 0x0c4
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#define T_INDEX_BYTE_INDEX 0x0f4
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#define LOCAL_CSR_STATUS 0x180
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u32 ixp2000_uengine_mask;
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static void *ixp2000_uengine_csr_area(int uengine)
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{
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return ((void *)IXP2000_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
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}
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/*
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* LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
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* space means that the microengine we tried to access was also trying
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* to access its own CSR space on the same clock cycle as we did. When
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* this happens, we lose the arbitration process by default, and the
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* read or write we tried to do was not actually performed, so we try
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* again until it succeeds.
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*/
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u32 ixp2000_uengine_csr_read(int uengine, int offset)
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{
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void *uebase;
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u32 *local_csr_status;
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u32 *reg;
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u32 value;
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uebase = ixp2000_uengine_csr_area(uengine);
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local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
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reg = (u32 *)(uebase + offset);
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do {
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value = ixp2000_reg_read(reg);
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} while (ixp2000_reg_read(local_csr_status) & 1);
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return value;
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}
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EXPORT_SYMBOL(ixp2000_uengine_csr_read);
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void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
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{
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void *uebase;
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u32 *local_csr_status;
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u32 *reg;
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uebase = ixp2000_uengine_csr_area(uengine);
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local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
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reg = (u32 *)(uebase + offset);
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do {
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ixp2000_reg_write(reg, value);
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} while (ixp2000_reg_read(local_csr_status) & 1);
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}
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EXPORT_SYMBOL(ixp2000_uengine_csr_write);
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void ixp2000_uengine_reset(u32 uengine_mask)
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{
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ixp2000_reg_write(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
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ixp2000_reg_write(IXP2000_RESET1, 0);
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}
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EXPORT_SYMBOL(ixp2000_uengine_reset);
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void ixp2000_uengine_set_mode(int uengine, u32 mode)
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{
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/*
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* CTL_STR_PAR_EN: unconditionally enable parity checking on
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* control store.
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*/
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mode |= 0x10000000;
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ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
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/*
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* Enable updating of condition codes.
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*/
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ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
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/*
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* Initialise other per-microengine registers.
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*/
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ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
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ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
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ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
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}
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EXPORT_SYMBOL(ixp2000_uengine_set_mode);
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static int make_even_parity(u32 x)
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{
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return hweight32(x) & 1;
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}
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static void ustore_write(int uengine, u64 insn)
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{
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/*
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* Generate even parity for top and bottom 20 bits.
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*/
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insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
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insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
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/*
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* Write to microstore. The second write auto-increments
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* the USTORE_ADDRESS index register.
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*/
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ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
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ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
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}
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void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
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{
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int i;
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/*
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* Start writing to microstore at address 0.
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*/
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ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
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for (i = 0; i < insns; i++) {
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u64 insn;
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insn = (((u64)ucode[0]) << 32) |
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(((u64)ucode[1]) << 24) |
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(((u64)ucode[2]) << 16) |
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(((u64)ucode[3]) << 8) |
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((u64)ucode[4]);
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ucode += 5;
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ustore_write(uengine, insn);
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}
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/*
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* Pad with a few NOPs at the end (to avoid the microengine
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* aborting as it prefetches beyond the last instruction), unless
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* we run off the end of the instruction store first, at which
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* point the address register will wrap back to zero.
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*/
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for (i = 0; i < 4; i++) {
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u32 addr;
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addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
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if (addr == 0x80000000)
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break;
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ustore_write(uengine, 0xf0000c0300ULL);
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}
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/*
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* End programming.
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*/
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ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
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}
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EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
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void ixp2000_uengine_init_context(int uengine, int context, int pc)
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{
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/*
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* Select the right context for indirect access.
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*/
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ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
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/*
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* Initialise signal masks to immediately go to Ready state.
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*/
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ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
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ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
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/*
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* Set program counter.
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*/
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ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
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}
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EXPORT_SYMBOL(ixp2000_uengine_init_context);
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void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
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{
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u32 mask;
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/*
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* Enable the specified context to go to Executing state.
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*/
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mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
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mask |= ctx_mask << 8;
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ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
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}
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EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
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void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
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{
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u32 mask;
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/*
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* Disable the Ready->Executing transition. Note that this
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* does not stop the context until it voluntarily yields.
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*/
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mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
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mask &= ~(ctx_mask << 8);
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ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
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}
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EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
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static int check_ixp_type(struct ixp2000_uengine_code *c)
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{
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u32 product_id;
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u32 rev;
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product_id = ixp2000_reg_read(IXP2000_PRODUCT_ID);
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if (((product_id >> 16) & 0x1f) != 0)
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return 0;
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switch ((product_id >> 8) & 0xff) {
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case 0: /* IXP2800 */
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if (!(c->cpu_model_bitmask & 4))
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return 0;
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break;
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case 1: /* IXP2850 */
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if (!(c->cpu_model_bitmask & 8))
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return 0;
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break;
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case 2: /* IXP2400 */
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if (!(c->cpu_model_bitmask & 2))
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return 0;
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break;
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default:
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return 0;
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}
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rev = product_id & 0xff;
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if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
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return 0;
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return 1;
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}
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static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
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{
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int offset;
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int i;
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offset = 0;
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for (i = 0; i < 128; i++) {
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u8 b3;
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u8 b2;
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u8 b1;
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u8 b0;
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b3 = (gpr_a[i] >> 24) & 0xff;
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b2 = (gpr_a[i] >> 16) & 0xff;
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b1 = (gpr_a[i] >> 8) & 0xff;
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b0 = gpr_a[i] & 0xff;
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// immed[@ai, (b1 << 8) | b0]
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// 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
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ucode[offset++] = 0xf0;
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ucode[offset++] = (b1 >> 4);
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ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
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ucode[offset++] = (b0 << 2);
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ucode[offset++] = 0x80 | i;
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// immed_w1[@ai, (b3 << 8) | b2]
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// 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
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ucode[offset++] = 0xf4;
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ucode[offset++] = 0x40 | (b3 >> 4);
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ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
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ucode[offset++] = (b2 << 2);
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ucode[offset++] = 0x80 | i;
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}
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for (i = 0; i < 128; i++) {
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u8 b3;
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u8 b2;
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u8 b1;
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u8 b0;
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b3 = (gpr_b[i] >> 24) & 0xff;
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b2 = (gpr_b[i] >> 16) & 0xff;
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b1 = (gpr_b[i] >> 8) & 0xff;
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b0 = gpr_b[i] & 0xff;
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// immed[@bi, (b1 << 8) | b0]
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// 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
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ucode[offset++] = 0xf0;
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ucode[offset++] = (b1 >> 4);
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ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
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ucode[offset++] = (i << 2) | 0x03;
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ucode[offset++] = b0;
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// immed_w1[@bi, (b3 << 8) | b2]
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// 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
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ucode[offset++] = 0xf4;
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ucode[offset++] = 0x40 | (b3 >> 4);
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ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
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ucode[offset++] = (i << 2) | 0x03;
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ucode[offset++] = b2;
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}
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// ctx_arb[kill]
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ucode[offset++] = 0xe0;
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ucode[offset++] = 0x00;
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ucode[offset++] = 0x01;
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ucode[offset++] = 0x00;
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ucode[offset++] = 0x00;
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}
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static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
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{
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int per_ctx_regs;
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u32 *gpr_a;
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u32 *gpr_b;
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u8 *ucode;
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int i;
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gpr_a = kmalloc(128 * sizeof(u32), GFP_KERNEL);
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gpr_b = kmalloc(128 * sizeof(u32), GFP_KERNEL);
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ucode = kmalloc(513 * 5, GFP_KERNEL);
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if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
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kfree(ucode);
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kfree(gpr_b);
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kfree(gpr_a);
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return 1;
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}
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per_ctx_regs = 16;
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if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
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per_ctx_regs = 32;
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memset(gpr_a, 0, sizeof(gpr_a));
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memset(gpr_b, 0, sizeof(gpr_b));
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for (i = 0; i < 256; i++) {
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struct ixp2000_reg_value *r = c->initial_reg_values + i;
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u32 *bank;
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int inc;
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int j;
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if (r->reg == -1)
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break;
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bank = (r->reg & 0x400) ? gpr_b : gpr_a;
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inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
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j = r->reg & 0x7f;
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while (j < 128) {
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bank[j] = r->value;
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j += inc;
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}
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}
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generate_ucode(ucode, gpr_a, gpr_b);
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ixp2000_uengine_load_microcode(uengine, ucode, 513);
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ixp2000_uengine_init_context(uengine, 0, 0);
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ixp2000_uengine_start_contexts(uengine, 0x01);
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for (i = 0; i < 100; i++) {
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u32 status;
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status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
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if (!(status & 0x80000000))
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break;
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}
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ixp2000_uengine_stop_contexts(uengine, 0x01);
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kfree(ucode);
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kfree(gpr_b);
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kfree(gpr_a);
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return !!(i == 100);
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}
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int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
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{
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int ctx;
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if (!check_ixp_type(c))
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return 1;
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if (!(ixp2000_uengine_mask & (1 << uengine)))
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return 1;
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ixp2000_uengine_reset(1 << uengine);
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ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
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if (set_initial_registers(uengine, c))
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return 1;
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ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
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for (ctx = 0; ctx < 8; ctx++)
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ixp2000_uengine_init_context(uengine, ctx, 0);
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return 0;
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}
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EXPORT_SYMBOL(ixp2000_uengine_load);
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static int __init ixp2000_uengine_init(void)
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{
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int uengine;
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u32 value;
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/*
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* Determine number of microengines present.
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*/
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switch ((ixp2000_reg_read(IXP2000_PRODUCT_ID) >> 8) & 0x1fff) {
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case 0: /* IXP2800 */
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case 1: /* IXP2850 */
|
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ixp2000_uengine_mask = 0x00ff00ff;
|
||||
break;
|
||||
|
||||
case 2: /* IXP2400 */
|
||||
ixp2000_uengine_mask = 0x000f000f;
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
|
||||
(unsigned int)ixp2000_reg_read(IXP2000_PRODUCT_ID));
|
||||
ixp2000_uengine_mask = 0x00000000;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset microengines.
|
||||
*/
|
||||
ixp2000_reg_write(IXP2000_RESET1, ixp2000_uengine_mask);
|
||||
ixp2000_reg_write(IXP2000_RESET1, 0);
|
||||
|
||||
/*
|
||||
* Synchronise timestamp counters across all microengines.
|
||||
*/
|
||||
value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
|
||||
ixp2000_reg_write(IXP2000_MISC_CONTROL, value & ~0x80);
|
||||
for (uengine = 0; uengine < 32; uengine++) {
|
||||
if (ixp2000_uengine_mask & (1 << uengine)) {
|
||||
ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
|
||||
ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
|
||||
}
|
||||
}
|
||||
ixp2000_reg_write(IXP2000_MISC_CONTROL, value | 0x80);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(ixp2000_uengine_init);
|
||||
|
|
@ -59,14 +59,15 @@
|
|||
#define IXP2000_CAP_SIZE 0x00100000
|
||||
|
||||
/*
|
||||
* Addresses for specific on-chip peripherals
|
||||
* Addresses for specific on-chip peripherals.
|
||||
*/
|
||||
#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
|
||||
#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
|
||||
#define IXP2000_UART_PHYS_BASE 0xc0030000
|
||||
#define IXP2000_UART_VIRT_BASE 0xfef30000
|
||||
#define IXP2000_TIMER_VIRT_BASE 0xfef20000
|
||||
#define IXP2000_GPIO_VIRT_BASE 0Xfef10000
|
||||
#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000
|
||||
#define IXP2000_GPIO_VIRT_BASE 0xfef10000
|
||||
|
||||
/*
|
||||
* Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
|
||||
|
|
|
|||
62
include/asm-arm/arch-ixp2000/uengine.h
Normal file
62
include/asm-arm/arch-ixp2000/uengine.h
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Generic library functions for the microengines found on the Intel
|
||||
* IXP2000 series of network processors.
|
||||
*
|
||||
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
|
||||
* Dedicated to Marija Kulikova.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as
|
||||
* published by the Free Software Foundation; either version 2.1 of the
|
||||
* License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __IXP2000_UENGINE_H
|
||||
#define __IXP2000_UENGINE_H
|
||||
|
||||
extern u32 ixp2000_uengine_mask;
|
||||
|
||||
struct ixp2000_uengine_code
|
||||
{
|
||||
u32 cpu_model_bitmask;
|
||||
u8 cpu_min_revision;
|
||||
u8 cpu_max_revision;
|
||||
|
||||
u32 uengine_parameters;
|
||||
|
||||
struct ixp2000_reg_value {
|
||||
int reg;
|
||||
u32 value;
|
||||
} *initial_reg_values;
|
||||
|
||||
int num_insns;
|
||||
u8 *insns;
|
||||
};
|
||||
|
||||
u32 ixp2000_uengine_csr_read(int uengine, int offset);
|
||||
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
|
||||
void ixp2000_uengine_reset(u32 uengine_mask);
|
||||
void ixp2000_uengine_set_mode(int uengine, u32 mode);
|
||||
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
|
||||
void ixp2000_uengine_init_context(int uengine, int context, int pc);
|
||||
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
|
||||
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
|
||||
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
|
||||
|
||||
#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
|
||||
#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
|
||||
#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
|
||||
#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
|
||||
#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
|
||||
#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
|
||||
#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
|
||||
#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
|
||||
#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
|
||||
#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue