drm/nouveau/device: add method to retrieve some basic device info
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
8ec2a6ec6e
commit
d01c3092f0
4 changed files with 171 additions and 37 deletions
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@ -26,6 +26,7 @@
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#include <core/client.h>
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#include <core/handle.h>
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#include <core/option.h>
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#include <nvif/class.h>
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#include <nvif/unpack.h>
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#include <nvif/event.h>
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@ -26,9 +26,13 @@
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#include <core/device.h>
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#include <core/client.h>
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#include <core/option.h>
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#include <nvif/unpack.h>
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#include <nvif/class.h>
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#include <core/class.h>
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#include <subdev/fb.h>
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#include <subdev/instmem.h>
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#include "priv.h"
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#include "acpi.h"
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@ -53,11 +57,131 @@ nouveau_device_find(u64 name)
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/******************************************************************************
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* nouveau_devobj (0x0080): class implementation
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*****************************************************************************/
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struct nouveau_devobj {
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struct nouveau_parent base;
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struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
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};
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static int
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nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size)
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{
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struct nouveau_device *device = nv_device(object);
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struct nouveau_fb *pfb = nouveau_fb(device);
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struct nouveau_instmem *imem = nouveau_instmem(device);
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union {
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struct nv_device_info_v0 v0;
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} *args = data;
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int ret;
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nv_ioctl(object, "device info size %d\n", size);
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if (nvif_unpack(args->v0, 0, 0, false)) {
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nv_ioctl(object, "device info vers %d\n", args->v0.version);
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} else
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return ret;
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switch (device->chipset) {
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case 0x01a:
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case 0x01f:
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case 0x04c:
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case 0x04e:
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case 0x063:
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case 0x067:
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case 0x068:
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case 0x0aa:
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case 0x0ac:
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case 0x0af:
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args->v0.platform = NV_DEVICE_INFO_V0_IGP;
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break;
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default:
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if (device->pdev) {
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if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP))
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args->v0.platform = NV_DEVICE_INFO_V0_AGP;
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else
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if (pci_is_pcie(device->pdev))
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args->v0.platform = NV_DEVICE_INFO_V0_PCIE;
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else
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args->v0.platform = NV_DEVICE_INFO_V0_PCI;
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} else {
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args->v0.platform = NV_DEVICE_INFO_V0_SOC;
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}
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break;
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}
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switch (device->card_type) {
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case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break;
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case NV_10:
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case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break;
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case NV_20: args->v0.family = NV_DEVICE_INFO_V0_KELVIN; break;
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case NV_30: args->v0.family = NV_DEVICE_INFO_V0_RANKINE; break;
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case NV_40: args->v0.family = NV_DEVICE_INFO_V0_CURIE; break;
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case NV_50: args->v0.family = NV_DEVICE_INFO_V0_TESLA; break;
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case NV_C0:
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case NV_D0: args->v0.family = NV_DEVICE_INFO_V0_FERMI; break;
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case NV_E0: args->v0.family = NV_DEVICE_INFO_V0_KEPLER; break;
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case GM100: args->v0.family = NV_DEVICE_INFO_V0_MAXWELL; break;
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default:
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args->v0.family = 0;
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break;
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}
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args->v0.chipset = device->chipset;
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args->v0.revision = device->chipset >= 0x10 ? nv_rd32(device, 0) : 0x00;
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if (pfb) args->v0.ram_size = args->v0.ram_user = pfb->ram->size;
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else args->v0.ram_size = args->v0.ram_user = 0;
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if (imem) args->v0.ram_user = args->v0.ram_user - imem->reserved;
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return 0;
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}
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static int
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nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd,
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void *data, u32 size)
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{
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switch (mthd) {
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case NV_DEVICE_V0_INFO:
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return nouveau_devobj_info(object, data, size);
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default:
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break;
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}
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return -EINVAL;
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}
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static u8
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nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
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{
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return nv_rd08(object->engine, addr);
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}
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static u16
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nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
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{
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return nv_rd16(object->engine, addr);
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}
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static u32
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nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
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{
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return nv_rd32(object->engine, addr);
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}
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static void
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nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
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{
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nv_wr08(object->engine, addr, data);
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}
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static void
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nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
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{
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nv_wr16(object->engine, addr, data);
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}
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static void
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nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
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{
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nv_wr32(object->engine, addr, data);
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}
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static const u64 disable_map[] = {
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[NVDEV_SUBDEV_VBIOS] = NV_DEVICE_DISABLE_VBIOS,
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[NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_DISABLE_CORE,
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@ -311,48 +435,13 @@ nouveau_devobj_dtor(struct nouveau_object *object)
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nouveau_parent_destroy(&devobj->base);
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}
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static u8
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nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
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{
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return nv_rd08(object->engine, addr);
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}
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static u16
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nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
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{
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return nv_rd16(object->engine, addr);
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}
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static u32
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nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
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{
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return nv_rd32(object->engine, addr);
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}
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static void
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nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
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{
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nv_wr08(object->engine, addr, data);
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}
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static void
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nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
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{
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nv_wr16(object->engine, addr, data);
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}
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static void
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nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
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{
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nv_wr32(object->engine, addr, data);
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}
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static struct nouveau_ofuncs
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nouveau_devobj_ofuncs = {
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.ctor = nouveau_devobj_ctor,
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.dtor = nouveau_devobj_dtor,
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.init = _nouveau_parent_init,
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.fini = _nouveau_parent_fini,
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.mthd = nouveau_devobj_mthd,
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.rd08 = nouveau_devobj_rd08,
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.rd16 = nouveau_devobj_rd16,
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.rd32 = nouveau_devobj_rd32,
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1
drivers/gpu/drm/nouveau/core/include/nvif/class.h
Symbolic link
1
drivers/gpu/drm/nouveau/core/include/nvif/class.h
Symbolic link
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@ -0,0 +1 @@
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../../../nvif/class.h
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43
drivers/gpu/drm/nouveau/nvif/class.h
Normal file
43
drivers/gpu/drm/nouveau/nvif/class.h
Normal file
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@ -0,0 +1,43 @@
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#ifndef __NVIF_CLASS_H__
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#define __NVIF_CLASS_H__
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/*******************************************************************************
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* class identifiers
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******************************************************************************/
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/* the below match nvidia-assigned (either in hw, or sw) class numbers */
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#define NV_DEVICE 0x00000080
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/*******************************************************************************
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* device
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******************************************************************************/
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#define NV_DEVICE_V0_INFO 0x00
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struct nv_device_info_v0 {
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__u8 version;
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#define NV_DEVICE_INFO_V0_IGP 0x00
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#define NV_DEVICE_INFO_V0_PCI 0x01
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#define NV_DEVICE_INFO_V0_AGP 0x02
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#define NV_DEVICE_INFO_V0_PCIE 0x03
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#define NV_DEVICE_INFO_V0_SOC 0x04
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__u8 platform;
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__u16 chipset; /* from NV_PMC_BOOT_0 */
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__u8 revision; /* from NV_PMC_BOOT_0 */
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#define NV_DEVICE_INFO_V0_TNT 0x01
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#define NV_DEVICE_INFO_V0_CELSIUS 0x02
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#define NV_DEVICE_INFO_V0_KELVIN 0x03
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#define NV_DEVICE_INFO_V0_RANKINE 0x04
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#define NV_DEVICE_INFO_V0_CURIE 0x05
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#define NV_DEVICE_INFO_V0_TESLA 0x06
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#define NV_DEVICE_INFO_V0_FERMI 0x07
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#define NV_DEVICE_INFO_V0_KEPLER 0x08
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#define NV_DEVICE_INFO_V0_MAXWELL 0x09
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__u8 family;
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__u8 pad06[2];
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__u64 ram_size;
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__u64 ram_user;
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};
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#endif
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