/spare/repo/netdev-2.6 branch 'e100'
This commit is contained in:
Jeff Garzik
commit
cfc4692825
1 changed files with 217 additions and 24 deletions
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@ -1,7 +1,7 @@
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/*******************************************************************************
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Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
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Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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@ -156,7 +156,7 @@
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#define DRV_NAME "e100"
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#define DRV_EXT "-NAPI"
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#define DRV_VERSION "3.4.8-k2"DRV_EXT
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#define DRV_VERSION "3.4.14-k2"DRV_EXT
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#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
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#define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
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#define PFX DRV_NAME ": "
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@ -785,6 +785,7 @@ static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
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}
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#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
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#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
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static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
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{
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unsigned long flags;
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@ -798,7 +799,7 @@ static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
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if(likely(!readb(&nic->csr->scb.cmd_lo)))
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break;
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cpu_relax();
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if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
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if(unlikely(i > E100_WAIT_SCB_FAST))
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udelay(5);
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}
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if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
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@ -902,8 +903,8 @@ static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
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static void e100_get_defaults(struct nic *nic)
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{
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struct param_range rfds = { .min = 16, .max = 256, .count = 64 };
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struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
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struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
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struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
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pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
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/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
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@ -1006,24 +1007,212 @@ static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
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c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
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}
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/********************************************************/
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/* Micro code for 8086:1229 Rev 8 */
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/********************************************************/
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/* Parameter values for the D101M B-step */
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#define D101M_CPUSAVER_TIMER_DWORD 78
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#define D101M_CPUSAVER_BUNDLE_DWORD 65
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#define D101M_CPUSAVER_MIN_SIZE_DWORD 126
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#define D101M_B_RCVBUNDLE_UCODE \
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{\
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0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
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0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
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0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
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0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
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0x00380438, 0x00000000, 0x00140000, 0x00380555, \
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0x00308000, 0x00100662, 0x00100561, 0x000E0408, \
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0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
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0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
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0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
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0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
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0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
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0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
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0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
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0x00041000, 0x00010004, 0x00130826, 0x000C0006, \
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0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
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0x00101210, 0x00380C34, 0x00000000, 0x00000000, \
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0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
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0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
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0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
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0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
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0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
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0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
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0x00130826, 0x000C0001, 0x00220559, 0x00101313, \
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0x00380559, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00130831, 0x0010090B, 0x00124813, \
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0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
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0x003806A8, 0x00000000, 0x00000000, 0x00000000, \
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}
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/********************************************************/
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/* Micro code for 8086:1229 Rev 9 */
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/********************************************************/
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/* Parameter values for the D101S */
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#define D101S_CPUSAVER_TIMER_DWORD 78
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#define D101S_CPUSAVER_BUNDLE_DWORD 67
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#define D101S_CPUSAVER_MIN_SIZE_DWORD 128
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#define D101S_RCVBUNDLE_UCODE \
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{\
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0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
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0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
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0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
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0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
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0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
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0x00308000, 0x00100610, 0x00100561, 0x000E0408, \
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0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
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0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
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0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
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0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
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0x003A047E, 0x00044010, 0x00380819, 0x00000000, \
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0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
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0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
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0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
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0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
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0x00101313, 0x00380700, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
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0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
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0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
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0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
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0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
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0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
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0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
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0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
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0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
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0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00130831, \
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0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
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0x00041000, 0x00010004, 0x00380700 \
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}
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/********************************************************/
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/* Micro code for the 8086:1229 Rev F/10 */
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/********************************************************/
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/* Parameter values for the D102 E-step */
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#define D102_E_CPUSAVER_TIMER_DWORD 42
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#define D102_E_CPUSAVER_BUNDLE_DWORD 54
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#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
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#define D102_E_RCVBUNDLE_UCODE \
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{\
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0x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
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0x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
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0x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
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0x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
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0x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
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0x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
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0x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
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0x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
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0x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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}
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static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
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{
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int i;
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static const u32 ucode[UCODE_SIZE] = {
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/* NFS packets are misinterpreted as TCO packets and
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* incorrectly routed to the BMC over SMBus. This
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* microcode patch checks the fragmented IP bit in the
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* NFS/UDP header to distinguish between NFS and TCO. */
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0x0EF70E36, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF,
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0x1FFF1FFF, 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000,
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0x00906EFD, 0x00900EFD, 0x00E00EF8,
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};
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/* *INDENT-OFF* */
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static struct {
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u32 ucode[UCODE_SIZE + 1];
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u8 mac;
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u8 timer_dword;
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u8 bundle_dword;
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u8 min_size_dword;
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} ucode_opts[] = {
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{ D101M_B_RCVBUNDLE_UCODE,
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mac_82559_D101M,
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D101M_CPUSAVER_TIMER_DWORD,
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D101M_CPUSAVER_BUNDLE_DWORD,
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D101M_CPUSAVER_MIN_SIZE_DWORD },
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{ D101S_RCVBUNDLE_UCODE,
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mac_82559_D101S,
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D101S_CPUSAVER_TIMER_DWORD,
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D101S_CPUSAVER_BUNDLE_DWORD,
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D101S_CPUSAVER_MIN_SIZE_DWORD },
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{ D102_E_RCVBUNDLE_UCODE,
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mac_82551_F,
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D102_E_CPUSAVER_TIMER_DWORD,
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D102_E_CPUSAVER_BUNDLE_DWORD,
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D102_E_CPUSAVER_MIN_SIZE_DWORD },
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{ D102_E_RCVBUNDLE_UCODE,
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mac_82551_10,
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D102_E_CPUSAVER_TIMER_DWORD,
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D102_E_CPUSAVER_BUNDLE_DWORD,
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D102_E_CPUSAVER_MIN_SIZE_DWORD },
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{ {0}, 0, 0, 0, 0}
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}, *opts;
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/* *INDENT-ON* */
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#define BUNDLESMALL 1
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#define BUNDLEMAX 50
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#define INTDELAY 15000
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opts = ucode_opts;
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/* do not load u-code for ICH devices */
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if (nic->flags & ich)
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return;
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/* Search for ucode match against h/w rev_id */
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while (opts->mac) {
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if (nic->mac == opts->mac) {
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int i;
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u32 *ucode = opts->ucode;
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/* Insert user-tunable settings */
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ucode[opts->timer_dword] &= 0xFFFF0000;
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ucode[opts->timer_dword] |=
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(u16) INTDELAY;
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ucode[opts->bundle_dword] &= 0xFFFF0000;
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ucode[opts->bundle_dword] |= (u16) BUNDLEMAX;
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ucode[opts->min_size_dword] &= 0xFFFF0000;
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ucode[opts->min_size_dword] |=
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(BUNDLESMALL) ? 0xFFFF : 0xFF80;
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if(nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
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for(i = 0; i < UCODE_SIZE; i++)
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cb->u.ucode[i] = cpu_to_le32(ucode[i]);
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cb->command = cpu_to_le16(cb_ucode);
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} else
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return;
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}
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opts++;
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}
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cb->command = cpu_to_le16(cb_nop);
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}
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@ -1307,14 +1496,15 @@ static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
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{
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cb->command = nic->tx_command;
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/* interrupt every 16 packets regardless of delay */
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if((nic->cbs_avail & ~15) == nic->cbs_avail) cb->command |= cb_i;
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if((nic->cbs_avail & ~15) == nic->cbs_avail)
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cb->command |= cpu_to_le16(cb_i);
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cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
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cb->u.tcb.tcb_byte_count = 0;
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cb->u.tcb.threshold = nic->tx_threshold;
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cb->u.tcb.tbd_count = 1;
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cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
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skb->data, skb->len, PCI_DMA_TODEVICE));
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// check for mapping failure?
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/* check for mapping failure? */
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cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
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}
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@ -1539,7 +1729,7 @@ static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
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/* Don't indicate if hardware indicates errors */
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nic->net_stats.rx_dropped++;
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dev_kfree_skb_any(skb);
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} else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
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} else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
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/* Don't indicate oversized frames */
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nic->rx_over_length_errors++;
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nic->net_stats.rx_dropped++;
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@ -1706,6 +1896,7 @@ static int e100_poll(struct net_device *netdev, int *budget)
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static void e100_netpoll(struct net_device *netdev)
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{
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struct nic *nic = netdev_priv(netdev);
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e100_disable_irq(nic);
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e100_intr(nic->pdev->irq, netdev, NULL);
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e100_tx_clean(nic);
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@ -2108,6 +2299,8 @@ static void e100_diag_test(struct net_device *netdev,
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}
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for(i = 0; i < E100_TEST_LEN; i++)
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test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
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msleep_interruptible(4 * 1000);
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}
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static int e100_phys_id(struct net_device *netdev, u32 data)
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