tile PCI RC: support I/O space access
To enable this functionality, configure CONFIG_TILE_PCI_IO. Without this flag, the kernel still assigns I/O address ranges to the devices, but no TRIO resource and mapping support is provided. We assign disjoint I/O address ranges to separate PCIe domains. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
parent
a3c4f2fb26
commit
cf89c4262b
4 changed files with 257 additions and 18 deletions
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@ -396,6 +396,16 @@ config NO_IOMEM
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config NO_IOPORT
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def_bool !PCI
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config TILE_PCI_IO
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bool "PCI I/O space support"
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default n
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depends on PCI
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depends on TILEGX
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---help---
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Enable PCI I/O space support on TILEGx. Since the PCI I/O space
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is used by few modern PCIe endpoint devices, its support is disabled
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by default to save the TRIO PIO Region resource for other purposes.
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source "drivers/pci/Kconfig"
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config TILE_USB
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@ -19,7 +19,8 @@
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#include <linux/bug.h>
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#include <asm/page.h>
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#define IO_SPACE_LIMIT 0xfffffffful
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/* Maximum PCI I/O space address supported. */
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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@ -281,8 +282,108 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
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#endif
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#if CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO)
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static inline u8 inb(unsigned long addr)
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{
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return readb((volatile void __iomem *) addr);
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}
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static inline u16 inw(unsigned long addr)
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{
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return readw((volatile void __iomem *) addr);
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}
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static inline u32 inl(unsigned long addr)
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{
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return readl((volatile void __iomem *) addr);
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}
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static inline void outb(u8 b, unsigned long addr)
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{
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writeb(b, (volatile void __iomem *) addr);
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}
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static inline void outw(u16 b, unsigned long addr)
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{
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writew(b, (volatile void __iomem *) addr);
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}
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static inline void outl(u32 b, unsigned long addr)
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{
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writel(b, (volatile void __iomem *) addr);
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}
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static inline void insb(unsigned long addr, void *buffer, int count)
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{
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if (count) {
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u8 *buf = buffer;
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do {
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u8 x = inb(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insw(unsigned long addr, void *buffer, int count)
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{
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if (count) {
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u16 *buf = buffer;
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do {
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u16 x = inw(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insl(unsigned long addr, void *buffer, int count)
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{
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if (count) {
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u32 *buf = buffer;
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do {
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u32 x = inl(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void outsb(unsigned long addr, const void *buffer, int count)
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{
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if (count) {
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const u8 *buf = buffer;
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do {
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outb(*buf++, addr);
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} while (--count);
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}
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}
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static inline void outsw(unsigned long addr, const void *buffer, int count)
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{
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if (count) {
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const u16 *buf = buffer;
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do {
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outw(*buf++, addr);
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} while (--count);
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}
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}
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static inline void outsl(unsigned long addr, const void *buffer, int count)
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{
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if (count) {
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const u32 *buf = buffer;
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do {
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outl(*buf++, addr);
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} while (--count);
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}
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}
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extern void __iomem *ioport_map(unsigned long port, unsigned int len);
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extern void ioport_unmap(void __iomem *addr);
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#else
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/*
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* The Tile architecture does not support IOPORT, even with PCI.
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* The TilePro architecture does not support IOPORT, even with PCI.
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* Unfortunately we can't yet simply not declare these methods,
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* since some generic code that compiles into the kernel, but
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* we never run, uses them unconditionally.
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@ -290,7 +391,12 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
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static inline long ioport_panic(void)
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{
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#ifdef __tilegx__
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panic("PCI IO space support is disabled. Configure the kernel with"
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" CONFIG_TILE_PCI_IO to enable it");
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#else
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panic("inb/outb and friends do not exist on tile");
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#endif
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return 0;
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}
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@ -335,13 +441,6 @@ static inline void outl(u32 b, unsigned long addr)
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ioport_panic();
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}
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#define inb_p(addr) inb(addr)
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#define inw_p(addr) inw(addr)
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#define inl_p(addr) inl(addr)
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#define outb_p(x, addr) outb((x), (addr))
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#define outw_p(x, addr) outw((x), (addr))
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#define outl_p(x, addr) outl((x), (addr))
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static inline void insb(unsigned long addr, void *buffer, int count)
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{
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ioport_panic();
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@ -372,6 +471,15 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
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ioport_panic();
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}
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#endif /* CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO) */
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#define inb_p(addr) inb(addr)
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#define inw_p(addr) inw(addr)
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#define inl_p(addr) inl(addr)
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#define outb_p(x, addr) outb((x), (addr))
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#define outw_p(x, addr) outw((x), (addr))
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#define outl_p(x, addr) outl((x), (addr))
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#define ioread16be(addr) be16_to_cpu(ioread16(addr))
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#define ioread32be(addr) be32_to_cpu(ioread32(addr))
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#define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
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@ -144,6 +144,10 @@ struct pci_controller {
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int pio_mem_index; /* PIO region index for memory access */
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#ifdef CONFIG_TILE_PCI_IO
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int pio_io_index; /* PIO region index for I/O space access */
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#endif
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/*
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* Mem-Map regions for all the memory controllers so that Linux can
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* map all of its physical memory space to the PCI bus.
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@ -153,6 +157,10 @@ struct pci_controller {
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int index; /* PCI domain number */
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struct pci_bus *root_bus;
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/* PCI I/O space resource for this controller. */
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struct resource io_space;
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char io_space_name[32];
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/* PCI memory space resource for this controller. */
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struct resource mem_space;
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char mem_space_name[32];
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@ -210,7 +218,8 @@ static inline int pcibios_assign_all_busses(void)
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}
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#define PCIBIOS_MIN_MEM 0
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#define PCIBIOS_MIN_IO 0
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/* Minimum PCI I/O address, starting at the page boundary. */
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#define PCIBIOS_MIN_IO PAGE_SIZE
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/* Use any cpu for PCI. */
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#define cpumask_of_pcibus(bus) cpu_online_mask
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@ -77,6 +77,9 @@ static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
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/* Default number of seconds that the PCIe RC port probe can be delayed. */
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#define DEFAULT_RC_DELAY 10
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/* The PCI I/O space size in each PCI domain. */
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#define IO_SPACE_SIZE 0x10000
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/* Array of the PCIe ports configuration info obtained from the BIB. */
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struct pcie_port_property pcie_ports[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
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@ -421,6 +424,17 @@ int __init tile_pci_init(void)
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controller->index = i;
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controller->ops = &tile_cfg_ops;
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controller->io_space.start = PCIBIOS_MIN_IO +
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(i * IO_SPACE_SIZE);
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controller->io_space.end = controller->io_space.start +
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IO_SPACE_SIZE - 1;
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BUG_ON(controller->io_space.end > IO_SPACE_LIMIT);
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controller->io_space.flags = IORESOURCE_IO;
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snprintf(controller->io_space_name,
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sizeof(controller->io_space_name),
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"PCI I/O domain %d", i);
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controller->io_space.name = controller->io_space_name;
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/*
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* The PCI memory resource is located above the PA space.
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* For every host bridge, the BAR window or the MMIO aperture
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@ -861,17 +875,16 @@ int __init pcibios_init(void)
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/*
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* The PCI memory resource is located above the PA space.
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* The memory range for the PCI root bus should not overlap
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* with the physical RAM
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* with the physical RAM.
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*/
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pci_add_resource_offset(&resources, &controller->mem_space,
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controller->mem_offset);
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pci_add_resource(&resources, &controller->io_space);
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controller->first_busno = next_busno;
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bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
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controller, &resources);
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controller->root_bus = bus;
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next_busno = bus->busn_res.end + 1;
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}
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/* Do machine dependent PCI interrupt routing */
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@ -915,9 +928,9 @@ int __init pcibios_init(void)
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pci_controllers[i].mem_resources[0] =
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*next_bus->resource[0];
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pci_controllers[i].mem_resources[1] =
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*next_bus->resource[1];
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*next_bus->resource[1];
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pci_controllers[i].mem_resources[2] =
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*next_bus->resource[2];
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*next_bus->resource[2];
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break;
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}
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@ -967,6 +980,39 @@ int __init pcibios_init(void)
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continue;
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}
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#ifdef CONFIG_TILE_PCI_IO
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/*
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* Alloc a PIO region for PCI I/O space access for each RC port.
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*/
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ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
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if (ret < 0) {
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pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, "
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"give up\n", controller->trio_index,
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controller->mac);
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continue;
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}
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controller->pio_io_index = ret;
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/*
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* For PIO IO, the bus_address_hi parameter is hard-coded 0
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* because PCI I/O address space is 32-bit.
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*/
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ret = gxio_trio_init_pio_region_aux(trio_context,
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controller->pio_io_index,
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controller->mac,
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0,
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HV_TRIO_PIO_FLAG_IO_SPACE);
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if (ret < 0) {
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pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, "
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"give up\n", controller->trio_index,
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controller->mac);
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continue;
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}
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#endif
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/*
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* Configure a Mem-Map region for each memory controller so
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* that Linux can map all of its PA space to the PCI bus.
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@ -1052,8 +1098,7 @@ char *pcibios_setup(char *str)
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/*
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* Enable memory address decoding, as appropriate, for the
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* device described by the 'dev' struct. The I/O decoding
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* is disabled, though the TILE-Gx supports I/O addressing.
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* device described by the 'dev' struct.
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*
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* This is called from the generic PCI layer, and can be called
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* for bridges or endpoints.
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@ -1134,10 +1179,77 @@ void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
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* We need to keep the PCI bus address's in-page offset in the VA.
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*/
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return iorpc_ioremap(trio_fd, offset, size) +
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(phys_addr & (PAGE_SIZE - 1));
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(start & (PAGE_SIZE - 1));
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}
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EXPORT_SYMBOL(ioremap);
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#ifdef CONFIG_TILE_PCI_IO
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/* Map a PCI I/O address into VA space. */
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void __iomem *ioport_map(unsigned long port, unsigned int size)
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{
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struct pci_controller *controller = NULL;
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resource_size_t bar_start;
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resource_size_t bar_end;
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resource_size_t offset;
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resource_size_t start;
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resource_size_t end;
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int trio_fd;
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int i;
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start = port;
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end = port + size - 1;
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/*
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* In the following, each PCI controller's mem_resources[0]
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* represents its PCI I/O resource. By searching port in each
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* controller's mem_resources[0], we can determine the controller
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* that should accept the PCI I/O access.
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*/
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for (i = 0; i < num_rc_controllers; i++) {
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/*
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* Skip controllers that are not properly initialized or
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* have down links.
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*/
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if (pci_controllers[i].root_bus == NULL)
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continue;
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bar_start = pci_controllers[i].mem_resources[0].start;
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bar_end = pci_controllers[i].mem_resources[0].end;
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if ((start >= bar_start) && (end <= bar_end)) {
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controller = &pci_controllers[i];
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goto got_it;
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}
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}
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if (controller == NULL)
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return NULL;
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got_it:
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trio_fd = controller->trio->fd;
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/* Convert the resource start to the bus address offset. */
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port -= controller->io_space.start;
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offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
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/*
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* We need to keep the PCI bus address's in-page offset in the VA.
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*/
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return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
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}
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EXPORT_SYMBOL(ioport_map);
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void ioport_unmap(void __iomem *addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(ioport_unmap);
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#endif
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
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{
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iounmap(addr);
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Loading…
Reference in a new issue