mfd: rtsx: Add support for rts522A
rts522a(rts5227s) is derived from rts5227, and mainly same with rts5227. Add it to file mfd/rts5227.c to support this chip. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Micky Ching
Lee Jones
parent
6f44b14870
commit
ce6a5acc93
5 changed files with 93 additions and 5 deletions
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@ -736,9 +736,10 @@ config MFD_RTSX_PCI
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select MFD_CORE
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help
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This supports for Realtek PCI-Express card reader including rts5209,
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rts5229, rtl8411, etc. Realtek card reader supports access to many
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types of memory cards, such as Memory Stick, Memory Stick Pro,
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Secure Digital and MultiMediaCard.
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rts5227, rts522A, rts5229, rts5249, rts524A, rts525A, rtl8411, etc.
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Realtek card reader supports access to many types of memory cards,
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such as Memory Stick, Memory Stick Pro, Secure Digital and
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MultiMediaCard.
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config MFD_RT5033
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tristate "Richtek RT5033 Power Management IC"
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@ -26,6 +26,14 @@
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#include "rtsx_pcr.h"
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static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
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{
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u8 val;
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rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
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return val & 0x0F;
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}
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static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
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{
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u8 driving_3v3[4][3] = {
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@ -88,7 +96,7 @@ static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
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if (pm_state == HOST_ENTER_S3)
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rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10);
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rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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}
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@ -121,7 +129,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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@ -294,8 +302,73 @@ void rts5227_init_params(struct rtsx_pcr *pcr)
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pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
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pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
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pcr->ic_version = rts5227_get_ic_version(pcr);
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pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
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pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
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pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
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pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
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pcr->reg_pm_ctrl3 = PM_CTRL3;
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}
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static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
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{
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int err;
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err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
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0x00);
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if (err < 0)
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return err;
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if (is_version(pcr, 0x522A, IC_VER_A)) {
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err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
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PHY_RCR2_INIT_27S);
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if (err)
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return err;
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rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
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rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
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rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
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rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
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}
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return 0;
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}
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static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rts5227_extra_init_hw(pcr);
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rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
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FUNC_FORCE_UPME_XMT_DBG);
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rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
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rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
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rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
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return 0;
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}
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/* rts522a operations mainly derived from rts5227, except phy/hw init setting.
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*/
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static const struct pcr_ops rts522a_pcr_ops = {
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.fetch_vendor_settings = rts5227_fetch_vendor_settings,
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.extra_init_hw = rts522a_extra_init_hw,
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.optimize_phy = rts522a_optimize_phy,
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.turn_on_led = rts5227_turn_on_led,
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.turn_off_led = rts5227_turn_off_led,
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.enable_auto_blink = rts5227_enable_auto_blink,
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.disable_auto_blink = rts5227_disable_auto_blink,
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.card_power_on = rts5227_card_power_on,
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.card_power_off = rts5227_card_power_off,
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.switch_output_voltage = rts5227_switch_output_voltage,
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.cd_deglitch = NULL,
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.conv_clk_and_div_n = NULL,
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.force_power_down = rts5227_force_power_down,
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};
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void rts522a_init_params(struct rtsx_pcr *pcr)
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{
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rts5227_init_params(pcr);
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pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
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}
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@ -55,6 +55,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {
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{ PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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@ -1098,6 +1099,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
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rts5227_init_params(pcr);
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break;
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case 0x522A:
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rts522a_init_params(pcr);
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break;
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case 0x5249:
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rts5249_init_params(pcr);
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break;
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@ -27,6 +27,8 @@
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#define MIN_DIV_N_PCR 80
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#define MAX_DIV_N_PCR 208
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#define RTS522A_PM_CTRL3 0xFF7E
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#define RTS524A_PME_FORCE_CTL 0xFF78
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#define RTS524A_PM_CTRL3 0xFF7E
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@ -38,6 +40,7 @@ void rts5229_init_params(struct rtsx_pcr *pcr);
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void rtl8411_init_params(struct rtsx_pcr *pcr);
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void rtl8402_init_params(struct rtsx_pcr *pcr);
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void rts5227_init_params(struct rtsx_pcr *pcr);
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void rts522a_init_params(struct rtsx_pcr *pcr);
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void rts5249_init_params(struct rtsx_pcr *pcr);
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void rts524a_init_params(struct rtsx_pcr *pcr);
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void rts525a_init_params(struct rtsx_pcr *pcr);
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@ -589,6 +589,7 @@
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#define FORCE_ASPM_NO_ASPM 0x00
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#define PM_CLK_FORCE_CTL 0xFE58
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#define FUNC_FORCE_CTL 0xFE59
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#define FUNC_FORCE_UPME_XMT_DBG 0x02
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#define PERST_GLITCH_WIDTH 0xFE5C
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#define CHANGE_LINK_STATE 0xFE5B
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#define RESET_LOAD_REG 0xFE5E
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@ -712,6 +713,7 @@
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#define PHY_RCR1 0x02
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#define PHY_RCR1_ADP_TIME_4 0x0400
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#define PHY_RCR1_VCO_COARSE 0x001F
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#define PHY_RCR1_INIT_27S 0x0A1F
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#define PHY_SSCCR2 0x02
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#define PHY_SSCCR2_PLL_NCODE 0x0A00
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#define PHY_SSCCR2_TIME0 0x001C
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@ -724,6 +726,7 @@
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#define PHY_RCR2_FREQSEL_12 0x0040
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#define PHY_RCR2_CDR_SC_12P 0x0010
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#define PHY_RCR2_CALIB_LATE 0x0002
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#define PHY_RCR2_INIT_27S 0xC152
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#define PHY_SSCCR3 0x03
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#define PHY_SSCCR3_STEP_IN 0x2740
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#define PHY_SSCCR3_CHECK_DELAY 0x0008
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@ -800,12 +803,14 @@
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#define PHY_ANA1A_RXT_BIST 0x0500
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#define PHY_ANA1A_TXR_BIST 0x0040
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#define PHY_ANA1A_REV 0x0006
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#define PHY_FLD0_INIT_27S 0x2546
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#define PHY_FLD1 0x1B
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#define PHY_FLD2 0x1C
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#define PHY_FLD3 0x1D
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#define PHY_FLD3_TIMER_4 0x0800
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#define PHY_FLD3_TIMER_6 0x0020
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#define PHY_FLD3_RXDELINK 0x0004
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#define PHY_FLD3_INIT_27S 0x0004
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#define PHY_ANA1D 0x1D
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#define PHY_ANA1D_DEBUG_ADDR 0x0004
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#define _PHY_FLD0 0x1D
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@ -824,6 +829,7 @@
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#define PHY_FLD4_BER_COUNT 0x00E0
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#define PHY_FLD4_BER_TIMER 0x000A
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#define PHY_FLD4_BER_CHK_EN 0x0001
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#define PHY_FLD4_INIT_27S 0x5C7F
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#define PHY_DIG1E 0x1E
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#define PHY_DIG1E_REV 0x4000
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#define PHY_DIG1E_D0_X_D1 0x1000
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