[MTD] Add support for NDFC NAND controller
NDFC NAND Flash controller is embedded in PPC EP44x SoCs. Add platform driver based support. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner
parent
41796c2ea9
commit
ce4c61f184
4 changed files with 390 additions and 0 deletions
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@ -129,6 +129,12 @@ config MTD_NAND_S3C2410_HWECC
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currently not be able to switch to software, as there is no
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implementation for ECC method used by the S3C2410
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config MTD_NAND_NDFC
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tristate "NDFC NanD Flash Controller"
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depends on MTD_NAND && 44x
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help
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NDFC Nand Flash Controllers are integrated in EP44x SoCs
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config MTD_NAND_DISKONCHIP
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tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
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depends on MTD_NAND && EXPERIMENTAL
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@ -21,5 +21,6 @@ obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
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obj-$(CONFIG_MTD_NAND_TS7250) += ts7250.o
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obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
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obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
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obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
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nand-objs = nand_base.o nand_bbt.o
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317
drivers/mtd/nand/ndfc.c
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317
drivers/mtd/nand/ndfc.c
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@ -0,0 +1,317 @@
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/*
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* drivers/mtd/ndfc.c
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*
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* Overview:
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* Platform independend driver for NDFC (NanD Flash Controller)
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* integrated into EP440 cores
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*
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* Author: Thomas Gleixner
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*
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* Copyright 2006 IBM
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/ndfc.h>
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#include <linux/mtd/ubi.h>
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#include <linux/mtd/mtd.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/ibm44x.h>
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struct ndfc_nand_mtd {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct platform_nand_chip *pl_chip;
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};
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static struct ndfc_nand_mtd ndfc_mtd[NDFC_MAX_BANKS];
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struct ndfc_controller {
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void __iomem *ndfcbase;
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struct nand_hw_control ndfc_control;
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atomic_t childs_active;
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};
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static struct ndfc_controller ndfc_ctrl;
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static void ndfc_select_chip(struct mtd_info *mtd, int chip)
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{
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uint32_t ccr;
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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struct nand_chip *nandchip = mtd->priv;
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struct ndfc_nand_mtd *nandmtd = nandchip->priv;
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struct platform_nand_chip *pchip = nandmtd->pl_chip;
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ccr = __raw_readl(ndfc->ndfcbase + NDFC_CCR);
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if (chip >= 0) {
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ccr &= ~NDFC_CCR_BS_MASK;
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ccr |= NDFC_CCR_BS(chip + pchip->chip_offset);
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} else
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ccr |= NDFC_CCR_RESET_CE;
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writel(ccr, ndfc->ndfcbase + NDFC_CCR);
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}
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static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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struct nand_chip *chip = mtd->priv;
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switch (cmd) {
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case NAND_CTL_SETCLE:
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chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_CMD;
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break;
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case NAND_CTL_SETALE:
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chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_ALE;
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break;
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default:
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chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
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break;
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}
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}
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static int ndfc_ready(struct mtd_info *mtd)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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return __raw_readl(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
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}
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static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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uint32_t ccr;
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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ccr = __raw_readl(ndfc->ndfcbase + NDFC_CCR);
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ccr |= NDFC_CCR_RESET_ECC;
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__raw_writel(ccr, ndfc->ndfcbase + NDFC_CCR);
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wmb();
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}
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static int ndfc_calculate_ecc(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t ecc;
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uint8_t *p = (uint8_t *)&ecc;
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wmb();
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ecc = __raw_readl(ndfc->ndfcbase + NDFC_ECC);
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ecc_code[0] = p[1];
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ecc_code[1] = p[2];
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ecc_code[2] = p[3];
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return 0;
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}
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/*
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* Speedups for buffer read/write/verify
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*
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* NDFC allows 32bit read/write of data. So we can speed up the buffer
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* functions. No further checking, as nand_base will always read/write
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* page aligned.
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*/
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static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t *p = (uint32_t *) buf;
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for(;len > 0; len -= 4)
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*p++ = __raw_readl(ndfc->ndfcbase + NDFC_DATA);
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}
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static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t *p = (uint32_t *) buf;
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for(;len > 0; len -= 4)
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__raw_writel(*p++, ndfc->ndfcbase + NDFC_DATA);
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}
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static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t *p = (uint32_t *) buf;
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for(;len > 0; len -= 4)
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if (*p++ != __raw_readl(ndfc->ndfcbase + NDFC_DATA))
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return -EFAULT;
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return 0;
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}
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/*
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* Initialize chip structure
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*/
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static void ndfc_chip_init(struct ndfc_nand_mtd *mtd)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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struct nand_chip *chip = &mtd->chip;
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chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
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chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
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chip->hwcontrol = ndfc_hwcontrol;
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chip->dev_ready = ndfc_ready;
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chip->select_chip = ndfc_select_chip;
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chip->chip_delay = 50;
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chip->priv = mtd;
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chip->options = mtd->pl_chip->options;
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chip->controller = &ndfc->ndfc_control;
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chip->read_buf = ndfc_read_buf;
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chip->write_buf = ndfc_write_buf;
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chip->verify_buf = ndfc_verify_buf;
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chip->correct_data = nand_correct_data;
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chip->enable_hwecc = ndfc_enable_hwecc;
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chip->calculate_ecc = ndfc_calculate_ecc;
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chip->eccmode = NAND_ECC_HW3_256;
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chip->autooob = mtd->pl_chip->autooob;
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mtd->mtd.priv = chip;
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mtd->mtd.owner = THIS_MODULE;
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}
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static int ndfc_chip_probe(struct platform_device *pdev)
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{
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int rc;
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struct platform_nand_chip *nc = pdev->dev.platform_data;
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struct ndfc_chip_settings *settings = nc->priv;
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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struct ndfc_nand_mtd *nandmtd;
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if (nc->chip_offset >= NDFC_MAX_BANKS || nc->nr_chips > NDFC_MAX_BANKS)
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return -EINVAL;
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/* Set the bank settings */
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__raw_writel(settings->bank_settings,
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ndfc->ndfcbase + NDFC_BCFG0 + (nc->chip_offset << 2));
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nandmtd = &ndfc_mtd[pdev->id];
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if (nandmtd->pl_chip)
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return -EBUSY;
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nandmtd->pl_chip = nc;
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ndfc_chip_init(nandmtd);
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/* Scan for chips */
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if (nand_scan(&nandmtd->mtd, nc->nr_chips)) {
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nandmtd->pl_chip = NULL;
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return -ENODEV;
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}
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#ifdef CONFIG_MTD_PARTITIONS
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printk("Number of partitions %d\n", nc->nr_partitions);
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if (nc->nr_partitions) {
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struct mtd_info *mtd_ubi;
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nc->partitions[NAND_PARTS_CONTENT_IDX].mtdp = &mtd_ubi;
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add_mtd_device(&nandmtd->mtd); /* for testing */
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add_mtd_partitions(&nandmtd->mtd,
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nc->partitions,
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nc->nr_partitions);
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add_mtd_device(mtd_ubi);
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} else
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#else
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add_mtd_device(&nandmtd->mtd);
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#endif
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atomic_inc(&ndfc->childs_active);
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return 0;
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}
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static int ndfc_chip_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static int ndfc_nand_probe(struct platform_device *pdev)
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{
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struct platform_nand_ctrl *nc = pdev->dev.platform_data;
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struct ndfc_controller_settings *settings = nc->priv;
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struct resource *res = pdev->resource;
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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unsigned long long phys = NDFC_PHYSADDR_OFFS | res->start;
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ndfc->ndfcbase = ioremap64(phys, res->end - res->start + 1);
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if (!ndfc->ndfcbase) {
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printk(KERN_ERR "NDFC: ioremap failed\n");
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return -EIO;
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}
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__raw_writel(settings->ccr_settings, ndfc->ndfcbase + NDFC_CCR);
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spin_lock_init(&ndfc->ndfc_control.lock);
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init_waitqueue_head(&ndfc->ndfc_control.wq);
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platform_set_drvdata(pdev, ndfc);
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printk("NDFC NAND Driver initialized. Chip-Rev: 0x%08x\n",
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__raw_readl(ndfc->ndfcbase + NDFC_REVID));
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return 0;
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}
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static int ndfc_nand_remove(struct platform_device *pdev)
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{
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struct ndfc_controller *ndfc = platform_get_drvdata(pdev);
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if (atomic_read(&ndfc->childs_active))
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return -EBUSY;
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if (ndfc) {
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platform_set_drvdata(pdev, NULL);
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iounmap(ndfc_ctrl.ndfcbase);
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ndfc_ctrl.ndfcbase = NULL;
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}
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return 0;
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}
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/* driver device registration */
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static struct platform_driver ndfc_chip_driver = {
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.probe = ndfc_chip_probe,
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.remove = ndfc_chip_remove,
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.driver = {
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.name = "ndfc-chip",
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.owner = THIS_MODULE,
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},
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};
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static struct platform_driver ndfc_nand_driver = {
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.probe = ndfc_nand_probe,
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.remove = ndfc_nand_remove,
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.driver = {
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.name = "ndfc-nand",
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.owner = THIS_MODULE,
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},
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};
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static int __init ndfc_nand_init(void)
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{
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int ret = platform_driver_register(&ndfc_nand_driver);
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if (!ret)
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ret = platform_driver_register(&ndfc_chip_driver);
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return ret;
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}
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static void __exit ndfc_nand_exit(void)
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{
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platform_driver_unregister(&ndfc_chip_driver);
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platform_driver_unregister(&ndfc_nand_driver);
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}
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module_init(ndfc_nand_init);
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module_exit(ndfc_nand_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
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MODULE_DESCRIPTION("Platform driver for NDFC");
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66
include/linux/mtd/ndfc.h
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66
include/linux/mtd/ndfc.h
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@ -0,0 +1,66 @@
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/*
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* linux/include/linux/mtd/ndfc.h
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*
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* Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Info:
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* Contains defines, datastructures for ndfc nand controller
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*
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*/
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#ifndef __LINUX_MTD_NDFC_H
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#define __LINUX_MTD_NDFC_H
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/* NDFC Register definitions */
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#define NDFC_CMD 0x00
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#define NDFC_ALE 0x04
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#define NDFC_DATA 0x08
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#define NDFC_ECC 0x10
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#define NDFC_BCFG0 0x30
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#define NDFC_BCFG1 0x34
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#define NDFC_BCFG2 0x38
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#define NDFC_BCFG3 0x3c
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#define NDFC_CCR 0x40
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#define NDFC_STAT 0x44
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#define NDFC_HWCTL 0x48
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#define NDFC_REVID 0x50
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#define NDFC_STAT_IS_READY 0x01000000
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#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */
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#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
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#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */
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#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */
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#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */
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#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */
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#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */
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#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */
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#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
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#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
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#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
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#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
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#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */
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#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */
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#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */
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#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */
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#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */
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#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */
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#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */
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#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */
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#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
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#define NDFC_MAX_BANKS 4
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struct ndfc_controller_settings {
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uint32_t ccr_settings;
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};
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struct ndfc_chip_settings {
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uint32_t bank_settings;
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};
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#endif
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