Merge branch 'topic/irq' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap into mfd/da9052
This commit is contained in:
Mark Brown
commit
ce37954e93
4 changed files with 354 additions and 0 deletions
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@ -13,3 +13,6 @@ config REGMAP_I2C
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config REGMAP_SPI
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tristate
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config REGMAP_IRQ
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bool
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@ -2,3 +2,4 @@ obj-$(CONFIG_REGMAP) += regmap.o regcache.o regcache-indexed.o regcache-rbtree.o
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obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
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obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
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obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
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obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o
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302
drivers/base/regmap/regmap-irq.c
Normal file
302
drivers/base/regmap/regmap-irq.c
Normal file
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@ -0,0 +1,302 @@
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/*
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* regmap based irq_chip
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*
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* Copyright 2011 Wolfson Microelectronics plc
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*
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/export.h>
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#include <linux/regmap.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include "internal.h"
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struct regmap_irq_chip_data {
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struct mutex lock;
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struct regmap *map;
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struct regmap_irq_chip *chip;
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int irq_base;
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void *status_reg_buf;
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unsigned int *status_buf;
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unsigned int *mask_buf;
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unsigned int *mask_buf_def;
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};
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static inline const
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struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
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int irq)
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{
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return &data->chip->irqs[irq - data->irq_base];
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}
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static void regmap_irq_lock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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mutex_lock(&d->lock);
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}
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static void regmap_irq_sync_unlock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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int i, ret;
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/*
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* If there's been a change in the mask write it back to the
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* hardware. We rely on the use of the regmap core cache to
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* suppress pointless writes.
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*/
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for (i = 0; i < d->chip->num_regs; i++) {
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ret = regmap_update_bits(d->map, d->chip->mask_base + i,
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d->mask_buf_def[i], d->mask_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev, "Failed to sync masks in %x\n",
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d->chip->mask_base + i);
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}
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mutex_unlock(&d->lock);
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}
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static void regmap_irq_enable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
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d->mask_buf[irq_data->reg_offset] &= ~irq_data->mask;
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}
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static void regmap_irq_disable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
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d->mask_buf[irq_data->reg_offset] |= irq_data->mask;
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}
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static struct irq_chip regmap_irq_chip = {
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.name = "regmap",
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.irq_bus_lock = regmap_irq_lock,
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.irq_bus_sync_unlock = regmap_irq_sync_unlock,
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.irq_disable = regmap_irq_disable,
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.irq_enable = regmap_irq_enable,
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};
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static irqreturn_t regmap_irq_thread(int irq, void *d)
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{
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struct regmap_irq_chip_data *data = d;
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struct regmap_irq_chip *chip = data->chip;
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struct regmap *map = data->map;
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int ret, i;
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u8 *buf8 = data->status_reg_buf;
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u16 *buf16 = data->status_reg_buf;
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u32 *buf32 = data->status_reg_buf;
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bool handled = false;
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ret = regmap_bulk_read(map, chip->status_base, data->status_reg_buf,
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chip->num_regs);
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if (ret != 0) {
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dev_err(map->dev, "Failed to read IRQ status: %d\n", ret);
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return IRQ_NONE;
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}
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/*
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* Ignore masked IRQs and ack if we need to; we ack early so
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* there is no race between handling and acknowleding the
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* interrupt. We assume that typically few of the interrupts
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* will fire simultaneously so don't worry about overhead from
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* doing a write per register.
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*/
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for (i = 0; i < data->chip->num_regs; i++) {
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switch (map->format.val_bytes) {
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case 1:
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data->status_buf[i] = buf8[i];
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break;
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case 2:
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data->status_buf[i] = buf16[i];
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break;
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case 4:
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data->status_buf[i] = buf32[i];
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break;
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default:
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BUG();
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return IRQ_NONE;
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}
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data->status_buf[i] &= ~data->mask_buf[i];
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if (data->status_buf[i] && chip->ack_base) {
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ret = regmap_write(map, chip->ack_base + i,
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data->status_buf[i]);
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if (ret != 0)
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dev_err(map->dev, "Failed to ack 0x%x: %d\n",
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chip->ack_base + i, ret);
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}
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}
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for (i = 0; i < chip->num_irqs; i++) {
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if (data->status_buf[chip->irqs[i].reg_offset] &
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chip->irqs[i].mask) {
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handle_nested_irq(data->irq_base + i);
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handled = true;
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}
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}
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if (handled)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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/**
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* regmap_add_irq_chip(): Use standard regmap IRQ controller handling
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*
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* map: The regmap for the device.
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* irq: The IRQ the device uses to signal interrupts
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* irq_flags: The IRQF_ flags to use for the primary interrupt.
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* chip: Configuration for the interrupt controller.
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* data: Runtime data structure for the controller, allocated on success
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*
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* Returns 0 on success or an errno on failure.
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*
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* In order for this to be efficient the chip really should use a
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* register cache. The chip driver is responsible for restoring the
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* register values used by the IRQ controller over suspend and resume.
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*/
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int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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int irq_base, struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data)
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{
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struct regmap_irq_chip_data *d;
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int cur_irq, i;
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int ret = -ENOMEM;
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irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
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if (irq_base < 0) {
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dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
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irq_base);
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return irq_base;
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}
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d = kzalloc(sizeof(*d), GFP_KERNEL);
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if (!d)
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return -ENOMEM;
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d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->status_buf)
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goto err_alloc;
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d->status_reg_buf = kzalloc(map->format.val_bytes * chip->num_regs,
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GFP_KERNEL);
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if (!d->status_reg_buf)
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goto err_alloc;
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d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->mask_buf)
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goto err_alloc;
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d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->mask_buf_def)
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goto err_alloc;
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d->map = map;
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d->chip = chip;
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d->irq_base = irq_base;
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mutex_init(&d->lock);
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for (i = 0; i < chip->num_irqs; i++)
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d->mask_buf_def[chip->irqs[i].reg_offset]
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|= chip->irqs[i].mask;
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/* Mask all the interrupts by default */
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for (i = 0; i < chip->num_regs; i++) {
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d->mask_buf[i] = d->mask_buf_def[i];
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ret = regmap_write(map, chip->mask_base + i, d->mask_buf[i]);
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if (ret != 0) {
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dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
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chip->mask_base + i, ret);
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goto err_alloc;
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}
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}
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/* Register them with genirq */
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for (cur_irq = irq_base;
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cur_irq < chip->num_irqs + irq_base;
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cur_irq++) {
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irq_set_chip_data(cur_irq, d);
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irq_set_chip_and_handler(cur_irq, ®map_irq_chip,
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handle_edge_irq);
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irq_set_nested_thread(cur_irq, 1);
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/* ARM needs us to explicitly flag the IRQ as valid
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* and will set them noprobe when we do so. */
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#ifdef CONFIG_ARM
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set_irq_flags(cur_irq, IRQF_VALID);
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#else
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irq_set_noprobe(cur_irq);
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#endif
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}
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ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
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chip->name, d);
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if (ret != 0) {
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dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
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goto err_alloc;
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}
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return 0;
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err_alloc:
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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kfree(d->status_reg_buf);
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kfree(d->status_buf);
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kfree(d);
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return ret;
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}
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EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
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/**
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* regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
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*
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* @irq: Primary IRQ for the device
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* @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
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*/
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void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
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{
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if (!d)
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return;
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free_irq(irq, d);
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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kfree(d->status_reg_buf);
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kfree(d->status_buf);
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kfree(d);
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}
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EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
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/**
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* regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
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*
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* Useful for drivers to request their own IRQs.
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*
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* @data: regmap_irq controller to operate on.
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*/
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int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
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{
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return data->irq_base;
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}
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EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
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@ -144,4 +144,52 @@ int regcache_sync(struct regmap *map);
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void regcache_cache_only(struct regmap *map, bool enable);
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void regcache_cache_bypass(struct regmap *map, bool enable);
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/**
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* Description of an IRQ for the generic regmap irq_chip.
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*
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* @reg_offset: Offset of the status/mask register within the bank
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* @mask: Mask used to flag/control the register.
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*/
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struct regmap_irq {
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unsigned int reg_offset;
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unsigned int mask;
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};
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/**
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* Description of a generic regmap irq_chip. This is not intended to
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* handle every possible interrupt controller, but it should handle a
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* substantial proportion of those that are found in the wild.
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*
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* @name: Descriptive name for IRQ controller.
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*
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* @status_base: Base status register address.
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* @mask_base: Base mask register address.
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* @ack_base: Base ack address. If zero then the chip is clear on read.
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*
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* @num_regs: Number of registers in each control bank.
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* @irqs: Descriptors for individual IRQs. Interrupt numbers are
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* assigned based on the index in the array of the interrupt.
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* @num_irqs: Number of descriptors.
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*/
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struct regmap_irq_chip {
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const char *name;
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unsigned int status_base;
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unsigned int mask_base;
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unsigned int ack_base;
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int num_regs;
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const struct regmap_irq *irqs;
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int num_irqs;
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};
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struct regmap_irq_chip_data;
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int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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int irq_base, struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data);
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void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
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int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data);
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#endif
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