watchdog: MIPS: lantiq: implement OF support and minor fixes
Add support for OF. We also apply the following small fixes * reduce boiler plate by using devm_request_and_ioremap * sane error path for the clock * move LTQ_RST_CAUSE_WDTRST to a soc specific header file * add a message to show that the driver loaded Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Wim Van Sebroeck <wim@iguana.be> Cc: linux-watchdog@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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ceff2676b0
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3 changed files with 27 additions and 32 deletions
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@ -49,7 +49,6 @@ extern struct clk *clk_get_io(void);
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extern unsigned char ltq_boot_select(void);
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extern unsigned char ltq_boot_select(void);
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/* find out what caused the last cpu reset */
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/* find out what caused the last cpu reset */
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extern int ltq_reset_cause(void);
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extern int ltq_reset_cause(void);
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#define LTQ_RST_CAUSE_WDTRST 0x20
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOPORT_RESOURCE_END 0xffffffff
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@ -133,6 +133,8 @@ extern __iomem void *ltq_cgu_membase;
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#define LTQ_WDT_BASE_ADDR 0x1F8803F0
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#define LTQ_WDT_BASE_ADDR 0x1F8803F0
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#define LTQ_WDT_SIZE 0x10
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#define LTQ_WDT_SIZE 0x10
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#define LTQ_RST_CAUSE_WDTRST 0x20
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/* STP - serial to parallel conversion unit */
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/* STP - serial to parallel conversion unit */
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#define LTQ_STP_BASE_ADDR 0x1E100BB0
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#define LTQ_STP_BASE_ADDR 0x1E100BB0
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#define LTQ_STP_SIZE 0x40
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#define LTQ_STP_SIZE 0x40
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@ -13,14 +13,15 @@
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#include <linux/fs.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/watchdog.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/uaccess.h>
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#include <linux/uaccess.h>
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#include <linux/clk.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <lantiq.h>
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#include <lantiq_soc.h>
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/* Section 3.4 of the datasheet
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/*
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* Section 3.4 of the datasheet
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* The password sequence protects the WDT control register from unintended
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* The password sequence protects the WDT control register from unintended
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* write actions, which might cause malfunction of the WDT.
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* write actions, which might cause malfunction of the WDT.
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*
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*
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@ -70,7 +71,8 @@ ltq_wdt_disable(void)
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{
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{
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/* write the first password magic */
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/* write the first password magic */
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ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
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ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
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/* write the second password magic with no config
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/*
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* write the second password magic with no config
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* this turns the watchdog off
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* this turns the watchdog off
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*/
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*/
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ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR);
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ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR);
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@ -184,7 +186,7 @@ static struct miscdevice ltq_wdt_miscdev = {
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.fops = <q_wdt_fops,
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.fops = <q_wdt_fops,
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};
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};
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static int __init
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static int __devinit
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ltq_wdt_probe(struct platform_device *pdev)
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ltq_wdt_probe(struct platform_device *pdev)
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{
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -194,28 +196,27 @@ ltq_wdt_probe(struct platform_device *pdev)
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dev_err(&pdev->dev, "cannot obtain I/O memory region");
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dev_err(&pdev->dev, "cannot obtain I/O memory region");
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return -ENOENT;
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return -ENOENT;
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}
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}
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res = devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), dev_name(&pdev->dev));
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ltq_wdt_membase = devm_request_and_ioremap(&pdev->dev, res);
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if (!res) {
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dev_err(&pdev->dev, "cannot request I/O memory region");
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return -EBUSY;
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}
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ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!ltq_wdt_membase) {
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if (!ltq_wdt_membase) {
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dev_err(&pdev->dev, "cannot remap I/O memory region\n");
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dev_err(&pdev->dev, "cannot remap I/O memory region\n");
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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/* we do not need to enable the clock as it is always running */
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/* we do not need to enable the clock as it is always running */
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clk = clk_get(&pdev->dev, "io");
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clk = clk_get_io();
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WARN_ON(!clk);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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return -ENOENT;
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}
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ltq_io_region_clk_rate = clk_get_rate(clk);
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ltq_io_region_clk_rate = clk_get_rate(clk);
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clk_put(clk);
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clk_put(clk);
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/* find out if the watchdog caused the last reboot */
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if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
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if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
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ltq_wdt_bootstatus = WDIOF_CARDRESET;
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ltq_wdt_bootstatus = WDIOF_CARDRESET;
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dev_info(&pdev->dev, "Init done\n");
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return misc_register(<q_wdt_miscdev);
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return misc_register(<q_wdt_miscdev);
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}
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}
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@ -227,33 +228,26 @@ ltq_wdt_remove(struct platform_device *pdev)
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return 0;
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return 0;
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}
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}
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static const struct of_device_id ltq_wdt_match[] = {
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{ .compatible = "lantiq,wdt" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ltq_wdt_match);
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static struct platform_driver ltq_wdt_driver = {
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static struct platform_driver ltq_wdt_driver = {
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.probe = ltq_wdt_probe,
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.remove = __devexit_p(ltq_wdt_remove),
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.remove = __devexit_p(ltq_wdt_remove),
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.driver = {
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.driver = {
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.name = "ltq_wdt",
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.name = "wdt",
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.owner = THIS_MODULE,
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.owner = THIS_MODULE,
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.of_match_table = ltq_wdt_match,
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},
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},
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};
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};
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static int __init
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module_platform_driver(ltq_wdt_driver);
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init_ltq_wdt(void)
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{
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return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe);
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}
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static void __exit
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exit_ltq_wdt(void)
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{
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return platform_driver_unregister(<q_wdt_driver);
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}
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module_init(init_ltq_wdt);
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module_exit(exit_ltq_wdt);
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module_param(nowayout, bool, 0);
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
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MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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MODULE_DESCRIPTION("Lantiq SoC Watchdog");
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MODULE_DESCRIPTION("Lantiq SoC Watchdog");
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MODULE_LICENSE("GPL");
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MODULE_LICENSE("GPL");
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