dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
These global variables are integrated into the dmaengine structure. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Javier Martin
Vinod Koul
parent
a6cbb2d87d
commit
cd5cf9da02
1 changed files with 94 additions and 77 deletions
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@ -160,6 +160,8 @@ struct imxdma_engine {
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struct device *dev;
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struct device_dma_parameters dma_parms;
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struct dma_device dma_device;
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void __iomem *base;
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struct clk *dma_clk;
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struct imxdma_channel channel[IMX_DMA_CHANNELS];
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};
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@ -181,18 +183,17 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
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return false;
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}
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/* TODO: put this inside any struct */
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static void __iomem *imx_dmav1_baseaddr;
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static struct clk *dma_clk;
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static void imx_dmav1_writel(unsigned val, unsigned offset)
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static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
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unsigned offset)
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{
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__raw_writel(val, imx_dmav1_baseaddr + offset);
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__raw_writel(val, imxdma->base + offset);
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}
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static unsigned imx_dmav1_readl(unsigned offset)
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static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
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{
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return __raw_readl(imx_dmav1_baseaddr + offset);
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return __raw_readl(imxdma->base + offset);
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}
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static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
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@ -209,6 +210,7 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
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static inline int imxdma_sg_next(struct imxdma_desc *d)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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struct scatterlist *sg = d->sg;
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unsigned long now;
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@ -217,17 +219,19 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
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d->len -= now;
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if (d->direction == DMA_DEV_TO_MEM)
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imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
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imx_dmav1_writel(imxdma, sg->dma_address,
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DMA_DAR(imxdmac->channel));
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else
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imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(imxdma, sg->dma_address,
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DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
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imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
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pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
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"size 0x%08x\n", imxdmac->channel,
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imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
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imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
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imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
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imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
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imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
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imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
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return now;
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}
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@ -235,6 +239,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
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static void imxdma_enable_hw(struct imxdma_desc *d)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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int channel = imxdmac->channel;
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unsigned long flags;
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@ -242,10 +247,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
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local_irq_save(flags);
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imx_dmav1_writel(1 << channel, DMA_DISR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
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CCR_ACRPT, DMA_CCR(channel));
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imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
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imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
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~(1 << channel), DMA_DIMR);
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imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
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CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
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if ((cpu_is_mx21() || cpu_is_mx27()) &&
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d->sg && imxdma_hw_chain(imxdmac)) {
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@ -253,9 +259,9 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
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if (d->sg) {
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u32 tmp;
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imxdma_sg_next(d);
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tmp = imx_dmav1_readl(DMA_CCR(channel));
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imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
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DMA_CCR(channel));
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tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
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imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
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DMA_CCR(channel));
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}
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}
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@ -264,6 +270,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
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static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
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{
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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int channel = imxdmac->channel;
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unsigned long flags;
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@ -273,19 +280,21 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
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del_timer(&imxdmac->watchdog);
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local_irq_save(flags);
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imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
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DMA_CCR(channel));
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imx_dmav1_writel(1 << channel, DMA_DISR);
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imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
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(1 << channel), DMA_DIMR);
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imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
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~CCR_CEN, DMA_CCR(channel));
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imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
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local_irq_restore(flags);
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}
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static void imxdma_watchdog(unsigned long data)
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{
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struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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int channel = imxdmac->channel;
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imx_dmav1_writel(0, DMA_CCR(channel));
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imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
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/* Tasklet watchdog error handler */
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tasklet_schedule(&imxdmac->dma_tasklet);
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@ -299,37 +308,37 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
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int i, disr;
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int errcode;
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disr = imx_dmav1_readl(DMA_DISR);
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disr = imx_dmav1_readl(imxdma, DMA_DISR);
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err_mask = imx_dmav1_readl(DMA_DBTOSR) |
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imx_dmav1_readl(DMA_DRTOSR) |
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imx_dmav1_readl(DMA_DSESR) |
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imx_dmav1_readl(DMA_DBOSR);
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err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
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imx_dmav1_readl(imxdma, DMA_DRTOSR) |
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imx_dmav1_readl(imxdma, DMA_DSESR) |
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imx_dmav1_readl(imxdma, DMA_DBOSR);
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if (!err_mask)
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return IRQ_HANDLED;
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imx_dmav1_writel(disr & err_mask, DMA_DISR);
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imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
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for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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if (!(err_mask & (1 << i)))
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continue;
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errcode = 0;
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if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DBTOSR);
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if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
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imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
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errcode |= IMX_DMA_ERR_BURST;
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}
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if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DRTOSR);
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if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
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imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
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errcode |= IMX_DMA_ERR_REQUEST;
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}
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if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DSESR);
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if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
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imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
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errcode |= IMX_DMA_ERR_TRANSFER;
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}
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if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
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imx_dmav1_writel(1 << i, DMA_DBOSR);
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if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
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imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
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errcode |= IMX_DMA_ERR_BUFFER;
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}
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/* Tasklet error handler */
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@ -347,6 +356,7 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
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static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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{
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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int chno = imxdmac->channel;
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struct imxdma_desc *desc;
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@ -368,7 +378,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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if (desc->sg) {
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imxdma_sg_next(desc);
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tmp = imx_dmav1_readl(DMA_CCR(chno));
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tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
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if (imxdma_hw_chain(imxdmac)) {
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/* FIXME: The timeout should probably be
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@ -378,13 +388,14 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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jiffies + msecs_to_jiffies(500));
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tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
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imx_dmav1_writel(tmp, DMA_CCR(chno));
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imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
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} else {
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imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
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imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
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DMA_CCR(chno));
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tmp |= CCR_CEN;
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}
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imx_dmav1_writel(tmp, DMA_CCR(chno));
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imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
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if (imxdma_chan_is_doing_cyclic(imxdmac))
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/* Tasklet progression */
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@ -400,7 +411,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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}
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out:
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imx_dmav1_writel(0, DMA_CCR(chno));
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imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
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/* Tasklet irq */
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tasklet_schedule(&imxdmac->dma_tasklet);
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}
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@ -413,12 +424,12 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
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if (cpu_is_mx21() || cpu_is_mx27())
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imxdma_err_handler(irq, dev_id);
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disr = imx_dmav1_readl(DMA_DISR);
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disr = imx_dmav1_readl(imxdma, DMA_DISR);
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pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
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disr);
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imx_dmav1_writel(disr, DMA_DISR);
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imx_dmav1_writel(imxdma, disr, DMA_DISR);
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for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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if (disr & (1 << i))
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dma_irq_handle_channel(&imxdma->channel[i]);
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@ -435,12 +446,12 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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/* Configure and enable */
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switch (d->type) {
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case IMXDMA_DESC_MEMCPY:
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imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
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imx_dmav1_writel(d->config_mem | (d->config_port << 2),
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imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
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imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
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DMA_CCR(imxdmac->channel));
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imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
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imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
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dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
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"dma_length=%d\n", __func__, imxdmac->channel,
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@ -451,9 +462,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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case IMXDMA_DESC_CYCLIC:
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case IMXDMA_DESC_SLAVE_SG:
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if (d->direction == DMA_DEV_TO_MEM) {
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imx_dmav1_writel(imxdmac->per_address,
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imx_dmav1_writel(imxdma, imxdmac->per_address,
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DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(imxdmac->ccr_from_device,
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imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
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DMA_CCR(imxdmac->channel));
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dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
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@ -461,9 +472,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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__func__, imxdmac->channel, d->sg, d->sgcount,
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d->len, imxdmac->per_address);
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} else if (d->direction == DMA_MEM_TO_DEV) {
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imx_dmav1_writel(imxdmac->per_address,
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imx_dmav1_writel(imxdma, imxdmac->per_address,
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DMA_DAR(imxdmac->channel));
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imx_dmav1_writel(imxdmac->ccr_to_device,
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imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
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DMA_CCR(imxdmac->channel));
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dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
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@ -528,6 +539,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct dma_slave_config *dmaengine_cfg = (void *)arg;
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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unsigned long flags;
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unsigned int mode = 0;
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@ -573,12 +585,12 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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imxdmac->ccr_to_device =
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(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
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((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
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imx_dmav1_writel(imxdmac->dma_request,
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imx_dmav1_writel(imxdma, imxdmac->dma_request,
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DMA_RSSR(imxdmac->channel));
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/* Set burst length */
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imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
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DMA_BLR(imxdmac->channel));
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imx_dmav1_writel(imxdma, imxdmac->watermark_level *
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imxdmac->word_size, DMA_BLR(imxdmac->channel));
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return 0;
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default:
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@ -836,27 +848,35 @@ static int __init imxdma_probe(struct platform_device *pdev)
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struct imxdma_engine *imxdma;
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int ret, i;
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if (cpu_is_mx1())
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imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
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else if (cpu_is_mx21())
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imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
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else if (cpu_is_mx27())
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imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
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else
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return 0;
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dma_clk = clk_get(NULL, "dma");
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if (IS_ERR(dma_clk))
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return PTR_ERR(dma_clk);
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clk_enable(dma_clk);
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imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
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if (!imxdma)
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return -ENOMEM;
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if (cpu_is_mx1()) {
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imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
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} else if (cpu_is_mx21()) {
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imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
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} else if (cpu_is_mx27()) {
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imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
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} else {
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kfree(imxdma);
|
||||
return 0;
|
||||
}
|
||||
|
||||
imxdma->dma_clk = clk_get(NULL, "dma");
|
||||
if (IS_ERR(imxdma->dma_clk))
|
||||
return PTR_ERR(imxdma->dma_clk);
|
||||
clk_enable(imxdma->dma_clk);
|
||||
|
||||
/* reset DMA module */
|
||||
imx_dmav1_writel(DCR_DRST, DMA_DCR);
|
||||
imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
|
||||
|
||||
if (cpu_is_mx1()) {
|
||||
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
|
||||
if (ret) {
|
||||
pr_crit("Can't register IRQ for DMA\n");
|
||||
kfree(imxdma);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -864,22 +884,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
|
|||
if (ret) {
|
||||
pr_crit("Can't register ERRIRQ for DMA\n");
|
||||
free_irq(MX1_DMA_INT, NULL);
|
||||
kfree(imxdma);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* enable DMA module */
|
||||
imx_dmav1_writel(DCR_DEN, DMA_DCR);
|
||||
imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
|
||||
|
||||
/* clear all interrupts */
|
||||
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
|
||||
imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
|
||||
|
||||
/* disable interrupts */
|
||||
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
|
||||
|
||||
imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
|
||||
if (!imxdma)
|
||||
return -ENOMEM;
|
||||
imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
|
||||
|
||||
INIT_LIST_HEAD(&imxdma->dma_device.channels);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue