sgiioc4: coding style cleanup
Fix several errors and warnings given by checkpatch.pl: - space between the asterisk and parameter name; - inconsistent spacing between operator and operands; - space between *sizeof* and open parenthesis; - #include <asm/io.h> instead of #include <linux/io.h> - use of *typedef* instead of a structure tag; - line over 80 characters. In addition to these changes, also do the following: - indent with tabs instead of spaces; - put the function's result type and name/parameters on the same line; - join back the needlessly broken lines; - get rid of needless type cast in sgiioc4_checkirq(); - remove space between the type cast and the variable name; - remove commented out field initializer; - uppercase the acronyms, lowercase the normal words in the comments; - fix up the multi-line comment style... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov
Bartlomiej Zolnierkiewicz
parent
5880b5de71
commit
ccae50bcf9
1 changed files with 54 additions and 65 deletions
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (C) 2008 MontaVista Software, Inc.
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* Copyright (C) 2008-2009 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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@ -29,8 +29,7 @@
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#include <linux/blkdev.h>
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#include <linux/scatterlist.h>
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#include <linux/ioc4.h>
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#include <asm/io.h>
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#include <linux/io.h>
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#include <linux/ide.h>
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#define DRV_NAME "SGIIOC4"
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@ -72,7 +71,7 @@
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#define IOC4_CMD_CTL_BLK_SIZE 0x20
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#define IOC4_SUPPORTED_FIRMWARE_REV 46
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typedef struct {
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struct ioc4_dma_regs {
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u32 timing_reg0;
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u32 timing_reg1;
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u32 low_mem_ptr;
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@ -82,17 +81,18 @@ typedef struct {
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u32 dev_byte_count;
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u32 mem_byte_count;
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u32 status;
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} ioc4_dma_regs_t;
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};
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/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
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/* IOC4 has only 1 IDE channel */
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#define IOC4_PRD_BYTES 16
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#define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
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#define IOC4_PRD_BYTES 16
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#define IOC4_PRD_ENTRIES (PAGE_SIZE / (4 * IOC4_PRD_BYTES))
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static void
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sgiioc4_init_hwif_ports(struct ide_hw *hw, unsigned long data_port,
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unsigned long ctrl_port, unsigned long irq_port)
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static void sgiioc4_init_hwif_ports(struct ide_hw *hw,
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unsigned long data_port,
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unsigned long ctrl_port,
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unsigned long irq_port)
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{
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unsigned long reg = data_port;
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int i;
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@ -105,13 +105,11 @@ sgiioc4_init_hwif_ports(struct ide_hw *hw, unsigned long data_port,
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hw->io_ports.irq_addr = irq_port;
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}
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static int
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sgiioc4_checkirq(ide_hwif_t * hwif)
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static int sgiioc4_checkirq(ide_hwif_t *hwif)
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{
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unsigned long intr_addr =
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hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
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unsigned long intr_addr = hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
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if ((u8)readl((void __iomem *)intr_addr) & 0x03)
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if (readl((void __iomem *)intr_addr) & 0x03)
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return 1;
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return 0;
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@ -119,8 +117,7 @@ sgiioc4_checkirq(ide_hwif_t * hwif)
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static u8 sgiioc4_read_status(ide_hwif_t *);
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static int
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sgiioc4_clearirq(ide_drive_t * drive)
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static int sgiioc4_clearirq(ide_drive_t *drive)
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{
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u32 intr_reg;
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ide_hwif_t *hwif = drive->hwif;
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@ -158,12 +155,10 @@ sgiioc4_clearirq(ide_drive_t * drive)
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readl((void __iomem *)(io_ports->irq_addr + 4));
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pci_read_config_dword(dev, PCI_COMMAND,
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&pci_stat_cmd_reg);
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printk(KERN_ERR
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"%s(%s) : PCI Bus Error when doing DMA:"
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" status-cmd reg is 0x%x\n",
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printk(KERN_ERR "%s(%s): PCI Bus Error when doing DMA: "
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"status-cmd reg is 0x%x\n",
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__func__, drive->name, pci_stat_cmd_reg);
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printk(KERN_ERR
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"%s(%s) : PCI Error Address is 0x%x%x\n",
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printk(KERN_ERR "%s(%s): PCI Error Address is 0x%x%x\n",
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__func__, drive->name,
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pci_err_addr_high, pci_err_addr_low);
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/* Clear the PCI Error indicator */
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@ -189,8 +184,7 @@ static void sgiioc4_dma_start(ide_drive_t *drive)
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writel(temp_reg, (void __iomem *)ioc4_dma_addr);
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}
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static u32
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sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
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static u32 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
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{
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unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
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u32 ioc4_dma;
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@ -227,7 +221,7 @@ static int sgiioc4_dma_end(ide_drive_t *drive)
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}
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/*
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* The IOC4 will DMA 1's to the ending dma area to indicate that
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* The IOC4 will DMA 1's to the ending DMA area to indicate that
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* previous data DMA is complete. This is necessary because of relaxed
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* ordering between register reads and DMA writes on the Altix.
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*/
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@ -265,7 +259,7 @@ static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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}
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/* returns 1 if dma irq issued, 0 otherwise */
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/* Returns 1 if DMA IRQ issued, 0 otherwise */
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static int sgiioc4_dma_test_irq(ide_drive_t *drive)
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{
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return sgiioc4_checkirq(drive->hwif);
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@ -286,8 +280,7 @@ static void sgiioc4_resetproc(ide_drive_t *drive)
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sgiioc4_clearirq(drive);
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}
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static void
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sgiioc4_dma_lost_irq(ide_drive_t * drive)
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static void sgiioc4_dma_lost_irq(ide_drive_t *drive)
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{
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sgiioc4_resetproc(drive);
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@ -313,13 +306,13 @@ static u8 sgiioc4_read_status(ide_hwif_t *hwif)
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return reg;
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}
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/* Creates a dma map for the scatter-gather list entries */
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static int __devinit
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ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
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/* Creates a DMA map for the scatter-gather list entries */
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static int __devinit ide_dma_sgiioc4(ide_hwif_t *hwif,
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const struct ide_port_info *d)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
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int num_ports = sizeof (ioc4_dma_regs_t);
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int num_ports = sizeof(struct ioc4_dma_regs);
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void *pad;
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printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
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@ -362,8 +355,7 @@ ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
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}
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/* Initializes the IOC4 DMA Engine */
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static void
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sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
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static void sgiioc4_configure_for_dma(int dma_direction, ide_drive_t *drive)
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{
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u32 ioc4_dma;
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ide_hwif_t *hwif = drive->hwif;
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@ -374,31 +366,27 @@ sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
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ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
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if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
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printk(KERN_WARNING
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"%s(%s):Warning!! DMA from previous transfer was still active\n",
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__func__, drive->name);
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printk(KERN_WARNING "%s(%s): Warning!! DMA from previous "
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"transfer was still active\n", __func__, drive->name);
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writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
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ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
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if (ioc4_dma & IOC4_S_DMA_STOP)
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printk(KERN_ERR
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"%s(%s) : IOC4 Dma STOP bit is still 1\n",
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__func__, drive->name);
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printk(KERN_ERR "%s(%s): IOC4 DMA STOP bit is "
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"still 1\n", __func__, drive->name);
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}
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ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
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if (ioc4_dma & IOC4_S_DMA_ERROR) {
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printk(KERN_WARNING
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"%s(%s) : Warning!! - DMA Error during Previous"
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" transfer | status 0x%x\n",
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printk(KERN_WARNING "%s(%s): Warning!! DMA Error during "
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"previous transfer, status 0x%x\n",
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__func__, drive->name, ioc4_dma);
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writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
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ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
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if (ioc4_dma & IOC4_S_DMA_STOP)
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printk(KERN_ERR
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"%s(%s) : IOC4 DMA STOP bit is still 1\n",
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__func__, drive->name);
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printk(KERN_ERR "%s(%s): IOC4 DMA STOP bit is "
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"still 1\n", __func__, drive->name);
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}
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/* Address of the Scatter Gather List */
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@ -408,20 +396,22 @@ sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
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/* Address of the Ending DMA */
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memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
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ending_dma_addr = cpu_to_le32(hwif->extra_base);
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writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
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writel(ending_dma_addr, (void __iomem *)(dma_base +
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IOC4_DMA_END_ADDR * 4));
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writel(dma_direction, (void __iomem *)ioc4_dma_addr);
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}
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/* IOC4 Scatter Gather list Format */
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/* IOC4 Scatter Gather list Format */
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/* 128 Bit entries to support 64 bit addresses in the future */
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/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
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/* --------------------------------------------------------------------- */
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/* | Upper 32 bits - Zero | Lower 32 bits- address | */
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/* | Upper 32 bits - Zero | Lower 32 bits- address | */
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/* --------------------------------------------------------------------- */
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/* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
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/* --------------------------------------------------------------------- */
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/* Creates the scatter gather list, DMA Table */
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/* Creates the scatter gather list, DMA Table */
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static int sgiioc4_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
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{
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ide_hwif_t *hwif = drive->hwif;
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@ -448,8 +438,10 @@ static int sgiioc4_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
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if (bcount > cur_len)
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bcount = cur_len;
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/* put the addr, length in
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* the IOC4 dma-table format */
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/*
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* Put the address, length in
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* the IOC4 dma-table format
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*/
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*table = 0x0;
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table++;
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*table = cpu_to_be32(cur_addr);
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@ -540,8 +532,7 @@ static const struct ide_port_info sgiioc4_port_info __devinitconst = {
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.mwdma_mask = ATA_MWDMA2_ONLY,
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};
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static int __devinit
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sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
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static int __devinit sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
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{
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unsigned long cmd_base, irqport;
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unsigned long bar0, cmd_phys_base, ctl;
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@ -549,7 +540,7 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
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struct ide_hw hw, *hws[] = { &hw };
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int rc;
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/* Get the CmdBlk and CtrlBlk Base Registers */
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/* Get the CmdBlk and CtrlBlk base registers */
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bar0 = pci_resource_start(dev, 0);
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virt_base = pci_ioremap_bar(dev, 0);
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if (virt_base == NULL) {
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@ -557,9 +548,9 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
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DRV_NAME, bar0);
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return -ENOMEM;
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}
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cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
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ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
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irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
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cmd_base = (unsigned long)virt_base + IOC4_CMD_OFFSET;
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ctl = (unsigned long)virt_base + IOC4_CTRL_OFFSET;
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irqport = (unsigned long)virt_base + IOC4_INTR_OFFSET;
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cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
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if (request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
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@ -577,7 +568,7 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
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hw.irq = dev->irq;
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hw.dev = &dev->dev;
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/* Initializing chipset IRQ Registers */
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/* Initialize chipset IRQ registers */
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writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
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rc = ide_host_add(&sgiioc4_port_info, hws, 1, NULL);
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@ -590,8 +581,7 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
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return rc;
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}
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static unsigned int __devinit
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pci_init_sgiioc4(struct pci_dev *dev)
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static unsigned int __devinit pci_init_sgiioc4(struct pci_dev *dev)
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{
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int ret;
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@ -611,10 +601,10 @@ pci_init_sgiioc4(struct pci_dev *dev)
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return ret;
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}
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int __devinit
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ioc4_ide_attach_one(struct ioc4_driver_data *idd)
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int __devinit ioc4_ide_attach_one(struct ioc4_driver_data *idd)
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{
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/* PCI-RT does not bring out IDE connection.
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/*
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* PCI-RT does not bring out IDE connection.
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* Do not attach to this particular IOC4.
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*/
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if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
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@ -627,7 +617,6 @@ static struct ioc4_submodule __devinitdata ioc4_ide_submodule = {
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.is_name = "IOC4_ide",
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.is_owner = THIS_MODULE,
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.is_probe = ioc4_ide_attach_one,
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/* .is_remove = ioc4_ide_remove_one, */
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};
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static int __init ioc4_ide_init(void)
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