s390/pci: uninline instruction wrappers
Uninline pci related instruction wrappers to de-bloat the code: add/remove: 15/0 grow/shrink: 2/24 up/down: 1326/-12628 (-11302) This is especially useful for the inlined pci read and write functions which are used all over the kernel. Also remove the unused __stpcifc while at it. Reviewed-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Sebastian Ott
Martin Schwidefsky
parent
af0a8a8453
commit
cbcca5d070
3 changed files with 202 additions and 199 deletions
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@ -1,10 +1,6 @@
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#ifndef _ASM_S390_PCI_INSN_H
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#define _ASM_S390_PCI_INSN_H
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#include <linux/delay.h>
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#define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
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/* Load/Store status codes */
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#define ZPCI_PCI_ST_FUNC_NOT_ENABLED 4
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#define ZPCI_PCI_ST_FUNC_IN_ERR 8
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@ -82,199 +78,12 @@ struct zpci_fib {
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u64 reserved7;
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} __packed;
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/* Modify PCI Function Controls */
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static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rxy,0xe300000000d0,%[req],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
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: : "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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static inline int mpcifc_instr(u64 req, struct zpci_fib *fib)
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{
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u8 cc, status;
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do {
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cc = __mpcifc(req, fib, &status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d\n",
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__func__, cc, status);
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return (cc) ? -EIO : 0;
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}
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/* Refresh PCI Translations */
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static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
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{
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register u64 __addr asm("2") = addr;
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register u64 __range asm("3") = range;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d30000,%[fn],%[addr]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn)
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: [addr] "d" (__addr), "d" (__range)
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: "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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}
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static inline int rpcit_instr(u64 fn, u64 addr, u64 range)
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{
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u8 cc, status;
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do {
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cc = __rpcit(fn, addr, range, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d dma_addr: %Lx size: %Lx\n",
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__func__, cc, status, addr, range);
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return (cc) ? -EIO : 0;
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}
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/* Store PCI function controls */
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static inline u8 __stpcifc(u32 handle, u8 space, struct zpci_fib *fib, u8 *status)
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{
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u64 fn = (u64) handle << 32 | space << 16;
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u8 cc;
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asm volatile (
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" .insn rxy,0xe300000000d4,%[fn],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn), [fib] "=m" (*fib)
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: : "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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}
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/* Set Interruption Controls */
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static inline void sic_instr(u16 ctl, char *unused, u8 isc)
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{
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asm volatile (
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" .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
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: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
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}
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/* PCI Load */
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static inline u8 __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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u64 __data;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d20000,%[data],%[req]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [data] "=d" (__data), [req] "+d" (__req)
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: "d" (__offset)
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: "cc");
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*status = __req >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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static inline int pcilg_instr(u64 *data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcilg(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc) {
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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/* TODO: on IO errors set data to 0xff...
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* here or in users of pcilg (le conversion)?
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*/
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}
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return (cc) ? -EIO : 0;
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}
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/* PCI Store */
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static inline u8 __pcistg(u64 data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d00000,%[data],%[req]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (__req)
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: "d" (__offset), [data] "d" (data)
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: "cc");
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*status = __req >> 24 & 0xff;
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return cc;
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}
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static inline int pcistg_instr(u64 data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcistg(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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return (cc) ? -EIO : 0;
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}
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/* PCI Store Block */
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static inline u8 __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req)
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: [offset] "d" (offset), [data] "Q" (*data)
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: "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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static inline int pcistb_instr(const u64 *data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcistb(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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return (cc) ? -EIO : 0;
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}
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int mpcifc_instr(u64 req, struct zpci_fib *fib);
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int rpcit_instr(u64 fn, u64 addr, u64 range);
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void sic_instr(u16 ctl, char *unused, u8 isc);
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int pcilg_instr(u64 *data, u64 req, u64 offset);
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int pcistg_instr(u64 data, u64 req, u64 offset);
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int pcistb_instr(const u64 *data, u64 req, u64 offset);
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#endif
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@ -2,5 +2,5 @@
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# Makefile for the s390 PCI subsystem.
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#
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obj-$(CONFIG_PCI) += pci.o pci_dma.o pci_clp.o pci_msi.o \
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pci_sysfs.o pci_event.o pci_debug.o
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obj-$(CONFIG_PCI) += pci.o pci_dma.o pci_clp.o pci_msi.o pci_sysfs.o \
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pci_event.o pci_debug.o pci_insn.o
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194
arch/s390/pci/pci_insn.c
Normal file
194
arch/s390/pci/pci_insn.c
Normal file
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@ -0,0 +1,194 @@
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/*
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* s390 specific pci instructions
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*
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* Copyright IBM Corp. 2013
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*/
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#include <linux/export.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <asm/pci_insn.h>
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#define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
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/* Modify PCI Function Controls */
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static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rxy,0xe300000000d0,%[req],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
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: : "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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int mpcifc_instr(u64 req, struct zpci_fib *fib)
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{
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u8 cc, status;
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do {
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cc = __mpcifc(req, fib, &status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d\n",
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__func__, cc, status);
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return (cc) ? -EIO : 0;
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}
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/* Refresh PCI Translations */
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static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
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{
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register u64 __addr asm("2") = addr;
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register u64 __range asm("3") = range;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d30000,%[fn],%[addr]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn)
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: [addr] "d" (__addr), "d" (__range)
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: "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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}
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int rpcit_instr(u64 fn, u64 addr, u64 range)
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{
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u8 cc, status;
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do {
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cc = __rpcit(fn, addr, range, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d dma_addr: %Lx size: %Lx\n",
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__func__, cc, status, addr, range);
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return (cc) ? -EIO : 0;
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}
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/* Set Interruption Controls */
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void sic_instr(u16 ctl, char *unused, u8 isc)
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{
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asm volatile (
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" .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
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: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
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}
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/* PCI Load */
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static inline u8 __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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u64 __data;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d20000,%[data],%[req]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [data] "=d" (__data), [req] "+d" (__req)
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: "d" (__offset)
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: "cc");
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*status = __req >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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int pcilg_instr(u64 *data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcilg(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc) {
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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/* TODO: on IO errors set data to 0xff...
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* here or in users of pcilg (le conversion)?
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*/
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}
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return (cc) ? -EIO : 0;
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}
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EXPORT_SYMBOL_GPL(pcilg_instr);
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/* PCI Store */
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static inline u8 __pcistg(u64 data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d00000,%[data],%[req]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (__req)
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: "d" (__offset), [data] "d" (data)
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: "cc");
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*status = __req >> 24 & 0xff;
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return cc;
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}
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int pcistg_instr(u64 data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcistg(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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return (cc) ? -EIO : 0;
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}
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EXPORT_SYMBOL_GPL(pcistg_instr);
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/* PCI Store Block */
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static inline u8 __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req)
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: [offset] "d" (offset), [data] "Q" (*data)
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: "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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int pcistb_instr(const u64 *data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcistb(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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return (cc) ? -EIO : 0;
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}
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EXPORT_SYMBOL_GPL(pcistb_instr);
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