Fixes, improvements and addition of some missing features
of the exynos7 clock controller driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJWDkyVAAoJEE1bIKeAnHqLvEgQAIzCTebVdKFwTesgN2Jo5S0Y +iEEbz6jM1mlcr3LreAPZXrAAE2phjuEYRIEDd5DCcx4VH3n/X/rM4zJSopxLBke zaJiuv2jB08vpxmt4O497j0UWQsuxBQSrJ4YMaGm7WHTxMLZZ5wX+1tDqUYn4IB7 sHZ63RUR+ny9pFl1ozs7y+nObuHc9UU1ornar5Yf6LYPOoRd4MAoNNwiePCor/DW qzkGcC1vemW1vRCSOve5rpRxu7vX/htuPjaqd+dX4c6vWZxoa2GPScwIGW4YjXdj bfgg3N1axret3cZb6vQDjmZJfb93oX5e54w/xlN47X2LuKT/66aok8+wCgpx/xYf IGoQCoDvGKEyMDDG+XMJZjPt6vA2UMSDZwXHnia4IF/4MY73Jt9BurDgBIC4DxPc 9kUtQ1skyYnVP7rB2vE7MaGNJSDrq97vfzEi913hvOpoaaH1xstEaRzTTauWLbl1 GWxY8ITlTnxTXLS2gwoMhzhO86tTrLj6HWIXsBwRkdcOI0rrp/sEYFXmLfjm/t8p MnpANR1g1Q1J8r2+wvK3PshNwv97VUaRJBaZUs2gXxSElYOXRJTGI1HqeCuzfcG/ 1/qVoKm+QcX9GybtJx7DT4/0q8490AFsSd9xU0IVJV/2Tw7ftTahncLDyQtsEIj2 zQPNJjPevSyG76mvNcA5 =x8YL -----END PGP SIGNATURE----- Merge tag 'clk-samsung-4.4' of git://linuxtv.org/snawrocki/samsung into clk-next Pull updates from Sylwester Nawrocki: "Fixes, improvements and addition of some missing features of the exynos7 clock controller driver." * tag 'clk-samsung-4.4' of git://linuxtv.org/snawrocki/samsung: clk: samsung: exynos7: Add required clock tree for UFS clk: samsung: exynos7: Add missing fixed_clks to cmu_info clk: samsung: exynos7: Correct CMU_FSYS1 clocks names clk: samsung: exynos7: Correct CMU_FSYS0 clocks names clk: samsung: exynos7: Correct CMU_PERIS clocks names clk: samsung: exynos7: Correct CMU_PERIC1 clocks names clk: samsung: exynos7: Correct CMU_PERIC0 clocks names clk: samsung: exynos7: Correct CMU_CCORE clocks names clk: samsung: exynos7: Correct CMU_TOP1 clocks names clk: samsung: exynos7: Correct CMU_TOP0 clocks names clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC clk: samsung: exynos7: Change the CMU_TOPC block clock names clk: samsung: exynos7: Correct nr_clk_ids for fsys1 clk: samsung: exynos7: Correct nr_clk_ids for fsys0 clk: samsung: exynos7: Fix CMU TOP1 block clk: samsung: exynos7: Fix CMU TOPC block clock
This commit is contained in:
Stephen Boyd
commit
caac0ef841
2 changed files with 356 additions and 150 deletions
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@ -32,39 +32,41 @@
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#define DIV_TOPC0 0x0600
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#define DIV_TOPC1 0x0604
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#define DIV_TOPC3 0x060C
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#define ENABLE_ACLK_TOPC0 0x0800
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#define ENABLE_ACLK_TOPC1 0x0804
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#define ENABLE_SCLK_TOPC1 0x0A04
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static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
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FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
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FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
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FFACTOR(0, "ffac_topc_bus0_pll_div4",
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"ffac_topc_bus0_pll_div2", 1, 2, 0),
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FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
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FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
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FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
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FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
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FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
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FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
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};
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/* List of parent clocks for Muxes in CMU_TOPC */
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PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
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PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
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PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
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PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
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PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
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PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
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PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
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PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
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PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
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PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
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PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
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"mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
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"mout_sclk_mfc_pll_cmuc" };
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PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
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"mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
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"mout_topc_mfc_pll_half" };
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PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
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PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
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"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
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PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
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PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
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"ffac_topc_bus1_pll_div2"};
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PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
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PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
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"ffac_topc_cc_pll_div2"};
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PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
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PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
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"ffac_topc_mfc_pll_div2"};
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PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
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PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
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"ffac_topc_bus0_pll_div2"};
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static unsigned long topc_clk_regs[] __initdata = {
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@ -88,23 +90,27 @@ static unsigned long topc_clk_regs[] __initdata = {
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};
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static struct samsung_mux_clock topc_mux_clks[] __initdata = {
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MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
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MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
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MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
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MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
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MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
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MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
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MUX_SEL_TOPC0, 0, 1),
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MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
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MUX_SEL_TOPC0, 4, 1),
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MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
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MUX_SEL_TOPC0, 8, 1),
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MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
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MUX_SEL_TOPC0, 12, 1),
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MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
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MUX_SEL_TOPC0, 16, 2),
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MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
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MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
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MUX_SEL_TOPC0, 20, 1),
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MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
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MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
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MUX_SEL_TOPC0, 24, 1),
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MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
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MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
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MUX_SEL_TOPC0, 28, 1),
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MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
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MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
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MUX_SEL_TOPC1, 0, 1),
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MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
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MUX_SEL_TOPC1, 16, 1),
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MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
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MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
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@ -121,16 +127,16 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
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DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
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DIV_TOPC1, 24, 4),
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DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
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DIV_TOPC3, 0, 3),
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DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
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DIV_TOPC3, 8, 3),
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DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
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DIV_TOPC3, 12, 3),
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DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
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DIV_TOPC3, 16, 3),
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DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
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DIV_TOPC3, 28, 3),
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DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
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DIV_TOPC3, 0, 4),
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DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
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DIV_TOPC3, 8, 4),
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DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
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DIV_TOPC3, 12, 4),
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DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
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DIV_TOPC3, 16, 4),
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DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
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DIV_TOPC3, 28, 4),
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};
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static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
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@ -139,8 +145,33 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
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};
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static struct samsung_gate_clock topc_gate_clks[] __initdata = {
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GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
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ENABLE_ACLK_TOPC0, 4, 0, 0),
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GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
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ENABLE_ACLK_TOPC1, 20, 0, 0),
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GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
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ENABLE_ACLK_TOPC1, 24, 0, 0),
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GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
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ENABLE_SCLK_TOPC1, 20, 0, 0),
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GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
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ENABLE_SCLK_TOPC1, 17, 0, 0),
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GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
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ENABLE_SCLK_TOPC1, 16, 0, 0),
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GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
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ENABLE_SCLK_TOPC1, 13, 0, 0),
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GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
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ENABLE_SCLK_TOPC1, 12, 0, 0),
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GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
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ENABLE_SCLK_TOPC1, 5, 0, 0),
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GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
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ENABLE_SCLK_TOPC1, 4, 0, 0),
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GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
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ENABLE_SCLK_TOPC1, 1, 0, 0),
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GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
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ENABLE_SCLK_TOPC1, 0, 0, 0),
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};
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static struct samsung_pll_clock topc_pll_clks[] __initdata = {
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@ -193,36 +224,37 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
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#define DIV_TOP0_PERIC1 0x0634
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#define DIV_TOP0_PERIC2 0x0638
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#define DIV_TOP0_PERIC3 0x063C
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#define ENABLE_ACLK_TOP03 0x080C
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#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
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#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
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#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
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#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
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/* List of parent clocks for Muxes in CMU_TOP0 */
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PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
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PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
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PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
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PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
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PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" };
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PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" };
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PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" };
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PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" };
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PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
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PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
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PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
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PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
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"ffac_top0_bus0_pll_div2"};
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PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
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PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
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"ffac_top0_bus1_pll_div2"};
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PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
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PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
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"ffac_top0_cc_pll_div2"};
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PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
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PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
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"ffac_top0_mfc_pll_div2"};
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PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
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"mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
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"mout_top0_half_mfc_pll"};
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PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
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"mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
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"mout_top0_mfc_pll_half"};
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PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
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"ioclk_audiocdclk1", "ioclk_spdif_extclk",
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"mout_top0_aud_pll", "mout_top0_half_bus0_pll",
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"mout_top0_half_bus1_pll"};
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PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
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"mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
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"mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
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"mout_top0_bus1_pll_half"};
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PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
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"mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
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static unsigned long top0_clk_regs[] __initdata = {
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MUX_SEL_TOP00,
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@ -244,19 +276,24 @@ static unsigned long top0_clk_regs[] __initdata = {
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};
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static struct samsung_mux_clock top0_mux_clks[] __initdata = {
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MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
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MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
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MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
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MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
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MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
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MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
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MUX_SEL_TOP00, 0, 1),
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MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
|
||||
MUX_SEL_TOP00, 4, 1),
|
||||
MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
|
||||
MUX_SEL_TOP00, 8, 1),
|
||||
MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
|
||||
MUX_SEL_TOP00, 12, 1),
|
||||
MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
|
||||
MUX_SEL_TOP00, 16, 1),
|
||||
|
||||
MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
|
||||
MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
|
||||
MUX_SEL_TOP01, 4, 1),
|
||||
MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
|
||||
MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
|
||||
MUX_SEL_TOP01, 8, 1),
|
||||
MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
|
||||
MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
|
||||
MUX_SEL_TOP01, 12, 1),
|
||||
MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
|
||||
MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
|
||||
MUX_SEL_TOP01, 16, 1),
|
||||
|
||||
MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
|
||||
|
|
@ -302,6 +339,11 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
|
|||
};
|
||||
|
||||
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
|
||||
GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
|
||||
ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
|
||||
ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
|
||||
ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
|
||||
|
|
@ -331,10 +373,12 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
|
|||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
|
||||
1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
|
||||
1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info top0_cmu_info __initdata = {
|
||||
|
|
@ -365,31 +409,34 @@ CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
|
|||
#define MUX_SEL_TOP13 0x020C
|
||||
#define MUX_SEL_TOP1_FSYS0 0x0224
|
||||
#define MUX_SEL_TOP1_FSYS1 0x0228
|
||||
#define MUX_SEL_TOP1_FSYS11 0x022C
|
||||
#define DIV_TOP13 0x060C
|
||||
#define DIV_TOP1_FSYS0 0x0624
|
||||
#define DIV_TOP1_FSYS1 0x0628
|
||||
#define DIV_TOP1_FSYS11 0x062C
|
||||
#define ENABLE_ACLK_TOP13 0x080C
|
||||
#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
|
||||
#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
|
||||
#define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP1 */
|
||||
PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
|
||||
PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" };
|
||||
PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
|
||||
PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
|
||||
PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" };
|
||||
PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" };
|
||||
PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" };
|
||||
PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
|
||||
|
||||
PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
|
||||
PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
|
||||
"ffac_top1_bus0_pll_div2"};
|
||||
PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
|
||||
PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
|
||||
"ffac_top1_bus1_pll_div2"};
|
||||
PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
|
||||
PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
|
||||
"ffac_top1_cc_pll_div2"};
|
||||
PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
|
||||
PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
|
||||
"ffac_top1_mfc_pll_div2"};
|
||||
|
||||
PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
|
||||
"mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
|
||||
"mout_top1_half_mfc_pll"};
|
||||
PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
|
||||
"mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
|
||||
"mout_top1_mfc_pll_half"};
|
||||
|
||||
static unsigned long top1_clk_regs[] __initdata = {
|
||||
MUX_SEL_TOP10,
|
||||
|
|
@ -397,40 +444,54 @@ static unsigned long top1_clk_regs[] __initdata = {
|
|||
MUX_SEL_TOP13,
|
||||
MUX_SEL_TOP1_FSYS0,
|
||||
MUX_SEL_TOP1_FSYS1,
|
||||
MUX_SEL_TOP1_FSYS11,
|
||||
DIV_TOP13,
|
||||
DIV_TOP1_FSYS0,
|
||||
DIV_TOP1_FSYS1,
|
||||
DIV_TOP1_FSYS11,
|
||||
ENABLE_ACLK_TOP13,
|
||||
ENABLE_SCLK_TOP1_FSYS0,
|
||||
ENABLE_SCLK_TOP1_FSYS1,
|
||||
ENABLE_SCLK_TOP1_FSYS11,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock top1_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
|
||||
MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
|
||||
MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
|
||||
MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
|
||||
MUX_SEL_TOP10, 4, 1),
|
||||
MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
|
||||
MUX_SEL_TOP10, 8, 1),
|
||||
MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
|
||||
MUX_SEL_TOP10, 12, 1),
|
||||
MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
|
||||
MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
|
||||
MUX_SEL_TOP10, 16, 1),
|
||||
|
||||
MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
|
||||
MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
|
||||
MUX_SEL_TOP11, 4, 1),
|
||||
MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
|
||||
MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
|
||||
MUX_SEL_TOP11, 8, 1),
|
||||
MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
|
||||
MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
|
||||
MUX_SEL_TOP11, 12, 1),
|
||||
MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
|
||||
MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
|
||||
MUX_SEL_TOP11, 16, 1),
|
||||
|
||||
MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
|
||||
MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
|
||||
|
||||
MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
|
||||
MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
|
||||
MUX_SEL_TOP1_FSYS0, 0, 2),
|
||||
MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
|
||||
MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
|
||||
MUX_SEL_TOP1_FSYS0, 28, 2),
|
||||
|
||||
MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
|
||||
MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
|
||||
MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
|
||||
MUX_SEL_TOP1_FSYS1, 0, 2),
|
||||
MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
|
||||
MUX_SEL_TOP1_FSYS1, 16, 2),
|
||||
|
||||
MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
|
||||
MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
|
||||
MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
|
||||
MUX_SEL_TOP1_FSYS11, 24, 2),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock top1_div_clks[] __initdata = {
|
||||
|
|
@ -439,34 +500,61 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
|
|||
DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
|
||||
DIV_TOP13, 28, 4),
|
||||
|
||||
DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
|
||||
"mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
|
||||
|
||||
DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
|
||||
"mout_sclk_ufsunipro20",
|
||||
DIV_TOP1_FSYS1, 16, 6),
|
||||
|
||||
DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
|
||||
DIV_TOP1_FSYS0, 24, 4),
|
||||
DIV_TOP1_FSYS0, 16, 10),
|
||||
DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
|
||||
DIV_TOP1_FSYS0, 28, 4),
|
||||
|
||||
DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
|
||||
DIV_TOP1_FSYS1, 24, 4),
|
||||
DIV_TOP1_FSYS11, 0, 10),
|
||||
DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
|
||||
DIV_TOP1_FSYS1, 28, 4),
|
||||
DIV_TOP1_FSYS11, 12, 10),
|
||||
|
||||
DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
|
||||
"mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock top1_gate_clks[] __initdata = {
|
||||
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
|
||||
ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
|
||||
ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
|
||||
ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
|
||||
|
||||
GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
|
||||
ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
|
||||
ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
|
||||
ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
|
||||
ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
|
||||
ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
|
||||
ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
|
||||
ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
|
||||
ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
|
||||
"dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
|
||||
24, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
|
||||
1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
|
||||
1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info top1_cmu_info __initdata = {
|
||||
|
|
@ -501,7 +589,7 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
|
|||
/*
|
||||
* List of parent clocks for Muxes in CMU_CCORE
|
||||
*/
|
||||
PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" };
|
||||
PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
|
||||
|
||||
static unsigned long ccore_clk_regs[] __initdata = {
|
||||
MUX_SEL_CCORE,
|
||||
|
|
@ -509,7 +597,7 @@ static unsigned long ccore_clk_regs[] __initdata = {
|
|||
};
|
||||
|
||||
static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
|
||||
MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
|
||||
MUX_SEL_CCORE, 1, 1),
|
||||
};
|
||||
|
||||
|
|
@ -542,8 +630,8 @@ CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
|
|||
#define ENABLE_SCLK_PERIC0 0x0A00
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIC0 */
|
||||
PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" };
|
||||
PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" };
|
||||
PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
|
||||
PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
|
||||
|
||||
static unsigned long peric0_clk_regs[] __initdata = {
|
||||
MUX_SEL_PERIC0,
|
||||
|
|
@ -552,9 +640,9 @@ static unsigned long peric0_clk_regs[] __initdata = {
|
|||
};
|
||||
|
||||
static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
|
||||
MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
|
||||
MUX_SEL_PERIC0, 0, 1),
|
||||
MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
|
||||
MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
|
||||
MUX_SEL_PERIC0, 16, 1),
|
||||
};
|
||||
|
||||
|
|
@ -611,15 +699,15 @@ CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
|
|||
exynos7_clk_peric0_init);
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIC1 */
|
||||
PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
|
||||
PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
|
||||
PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
|
||||
PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
|
||||
PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
|
||||
PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
|
||||
PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
|
||||
PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
|
||||
PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
|
||||
PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
|
||||
PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
|
||||
PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
|
||||
PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
|
||||
PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
|
||||
PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
|
||||
PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
|
||||
PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
|
||||
PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
|
||||
|
||||
static unsigned long peric1_clk_regs[] __initdata = {
|
||||
MUX_SEL_PERIC10,
|
||||
|
|
@ -630,24 +718,24 @@ static unsigned long peric1_clk_regs[] __initdata = {
|
|||
};
|
||||
|
||||
static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
|
||||
MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
|
||||
MUX_SEL_PERIC10, 0, 1),
|
||||
|
||||
MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
|
||||
MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
|
||||
MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
|
||||
MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
|
||||
MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
|
||||
MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
|
||||
MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
|
||||
MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
|
||||
MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
|
||||
MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
|
||||
MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
|
||||
MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
|
||||
MUX_SEL_PERIC11, 20, 1),
|
||||
MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
|
||||
MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
|
||||
MUX_SEL_PERIC11, 24, 1),
|
||||
MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
|
||||
MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
|
||||
MUX_SEL_PERIC11, 28, 1),
|
||||
};
|
||||
|
||||
|
|
@ -735,7 +823,7 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
|
|||
#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIS */
|
||||
PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
|
||||
PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
|
||||
|
||||
static unsigned long peris_clk_regs[] __initdata = {
|
||||
MUX_SEL_PERIS,
|
||||
|
|
@ -747,7 +835,7 @@ static unsigned long peris_clk_regs[] __initdata = {
|
|||
|
||||
static struct samsung_mux_clock peris_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_peris_66_user",
|
||||
mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
|
||||
mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
|
||||
|
|
@ -795,13 +883,13 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
|
|||
/*
|
||||
* List of parent clocks for Muxes in CMU_FSYS0
|
||||
*/
|
||||
PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
|
||||
PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
|
||||
PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" };
|
||||
PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" };
|
||||
|
||||
PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" };
|
||||
PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll",
|
||||
PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" };
|
||||
PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll",
|
||||
"phyclk_usbdrd300_udrd30_phyclock" };
|
||||
PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
|
||||
PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
|
||||
"phyclk_usbdrd300_udrd30_pipe_pclk" };
|
||||
|
||||
/* fixed rate clocks used in the FSYS0 block */
|
||||
|
|
@ -824,29 +912,30 @@ static unsigned long fsys0_clk_regs[] __initdata = {
|
|||
};
|
||||
|
||||
static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
|
||||
MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
|
||||
MUX_SEL_FSYS00, 24, 1),
|
||||
|
||||
MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
|
||||
MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
|
||||
MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
|
||||
MUX_SEL_FSYS01, 24, 1),
|
||||
MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
|
||||
MUX_SEL_FSYS01, 28, 1),
|
||||
|
||||
MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
|
||||
mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
|
||||
mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
|
||||
MUX_SEL_FSYS02, 24, 1),
|
||||
MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
|
||||
mout_phyclk_usbdrd300_udrd30_phyclk_p,
|
||||
mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
|
||||
MUX_SEL_FSYS02, 28, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
|
||||
GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
|
||||
"mout_aclk_fsys0_200_user",
|
||||
ENABLE_ACLK_FSYS00, 19, 0, 0),
|
||||
GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
|
||||
ENABLE_ACLK_FSYS00, 3, 0, 0),
|
||||
GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
|
||||
ENABLE_ACLK_FSYS00, 4, 0, 0),
|
||||
GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
|
||||
"mout_aclk_fsys0_200_user",
|
||||
ENABLE_ACLK_FSYS00, 19, 0, 0),
|
||||
|
||||
GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
|
||||
ENABLE_ACLK_FSYS01, 29, 0, 0),
|
||||
|
|
@ -874,11 +963,13 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
|
|||
};
|
||||
|
||||
static struct samsung_cmu_info fsys0_cmu_info __initdata = {
|
||||
.fixed_clks = fixed_rate_clks_fsys0,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
|
||||
.mux_clks = fsys0_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
|
||||
.gate_clks = fsys0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
|
||||
.nr_clk_ids = TOP1_NR_CLK,
|
||||
.nr_clk_ids = FSYS0_NR_CLK,
|
||||
.clk_regs = fsys0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
|
||||
};
|
||||
|
|
@ -894,42 +985,122 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
|
|||
/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
|
||||
#define MUX_SEL_FSYS10 0x0200
|
||||
#define MUX_SEL_FSYS11 0x0204
|
||||
#define MUX_SEL_FSYS12 0x0208
|
||||
#define DIV_FSYS1 0x0600
|
||||
#define ENABLE_ACLK_FSYS1 0x0800
|
||||
#define ENABLE_PCLK_FSYS1 0x0900
|
||||
#define ENABLE_SCLK_FSYS11 0x0A04
|
||||
#define ENABLE_SCLK_FSYS12 0x0A08
|
||||
#define ENABLE_SCLK_FSYS13 0x0A0C
|
||||
|
||||
/*
|
||||
* List of parent clocks for Muxes in CMU_FSYS1
|
||||
*/
|
||||
PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
|
||||
PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
|
||||
PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
|
||||
PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
|
||||
PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m",
|
||||
"sclk_phy_fsys1_26m" };
|
||||
PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
|
||||
PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
|
||||
PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" };
|
||||
PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
|
||||
PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
|
||||
PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
|
||||
|
||||
/* fixed rate clocks used in the FSYS1 block */
|
||||
struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
|
||||
FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
|
||||
CLK_IS_ROOT, 300000000),
|
||||
FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
|
||||
CLK_IS_ROOT, 300000000),
|
||||
FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
|
||||
CLK_IS_ROOT, 300000000),
|
||||
};
|
||||
|
||||
static unsigned long fsys1_clk_regs[] __initdata = {
|
||||
MUX_SEL_FSYS10,
|
||||
MUX_SEL_FSYS11,
|
||||
MUX_SEL_FSYS12,
|
||||
DIV_FSYS1,
|
||||
ENABLE_ACLK_FSYS1,
|
||||
ENABLE_PCLK_FSYS1,
|
||||
ENABLE_SCLK_FSYS11,
|
||||
ENABLE_SCLK_FSYS12,
|
||||
ENABLE_SCLK_FSYS13,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
|
||||
MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
|
||||
mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
|
||||
MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
|
||||
MUX_SEL_FSYS10, 20, 2),
|
||||
MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
|
||||
MUX_SEL_FSYS10, 28, 1),
|
||||
|
||||
MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
|
||||
MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
|
||||
MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
|
||||
MUX_SEL_FSYS11, 24, 1),
|
||||
MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
|
||||
MUX_SEL_FSYS11, 28, 1),
|
||||
MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
|
||||
MUX_SEL_FSYS11, 20, 1),
|
||||
|
||||
MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
|
||||
mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
|
||||
MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
|
||||
mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
|
||||
MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
|
||||
mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock fsys1_div_clks[] __initdata = {
|
||||
DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
|
||||
DIV_FSYS1, 0, 2),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
|
||||
GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
|
||||
"mout_sclk_ufsunipro20_user",
|
||||
ENABLE_SCLK_FSYS11, 20, 0, 0),
|
||||
|
||||
GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
|
||||
ENABLE_ACLK_FSYS1, 29, 0, 0),
|
||||
GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
|
||||
ENABLE_ACLK_FSYS1, 30, 0, 0),
|
||||
|
||||
GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
|
||||
ENABLE_ACLK_FSYS1, 31, 0, 0),
|
||||
GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
|
||||
ENABLE_PCLK_FSYS1, 30, 0, 0),
|
||||
|
||||
GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
|
||||
"mout_phyclk_ufs20_rx1_symbol_user",
|
||||
ENABLE_SCLK_FSYS12, 16, 0, 0),
|
||||
GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
|
||||
"mout_phyclk_ufs20_rx0_symbol_user",
|
||||
ENABLE_SCLK_FSYS12, 24, 0, 0),
|
||||
GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
|
||||
"mout_phyclk_ufs20_tx0_symbol_user",
|
||||
ENABLE_SCLK_FSYS12, 28, 0, 0),
|
||||
|
||||
GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
|
||||
"oscclk_phy_clkout_embedded_combo_phy",
|
||||
"fin_pll",
|
||||
ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
|
||||
"mout_fsys1_phyclk_sel1",
|
||||
ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info fsys1_cmu_info __initdata = {
|
||||
.fixed_clks = fixed_rate_clks_fsys1,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
|
||||
.mux_clks = fsys1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
|
||||
.div_clks = fsys1_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
|
||||
.gate_clks = fsys1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
|
||||
.nr_clk_ids = TOP1_NR_CLK,
|
||||
.nr_clk_ids = FSYS1_NR_CLK,
|
||||
.clk_regs = fsys1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,7 +21,18 @@
|
|||
#define ACLK_MSCL_532 8
|
||||
#define DOUT_SCLK_AUD_PLL 9
|
||||
#define FOUT_AUD_PLL 10
|
||||
#define TOPC_NR_CLK 11
|
||||
#define SCLK_AUD_PLL 11
|
||||
#define SCLK_MFC_PLL_B 12
|
||||
#define SCLK_MFC_PLL_A 13
|
||||
#define SCLK_BUS1_PLL_B 14
|
||||
#define SCLK_BUS1_PLL_A 15
|
||||
#define SCLK_BUS0_PLL_B 16
|
||||
#define SCLK_BUS0_PLL_A 17
|
||||
#define SCLK_CC_PLL_B 18
|
||||
#define SCLK_CC_PLL_A 19
|
||||
#define ACLK_CCORE_133 20
|
||||
#define ACLK_PERIS_66 21
|
||||
#define TOPC_NR_CLK 22
|
||||
|
||||
/* TOP0 */
|
||||
#define DOUT_ACLK_PERIC1 1
|
||||
|
|
@ -38,7 +49,9 @@
|
|||
#define CLK_SCLK_SPDIF 12
|
||||
#define CLK_SCLK_PCM1 13
|
||||
#define CLK_SCLK_I2S1 14
|
||||
#define TOP0_NR_CLK 15
|
||||
#define CLK_ACLK_PERIC0_66 15
|
||||
#define CLK_ACLK_PERIC1_66 16
|
||||
#define TOP0_NR_CLK 17
|
||||
|
||||
/* TOP1 */
|
||||
#define DOUT_ACLK_FSYS1_200 1
|
||||
|
|
@ -49,7 +62,16 @@
|
|||
#define CLK_SCLK_MMC2 6
|
||||
#define CLK_SCLK_MMC1 7
|
||||
#define CLK_SCLK_MMC0 8
|
||||
#define TOP1_NR_CLK 9
|
||||
#define CLK_ACLK_FSYS0_200 9
|
||||
#define CLK_ACLK_FSYS1_200 10
|
||||
#define CLK_SCLK_PHY_FSYS1 11
|
||||
#define CLK_SCLK_PHY_FSYS1_26M 12
|
||||
#define MOUT_SCLK_UFSUNIPRO20 13
|
||||
#define DOUT_SCLK_UFSUNIPRO20 14
|
||||
#define CLK_SCLK_UFSUNIPRO20 15
|
||||
#define DOUT_SCLK_PHY_FSYS1 16
|
||||
#define DOUT_SCLK_PHY_FSYS1_26M 17
|
||||
#define TOP1_NR_CLK 18
|
||||
|
||||
/* CCORE */
|
||||
#define PCLK_RTC 1
|
||||
|
|
@ -124,7 +146,20 @@
|
|||
/* FSYS1 */
|
||||
#define ACLK_MMC1 1
|
||||
#define ACLK_MMC0 2
|
||||
#define FSYS1_NR_CLK 3
|
||||
#define PHYCLK_UFS20_TX0_SYMBOL 3
|
||||
#define PHYCLK_UFS20_RX0_SYMBOL 4
|
||||
#define PHYCLK_UFS20_RX1_SYMBOL 5
|
||||
#define ACLK_UFS20_LINK 6
|
||||
#define SCLK_UFSUNIPRO20_USER 7
|
||||
#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
|
||||
#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
|
||||
#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
|
||||
#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
|
||||
#define SCLK_COMBO_PHY_EMBEDDED_26M 12
|
||||
#define DOUT_PCLK_FSYS1 13
|
||||
#define PCLK_GPIO_FSYS1 14
|
||||
#define MOUT_FSYS1_PHYCLK_SEL1 15
|
||||
#define FSYS1_NR_CLK 16
|
||||
|
||||
/* MSCL */
|
||||
#define USERMUX_ACLK_MSCL_532 1
|
||||
|
|
|
|||
Loading…
Reference in a new issue