[IA64] Fix IOSAPIC delivery mode setting
Fix the problem that redirect hit bit in I/O SAPIC RTE is set even when it must be disabled (e.g. nointroute boot option is set, CPU hotplug is enabled or percpu vector is enabled). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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1 changed files with 15 additions and 3 deletions
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@ -748,6 +748,15 @@ get_target_cpu (unsigned int gsi, int irq)
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#endif
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#endif
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}
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}
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static inline unsigned char choose_dmode(void)
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{
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#ifdef CONFIG_SMP
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if (smp_int_redirect & SMP_IRQ_REDIRECTION)
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return IOSAPIC_LOWEST_PRIORITY;
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#endif
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return IOSAPIC_FIXED;
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}
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/*
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/*
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* ACPI can describe IOSAPIC interrupts via static tables and namespace
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* ACPI can describe IOSAPIC interrupts via static tables and namespace
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* methods. This provides an interface to register those interrupts and
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* methods. This provides an interface to register those interrupts and
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@ -762,6 +771,7 @@ iosapic_register_intr (unsigned int gsi,
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unsigned long flags;
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unsigned long flags;
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struct iosapic_rte_info *rte;
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struct iosapic_rte_info *rte;
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u32 low32;
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u32 low32;
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unsigned char dmode;
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/*
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/*
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* If this GSI has already been registered (i.e., it's a
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* If this GSI has already been registered (i.e., it's a
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@ -791,8 +801,8 @@ iosapic_register_intr (unsigned int gsi,
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spin_lock(&irq_desc[irq].lock);
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spin_lock(&irq_desc[irq].lock);
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dest = get_target_cpu(gsi, irq);
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dest = get_target_cpu(gsi, irq);
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err = register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY,
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dmode = choose_dmode();
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polarity, trigger);
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err = register_intr(gsi, irq, dmode, polarity, trigger);
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if (err < 0) {
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if (err < 0) {
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spin_unlock(&irq_desc[irq].lock);
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spin_unlock(&irq_desc[irq].lock);
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irq = err;
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irq = err;
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@ -961,10 +971,12 @@ iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
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{
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{
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int vector, irq;
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int vector, irq;
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unsigned int dest = cpu_physical_id(smp_processor_id());
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unsigned int dest = cpu_physical_id(smp_processor_id());
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unsigned char dmode;
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irq = vector = isa_irq_to_vector(isa_irq);
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irq = vector = isa_irq_to_vector(isa_irq);
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BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
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BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
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register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
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dmode = choose_dmode();
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register_intr(gsi, irq, dmode, polarity, trigger);
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DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
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DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
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isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
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isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
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